JP3488250B2 - Serial data communication method - Google Patents

Description

BACKGROUND OF THE INVENTION [0001] BACKGROUND OF THE INVENTION This invention relates to serial data communication method for sending serial data from a master device to a plurality of slave devices, in particular, substantially three Serial data communication in which a master device specifies a slave device to transmit data to and transmits serial data to a plurality of slave devices simultaneously, and the specified slave device receives received serial data using a cable About the method. 2. Description of the Related Art As a method of transmitting (communicating) data with a small number of cables, there is a serial data communication system. FIG. 4 shows a conventional configuration example of such a serial data communication system.
Shown in In this serial data communication system, an arithmetic and control unit (CPU) 21 of a microcomputer, a first integrated circuit (IC) 22 and a second IC 23 are connected via a plurality of cables 24 each having two wires. .
This serial data transmission method is a communication method in which serial data is sent from the CPU 21 to the first IC 22 or the second IC 23 in one direction. FIG. 5 shows a timing chart of the data transmission. When transmitting serial data from the CPU 21 to the first IC 22, the CPU 21 outputs a clock CLK together with the serial data DATA from the serial data output terminal SDO and the clock output terminal CLK. The serial data input terminal SDI and the clock input terminal CLK of the first IC 22 and the second IC 23 are connected to the serial data DAT from the CPU 21.
A and the clock CLK are input, and the first IC 22 and the second IC 23
Enter A. However, the serial data DATA
Is only entered temporarily, and is not formally captured and output externally. When the transmission of the serial data DATA is completed, the CPU 21 outputs a load signal LOAD to the first IC 22 from the load signal output terminal LD1. When the first IC 22 receives the load signal LOAD at its load signal input terminal LOAD, it formalizes the input serial data DATA and outputs it externally. On the other hand, when the load signal LOAD is not input, the second
Does not formally take in the input serial data DATA. FIG. 6 shows a configuration of another conventional serial data communication system. This serial data communication system uses a CPU
25, the first IC 22, and the second IC 23 are connected by three cables. Here, the serial data output terminal SDO of the first IC 22 and the serial data input terminal SDI of the next second IC 23 are connected. Second
The same applies to ICs (not shown) following IC23. FIG. 7 shows the first IC 22 and the second IC 22 from the CPU 25 of FIG.
FIG. 5 is a timing chart for transmitting serial data DATA to the IC 23 and a third IC (not shown). CPU2
5 , serial data DATA for three ICs
3 to output data DATA1 together with the clock CLK. These serial data DATA3 to data DAT
A1 is sequentially input via the first IC 22 and the second IC 23, and is output to the third IC. When three serial data DATA3 to DATA1 are transmitted, C
The PU 25 outputs a pulse-like load signal LOAD.
This load signal LOAD is transmitted from the first IC 22 to the third IC 22.
At the same time, and each IC receives the load signal LOA.
At the time when D is input, the serial data DATA temporarily input to its own IC is formally taken in and output to the outside. [0004] In the serial data communication system shown in FIG.
In addition to the necessity of a cable for outputting the load signal LOAD by the number of C, there is a problem that the CPU 21 must be provided with terminals of the same number of cables. Since the number of ICs that make up the serial data communication method differs depending on the system, considering the use for a wide range of applications,
There is a problem that the number of terminals of the PU 21 must be considerably provided, and pins are wasted. In addition, there is a problem that it cannot be connected to an IC having more pins than the number of pins provided in the CPU.
On the other hand, in the serial data communication method shown in FIG.
Must be transmitted, which causes a problem that the transmission speed is reduced. Therefore, according to the present invention, the master device can be configured without depending on the number of slave devices, the number of connection cables between the master device and a plurality of slave devices can be reduced, and the transmission speed can be reduced. It is an object of the present invention to provide a serial data communication system which does not lower the communication speed. According to the present invention, there is provided a master device having a clock output terminal, a serial data output terminal, and a load signal output terminal, a clock input terminal, and a serial data input terminal, respectively. A plurality of independently provided slave devices having a terminal and a load signal input terminal; and a slave corresponding to and corresponding to the slave device.
A gate circuit connected to a load signal input terminal of the corresponding slave device, the gate circuit being provided in the vicinity of the device and having a corresponding slave device address set therein ;
A plurality of decoding means having an comparator and a shift register, and substantially three first to third cables, wherein the first cable is substantially one, and The clock output terminal and the plurality of clock input terminals of the plurality of slave devices are connected to the plurality of clock input terminals of the plurality of decoding means, and the second cable is substantially one, and the second cable is connected to the master device. The serial data output terminal is connected to a plurality of serial data input terminals of the plurality of slave devices, and the third cable is substantially one, and the load signal output terminal of the master device and each of the plurality of connect of the one input terminal of the gate circuit in the decoding means, wherein the master device, and outputs the clock to the serial from the clock output terminal DOO Indicate the end of serial data transmission of the data to be transmitted a code identifying the slave device should transmit data from the synchronous serial data output terminal to the clock output and transmitted serially, from then the load signal output terminal A load signal is transmitted, and the plurality of slave devices should simultaneously input a clock via the first cable and transmit the data via the second cable according to the input clock. A code for identifying the slave device and data to be transmitted are serially input and temporarily stored, and each of the plurality of decoding means inputs a clock via the first cable, and receives the input. Of the serial input data temporarily stored in the corresponding slave device according to a clock, the slave to be transmitted The code that identifies the location input to the shift register, the comparator
The set address and the code input to the shift register are compared with each other, and when they are matched, the other input terminal of the gate circuit is activated and A load signal is applied to the load signal input terminal of the corresponding slave device via a gate circuit, and the slave device to which the load signal is applied from the decoding means to the load signal input terminal is serially input from the serial data input terminal. Then, a serial data communication system is provided in which the temporarily held data is taken in properly. The serial data communication system of the present invention
Lock output terminal, serial data output terminal, and load
A master device having a signal output terminal;
Device, a plurality of decoding means, and substantially three first
To a third cable. For multiple slave devices
Each has a clock input terminal and a serial data input terminal.
And a load signal input terminal.
You. A plurality of decoding means correspond to the slave device.
And in the vicinity of the corresponding slave device.
Address of the corresponding slave device is the that is set.
Thus, multiple decoding means correspond to slave devices
And in the vicinity of the corresponding slave device
Do not wire the slave device selection signal over long distances.
By the way, each slave device is a slave to which data should be transmitted.
A code for identifying the device, transmission data, and a load signal
Receive the signal according to the distance from the master device.
Due to the delay time, the mutual data of these signals (data)
Immediate data reception is possible without occurrence of
And it is possible to select the correct slave device
Has the advantage of Each decoding means is provided with the corresponding switch.
Gate circuit connected to the load signal input terminal of the slave device
Having a path, a comparator, and a shift register.
It has a relatively simple circuit configuration. The first cable is
The clock output of the master device, substantially one;
Terminals and a plurality of clock inputs of the plurality of slave devices
And a plurality of clock input terminals of the plurality of decoding means.
And the second cable is substantially one,
The serial data output terminal of the master device and the
Multiple serial data input terminals of the slave devices
And the third cable is substantially a single cable.
The load signal output terminal of the star device and the plurality of
One input terminal of the gate circuit in each decoding means
Connected with child. The master device is connected to the clock.
Clock output from the clock output terminal
The serial data output terminal is synchronized with the clock output.
Code that identifies the slave device to which data should be transmitted from
And the data to be transmitted are transmitted serially,
Indicates the end of serial data transmission from the load signal output terminal.
Send a load signal. The plurality of slave devices are the same.
Occasionally input a clock via the first cable
And the second cable according to the input clock.
A slave device to which said data is to be transmitted via
Input the serial code and the data to be transmitted serially
Hold. Each of the plurality of decoding means is
Input a clock via a first cable, and
According to the input clock, the corresponding slave device
Of the temporarily stored serial input data,
Shifting the code identifying the slave device to be transmitted
Input to the register and set by the comparator.
Address and code input to the shift register
Is compared to see if they match
The other input terminal of the gate circuit is energized to activate the gate circuit.
Said load signal input of a corresponding slave device via a path
Apply a load signal to the terminal. Before the decoding means
The load signal applied to the load signal input terminal
Serial device from the serial data input terminal.
Force to temporarily capture the temporarily held data. FIG. 1 is a circuit diagram showing a first embodiment of a serial data communication system according to the present invention. This serial data communication system has an arithmetic and control unit (CPU) 1 of a microcomputer as a master device and first to third integrated circuits (ICs) 3 to 5 as a plurality of slave devices.
PU1 and the first to third ICs 3 to 5 are connected by two cables 2A and 2B. That is, CPU
1 clock output terminal CLK and a plurality of IC3 to IC5.
One cable 2A between the clock input terminal CLK
Connected to the serial data output terminal S of the CPU 1.
DO and serial data input terminals of multiple IC3 to IC5
The SDI is connected with one cable 2B.
Also in this serial data communication system, serial data is transmitted in one direction from the CPU 1 to the first IC 3 to the third IC 5. The serial data communication system shown in FIG. 1 further includes a decoding means including a shift register 7 and a decoder 8. The shift register 7 of the decoding means
Clock is input through the over b le 2A, the decoder 8
Is connected to the load signal output terminal LOAD of the CPU 1.
Load signal LOAD is input via cable 2C
I have. In this serial data communication system, for example, in order to automatically test and inspect a plurality of TV receivers, an adjustment signal is output as serial data from a CPU 1 as a master device, and each of the image receiving devices to be inspected and inspected. The present invention is applied to a test / inspection system including a first IC3 to a third IC5 as slave devices which are connected to a device and function as an interface thereof. A cable 2A transmits a clock CLK serially output from the clock output terminal CLK of the CPU 1 as illustrated in FIG. 2, and a cable 2B transmits the clock CLK from the serial data output terminal SDO of the CPU 1 to FIG. As illustrated
Transmitting serial data output serially. The third cable 2C is a load signal LOA output from the load signal output terminal LOAD of the CPU 1 to the decoder 8.
Transmit D. The clock CLK and the serial data are supplied to the clock input terminals C of the first IC3 to the third IC5.
LK and the serial data input terminal SDI. FIG. 2 is a timing chart of signals output from the CPU 1. Serial data output terminal S of CPU1
The serial data output from the DO is prefixed with an IC number ICNO indicating the identification code of the IC to which the data DATA is to be transmitted. The clock CLK output from the CPU 1 is composed of the IC number ICNO and the original data DA.
The number of pulses required for serial transmission of the TA is output. The load signal LOAD output from the CPU 1 is output as a pulse signal at the end of the transmission of the serial data DATA. The serial data consisting of the IC number ICNO and the data DATA shown in FIG.
At the same time. However, it is not formally taken into the IC3IC5, is temporarily stored, and is not output to the outside. The shift register 7 constituting the decoding means responds to the clock CLK and outputs the IC number I among the serial data input to the first IC 3.
CNO (signal S3) is input. The input of the IC number ICNO to the shift register 7 may be input from any IC. The IC number ICNO input to the shift register 7 is decoded by the decoder 8, and one IC corresponding to the IC number ICNO is specified. When the load signal LOAD is applied from the CPU 1 to the terminal G of the decoder 8, the decoder 8 outputs the I signal from the output terminal corresponding to the decoded IC.
C, for example, the load signal input terminal LO of the second IC 4
A decode output S82 is output to AD. The second IC 4 to which the load signal LOAD is input from the decoder 8 takes in the provisionally input serial data into the inside and outputs it externally. Note that the second IC 4 is an IC
It is not necessary to take in the number ICNO and output it outside.
Only one IC can formally fetch serial data internally and output it to the outside. In this case, other ICs do not perform the formal serial data fetching operation and the external output operation. As a result, the serial data is formally taken into only the second IC 4 designated by the CPU 1. The TV receiver connected to the second IC 4 is inspected based on the fetched serial data. As is apparent from the configuration of the serial data communication system of FIG. 1, the problems of the number of terminals for outputting the load signal of the CPU 21 and the number of cables for transmitting the load signal shown in FIG. 4 are solved. , Does not depend on the number of connected ICs. In addition, the serial data communication method of FIG. 1 simultaneously transmits serial data to a plurality of ICs, and therefore solves the problem of a decrease in transmission speed in the serial data communication method shown in FIG. Further, the serial data communication system shown in FIG. 1 only has a shift register 7 and a decoder 8 as decoding means, so that the circuit configuration is not complicated, and the complexity of the circuit operation and the communication operation in the CPU 1 increase. Nor. FIG. 3 shows the configuration of a second embodiment of the serial data communication system of the present invention. This serial data communication system is obtained by replacing the circuit configuration of the decoding means shown in FIG.
Magnitude comparator 15, shift register 16
And an AND gate 11. Second
The address matching circuit 18 as decoding means for the IC 4 and the address matching circuit 19 as decoding means for the third IC 5 have the same circuit configuration as the magnitude comparator 15 and the shift register 16, respectively. The CPU 1 and the first to third ICs 3 to 5 are connected via cables 2A and 2B as in the case of FIG. In the serial data communication system shown in FIG. 3, the serial data output from the CPU 1, the clock CLK, and the signal waveform (or format) and timing of the load signal LOAD are the same as those shown in FIG. Therefore, the serial data is the IC number IC
NO and data DATA. The data transmission to the first IC 3 will be described. Similarly to the input to the shift register 7 in FIG. 1, the IC number ICNO is input from the first IC 3 to the shift register 16. The IC number ICNO input to the shift register 16 is the magnitude comparator 15
Is output to The address of the first IC 3 is set in the magnitude comparator 15 in advance, and when the address matches the IC number ICNO from the shift register 16, the
It outputs a “high” level coincidence signal S15 to the D gate 11. At the end of the serial data transmission, the load signal LOAD is sent from the CPU 1 as a pulse signal to the AND gate 1.
1, the load signal L from the AND gate 11 is output.
The “high” level pulse signal corresponding to the OAD is the first I
Input to the load signal output terminal LOAD of C3,
IC3 officially takes in the serial data already input and outputs it externally. The same applies to the operation of other ICs. The serial data communication system shown in FIG. 3 operates in the same manner as the serial data communication system shown in FIG. 1 except that the decoding means is different. Can be. In the serial data communication system shown in FIG.
AND gate 1 in each IC, eg, first IC3
1, the circuit of the magnitude comparator 15 and the shift register 16 may be incorporated to form one IC. This makes the circuit configuration and wiring simpler. As described above, according to the serial data communication system of the present invention, a master device can be configured without depending on the number of slave devices, and a master device and a plurality of slave devices can be configured. The number of cables connecting the devices does not depend on the number of slave devices. Further, according to the serial data communication method of the present invention, serial data is simultaneously transmitted to a plurality of slave devices, so that there is no data transmission delay that occurs when serial transmission is sequentially performed for a plurality of slave devices. .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of a serial data communication system according to a first embodiment of the present invention. FIG. 2 is a diagram showing a transmission signal format and transmission timing in FIG. FIG. 3 is a configuration diagram of a serial data communication system according to a second embodiment of the present invention. FIG. 4 is a diagram showing a configuration of a conventional serial data communication system. FIG. 5 is a diagram showing a transmission signal format and timing in FIG. 4; FIG. 6 is a diagram showing a configuration of another conventional serial data communication system. FIG. 7 is a diagram showing a transmission signal format and timing in FIG. 6; [Description of Signs] 1 CPU 2A-2C Cable 3-5 IC 7 Shift register 8 Decoder 11-13 AND gate 15 Magnitude comparator 16 Shift register 18, 19 Address matching circuit

   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-59-71526 (JP, A)                 JP-A-61-103263 (JP, A)                 JP-A-64-64056 (JP, A)

Claims (1)

(57) [Claim 1] A master device having a clock output terminal, a serial data output terminal, and a load signal output terminal, a clock input terminal, a serial data input terminal, and a load device, respectively. A plurality of independently provided slave devices having signal input terminals, and slave devices corresponding to and corresponding to the slave devices
Provided near the are set the address of the corresponding slave device, and a gate circuit connected to the load signal input terminal of the slave device in which the corresponding, comparator
And a plurality of decoding means having a shift register and a shift register; and substantially three first to third cables, wherein the first cable is substantially one, and The clock output terminal is connected to a plurality of clock input terminals of the plurality of slave devices, and a plurality of clock input terminals of the plurality of decoding means. The second cable is substantially one, and the second cable is connected to the master device. The serial data output terminal is connected to the plurality of serial data input terminals of the plurality of slave devices. The third cable is substantially one, and the load signal output terminal of the master device and the plurality of the plurality of serial cables are respectively connected. connect the to one input terminal of the gate circuit de <br/> coding unit, the master unit, and outputs the clock to the serial from the clock output terminal DOO A code for identifying a slave device to which data is to be transmitted and data to be transmitted are serially transmitted from the serial data output terminal in synchronization with the clock output, and then serial data is transmitted from the load signal output terminal. Sending a load signal indicating the end of transmission, wherein the plurality of slave devices simultaneously input a clock via the first cable, and input the clock via the second cable in accordance with the input clock. A code for identifying a slave device to which data is to be transmitted and a data to be transmitted are serially input and temporarily stored, and each of the plurality of decoding means inputs a clock via the first cable, In addition, of the serial input data temporarily held in the corresponding slave device in accordance with the input clock, A code for identifying the slave device is input to the shift register, and an address set in the comparator is compared with a code input to the shift register to determine whether or not the code matches. A load signal is applied to the load signal input terminal of the corresponding slave device via the gate circuit by energizing the other input terminal of the circuit, and the load signal is applied to the load signal input terminal from the decoding means. A serial data communication method in which a slave device normally takes in data that is serially input from the serial data input terminal and temporarily held.