JP2001051912A - Serial data transfer system and abnormality detecting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent burden to a CPU or processing program and to enable even a processing circuit, in which the CPU does not exist, to detect abnormality in serial data transfer. SOLUTION: This system is provided with first and second processing circuits 100 and 200 respectively having receiving means 120 and 220 and transmitting means 110 and 220 as serial data transfer means. In this case, when performing data transfer between the transmitting means 110 of the first processing circuit 100 and the receiving means 220 of the second processing circuit 200 and between the transmitting means 210 of the second processing circuit 200 and the receiving means, 120 of the first processing circuit 100, test data transmitted from one processing circuit to be a test mode transmission side are turned with the other processing circuit to be a test mode receiving side, circulated through all signal lines and returned to one processing circuit to be the test mode transmitting side later. Thus, concerning the presence/absence of abnormality on the signal line, abnormality can be automatically detected while maintaining the direction of input/output on the signal line at the time of ordinary operation without increasing the number of signal lines or number of parts and without increasing the load of the CPU or processing program.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transfer system and a method for detecting an abnormality thereof, and more particularly, to a serial data transfer system for automatically detecting a failure in serial data transfer between a plurality of semiconductor integrated circuits and a method for detecting the abnormality. .

[0002]

2. Description of the Related Art In various devices, a plurality of processing circuits,
When there are a plurality of circuit boards, a plurality of semiconductor integrated circuits, and the like, and data is transferred between them, there is an advantage that the number of wirings can be reduced by using a serial data transfer unit.

Here, when processing circuits such as an ASIC are mounted on separate substrates, and serial data transfer is used for connection between the substrates, there is a case where the ASIC operates in synchronization with a clock for each substrate. is there. In such a case, the transmitting side outputs data with its own clock,
The receiving side also receives data with its own clock. A start bit is first sent to the data, and the timing is adjusted. In addition, if the transfer is continued for a long time, there is a possibility that a difference in clock between the transmitting side and the receiving side may be accumulated. Then, the next data is also provided with a start bit first.

Conventionally, the most frequently used method for detecting an abnormality related to data transfer is that the transmitting side sends test data to the receiving side, and the receiving side temporarily stores the test data in a register or performs signal processing. ,
In some cases, the stored data or the signal-processed data is sent back to the transmitting side. The transmitting side verifies the returned data and detects whether there is an error in transmission and reception.

However, when a transmission / reception error occurs during serial data transfer, it is difficult to determine whether the problem is a protocol (including data rate) problem or a physical abnormality in wiring (connection). Yes, they often spend a lot of time.

That is, if it is only known that a problem has occurred in transmission / reception, the problem is: whether the problem is soft or hard, whether the problem is a slight deviation of a signal for latching a clock, etc., serial data. This is a problem with the protocol, and struggling to narrow down (isolate) the problem.

As a result of various studies,
In many cases, the result is caused by hardware such as a broken wire, an incorrect component number, and a signal not correctly transferred to the partner ASIC.

[0008]

As for the inspection of serial data transfer as described above, Japanese Unexamined Patent Publication No. 60-45858 discloses that in two processing circuits, data transmitted from one of them is received by a circuit on the receiving side. In this case, control is performed so as to return to the middle of the data without causing the error to be detected on the transmission side.

According to this technique, although an abnormality can be detected on the transmission side, return control is performed on the reception side of each line used for serial data transfer, and test data is transmitted to each line on the transmission side. In addition, it is necessary to receive and inspect the test data. In other words, since each of the signal lines for the communication request signal, the signal line for the communication permission signal, and the signal line for the data is performed by both processing circuits, the load on the CPU and the processing program increases.

[0010] For this reason, a processing circuit (semiconductor integrated circuit) without a CPU requires a separate CPU, and the processing circuit with a CPU also has a problem that the load is increased.

Accordingly, the present invention has been made in view of the above problems, and does not impose a burden on a CPU or a processing program, and can realize abnormality detection of serial data transfer even in a processing circuit having no CPU. It is an object of the present invention to realize a serial data transfer system and an abnormality detection method thereof.

[0012]

SUMMARY OF THE INVENTION The present invention for solving the above problems is described below. (1) The invention according to claim 1 comprises a first processing circuit and a second processing circuit each having a receiving means and a transmitting means as serial data transfer means, wherein the transmitting means of the first processing circuit and the Between the receiving means of the second processing circuit,
Also, in a serial data transfer system for performing data transfer between the transmitting means of the second processing circuit and the receiving means of the first processing circuit, one of the processing circuits on the test mode transmitting side receives the signal from the transmitting means. First switching means for transmitting test data from the signal line of the communication request signal and guiding the test data received on the signal line of the received data to the receiving means; and transmitting the test data from the signal line of the communication permission signal to the transmission data signal. A second switching unit that returns the test data from the signal line of the communication request signal to a signal line of the communication permission signal, and a detection unit that detects an abnormality based on the test data circulated through each signal line. The test data from the signal line of the communication request signal is returned to the signal line of the communication enable signal in the other processing circuit on the test mode receiving side, and the received data is A third switching means for returning test data from the signal line to a communication request signal signal line and returning test data from the communication permission signal signal line to a transmission data signal line; System.

According to the present invention, the test data transmitted from one processing circuit on the test mode transmitting side is looped back with the other processing circuit on the test mode receiving side, and is passed through all signal lines. After the circulation, the process returns to one of the processing circuits on the test mode transmitting side.

Thus, in data transfer of two signal processing circuits having serial data transfer means requiring two or more signal lines, it is determined whether or not there is an abnormality on the signal line without increasing the number of signal lines or the number of parts. Abnormality can be automatically detected without increasing the load on the CPU or the processing program and maintaining the input / output direction of the signal line during normal operation.

Therefore, no burden is placed on the CPU and the processing program, and abnormality detection of serial data transfer can be easily realized even in a processing circuit having no CPU. For example, when the processing circuit is an integrated circuit such as an ASIC,
By mounting a relatively simple test circuit on the integrated circuit itself, the cost of the product itself and the number of components are not increased.

The detecting means detects an abnormality by comparing the transmitted test data with the received test data. Further, the detection means performs abnormality detection at a time interval from the transmission of the test data to the reception of the test data.

The apparatus further comprises mode setting means for setting a test mode, and mode discriminating means for discriminating whether or not the test mode has been set. Means and the signal transmission state of the third switching means can be switched.

The mode setting means sets a test mode for a certain period of time after the system is turned on.
It is desirable. Further, it is preferable that the mode setting means switches between a test mode transmitting side and a test mode receiving side when no abnormality is detected by the detecting means.

[0019] Further, there is provided time measuring means, wherein the mode setting means switches between a test mode transmitting side and a test mode receiving side based on the measurement result of the time measuring means.
It is desirable.

(2) The invention according to claim 8 is provided with a first processing circuit and a second processing circuit each having a receiving means and a transmitting means as serial data transfer means, and transmitting the first processing circuit. Abnormality in the serial data transfer system for performing data transfer between the means and the receiving means of the second processing circuit and between the transmitting means of the second processing circuit and the receiving means of the first processing circuit. A method for setting one of the processing circuits as a test mode transmitting side and setting the other processing circuit as a test mode receiving side, and the test mode transmitting side transmits test data from the transmitting means to a communication request signal. The test mode receiving side returns test data from the communication request signal signal line to the communication permission signal signal line, and the test mode transmission side transmits communication. The test data from the test mode receiving side is folded back to the communication request signal signal line, and the test mode transmitting side is folded to the communication request signal signal line. The test data from the test mode is returned to the signal line of the communication permission signal, the test mode receiving side returns the test data from the signal line of the communication permission signal to the data signal line, and the test mode transmitting side receives the data on the data signal line. An abnormality detection method for a serial data transfer system, wherein data is guided to a receiving unit and abnormality is detected by comparing transmitted test data with received test data.

According to the present invention, the test data transmitted from one processing circuit on the test mode transmitting side is looped back to the other processing circuit on the test mode receiving side, and is passed through all signal lines. After the circulation, the process returns to one of the processing circuits on the test mode transmitting side.

Thus, in data transfer of two signal processing circuits having serial data transfer means requiring two or more signal lines, it is possible to determine whether there is an abnormality on the signal line without increasing the number of signal lines or the number of parts. Abnormality can be automatically detected without increasing the load on the CPU or the processing program and maintaining the input / output direction of the signal line during normal operation.

For this reason, no burden is imposed on the CPU and the processing program, and an abnormality in serial data transfer can be easily detected even in a processing circuit having no CPU.

[0024]

Embodiments of the present invention will be described below in detail. FIG. 1 is a block diagram showing a basic detailed configuration of a serial data transfer system according to an embodiment of the present invention. FIG. 2 is a block diagram showing a basic schematic configuration of the serial data transfer system.

Here, the serial data transfer circuit 100
1 shows an example of a serial data transfer system including a serial data transfer circuit 200 and a serial data transfer circuit 200. First, the overall schematic configuration will be described with reference to FIG.

In this embodiment, the serial data transfer circuit 100 and the serial data transfer circuit 200 have substantially the same circuit configuration.
0, the serial data transfer circuit 200 is an independent processing circuit, and is configured by a semiconductor integrated circuit such as an ASIC. The transmitting means 110 and 210 for transmitting data and the receiving means 12 for receiving data, respectively.
0, 220, and separate function circuits 190, 290 for realizing various functions other than transmission and reception.

Next, a detailed circuit configuration relating to transmission and reception will be described with reference to FIG. FIG. 1 shows a case where the serial data transfer circuit 100 and the serial data transfer circuit 200 have the same circuit configuration. In addition,
The serial data transfer circuit 100 and the serial data transfer circuit 200 are independent processing circuits.
It is composed of a semiconductor integrated circuit such as C.

First, the internal configuration of the serial data transfer circuit 100 will be described. Since the serial data transfer circuit 200 has the same configuration as the serial data transfer circuit 100, detailed description will be omitted.

In the description of this embodiment, the serial data transfer circuit 100 is one processing circuit on the test mode transmitting side, and the serial data transfer circuit 200 is the other processing circuit on the test mode receiving side. The description will be made by taking the case of the case as an example.

Normally, the transmitting means 110 transmits a communication request signal (RTS) from the SREQ terminal, and transmits a transmission data (TxD) to the SDATA terminal when a communication permission signal (CTS) corresponding thereto is received from the other side at the SACK terminal. It is transmitted from the terminal. A feature of this embodiment is that the test data transmitting unit 111 in the transmitting unit 110 is in the test mode.
More test data is transmitted.

Normally, when the communication request signal (RTS) is received at the MREQ terminal, the receiving means 120 transmits a communication permission signal (CTS) corresponding to the communication request signal (RTS) from the MACK terminal, and transmits the transmission data from the other party to the reception data (RxD ) Is received at the MDATA terminal. Note that as a feature of the present embodiment, in the test mode, the test data received by the test data comparison unit 121 in the receiving unit 120 is compared.

A receiving unit 131 receives a mode signal for setting the test mode and informing the processing circuit whether the test mode is on the transmitting side or on the receiving side of the test mode.
And a receiving circuit 120. In addition,
In this embodiment, when the test A = L, the normal mode is set, and when the test A = H, the test mode is set. When the test A = H and the test B = H, the test mode is transmitted. When the test A = H and the test B = L, the test mode is set. Become a test mode receiver.

Reference numeral 141 denotes a selector as first switching means. On the test mode transmitting side in the test mode, test data from the transmitting means 110 is transmitted from a signal line connected to a SREQ terminal for transmitting a communication request signal (RTS). The test data transmitted through the reception data (RxD) signal line is guided to the reception unit 120.

Reference numeral 142 denotes a selector as first switching means. In the test mode, test data from the transmission means 110 passing through the selector 141 is transmitted to a communication request signal (RT
S) The signal is transmitted from the signal line connected to the SREQ terminal for transmission, and the communication request signal (RT
S) is transmitted from the signal line connected to the SREQ terminal.

Reference numeral 143 denotes a selector as second switching means. In the test mode, a logic circuit for receiving and distributing a signal received from a signal processing circuit connected to the SACK terminal for receiving a communication enable signal (CTS) from the other processing circuit. The test data that has passed through 162 and the transmission data (TxD) from the transmission unit 110 are transmitted from the signal line connected to the SDATA terminal for the transmission data (TxD) at normal times. In this case, the logic circuit 16
2 and the selector 143 constitute a folding means.

Reference numeral 144 denotes a selector as second switching means. In the test mode, a logic circuit for receiving and allocating a communication request signal (RTS) from the other processing circuit via a signal line connected to the MREQ terminal for receiving the signal is used. The test data that has passed through 164 is normally transmitted with a communication permission signal (CTS) from the receiving means 120 from a signal line connected to the MACK terminal for the communication permission signal (CTS). In this case, the logic circuit 1
The selector 64 and the selector 144 constitute a folding means.

Reference numerals 161 and 162 denote logic circuits for distributing test data in a test mode and a communication permission signal in a normal state. 163 and 164 are logic circuits for distributing test data in a test mode and a communication request signal in a normal state. Reference numerals 151 to 156 denote buffer amplifiers that amplify data passing through each terminal.

Each selector of the serial data transfer circuit 200 set on the test mode receiving side constitutes a third switching means. Each of the above selectors outputs an input on the H side when the applied test A or test B is H, and outputs the input on the opposite side to H when the applied test A or test B is L. Is configured to be output.

The operation of the serial data transfer system of FIG. 1 for error detection will be described below. Here, test A = H and test B = H are applied to the serial data transfer circuit 100 to set the test mode transmitting side, and the serial data transfer circuit 200 sets the test A = H,
It is assumed that the test mode is set to the test mode receiving side by applying the test B = L.

In this case, since H is applied to both inputs to the AND logic circuit 131, its output becomes H.
Since the output H of the logic circuit 131 is applied to the test data transmission unit 111, the test data transmission unit 11
1 outputs test data. The logic circuit 13
Since the output H of 1 is applied to the test data comparing unit 121, the test data comparing unit 121 is preparing to perform the comparison when receiving the test data.

The test data from the test data transmitting section 111 is output from the data terminal of the transmitting means 110 in the same manner as normal transmission data. This test data passes through the selector 141 and the selector 142 (FIG. 3A), and goes to the serial data transfer circuit 200 via a signal line connected to the SREQ terminal for transmitting a communication request signal (FIG. 3A). .

The test data received on the signal line connected to the MREQ terminal for receiving the communication request signal from the serial data transfer circuit 100 passes through the active distribution logic circuit 264, and is transmitted to the selector 244. The signal is looped back (FIG. 3C) and transmitted again to the serial data transfer circuit 100 from the signal line connected to the communication permission signal MACK terminal (FIG. 3D).

The test data received from the serial data transfer circuit 200 through the signal line connected to the SACK terminal for receiving the communication permission signal passes through the active distribution logic circuit 162, and is supplied to the selector 143. It is folded back (FIG. 3E) and transmitted again from the signal line connected to the transmission data SDATA terminal to the serial data transfer circuit 200 (FIG. 3F).

The test data received from the serial data transfer circuit 100 via the signal line connected to the transmission data MDATA terminal is turned back by the selector 241 and the selector 242 (FIG. 3G), and the communication request signal is transmitted. From the signal line connected to the SREQ terminal of the serial data transfer circuit 10 again.
0 is transmitted (FIG. 3C).

The test data received by the signal line connected to the MREQ terminal for receiving the communication request signal from the serial data transfer circuit 200 passes through the active distribution logic circuit 164, and is output by the selector 144. It is looped back (FIG. 3) and transmitted again to the serial data transfer circuit 200 from the signal line connected to the communication permission signal MACK terminal (FIG. 3).

The test data received from the serial data transfer circuit 100 through the signal line connected to the SACK terminal for receiving the communication permission signal passes through the active distribution logic circuit 262, and is supplied to the selector 243. The signal is looped back (FIG. 3C) and transmitted again from the signal line connected to the SDATA terminal for transmission data to the serial data transfer circuit 100 (FIG. 3C).

The test data received from the serial data transfer circuit 200 via the signal line connected to the transmission data MDATA terminal does not pass through the selector 241 and is received at the data terminal of the receiving means 120 (FIG. 3). S).

That is, the serial data transfer circuit 100
The test data transmitted from the controller circulates through all signal lines used for serial transfer and returns to the serial data transfer circuit 100 again.

At this point, the test data comparing unit 121 compares the test data transmitted from the transmitting unit 110 with
The contents are compared with the test data circulating and reaching the receiving means 120.

As a result of the comparison, if the transmitted test data matches the received test data, it is determined that the signal line is normal (no abnormality). In this case, the test mode may be ended and shifted to the normal mode.

If the comparison results do not match, it is determined that any of the signal lines is abnormal. In the case where there is an abnormality, it is desirable to transmit the result to a CPU or a display unit of the system.

Further, a time measuring means (not shown) is provided in the serial data transfer circuit 100, and abnormality is detected based on a value of a time interval from transmission of test data to reception of the test data. It is also possible. As a result, an unconnected state can be detected. It is desirable that the abnormality when the comparison result does not match and the abnormality in which the test data does not return be distinguished and transmitted to the CPU or the display means.

Thus, in data transfer of two signal processing circuits having serial data transfer means requiring two or more signal lines, it is determined whether or not there is an abnormality on the signal line without increasing the number of signal lines or the number of parts. Abnormality can be automatically detected without increasing the load on the CPU or the processing program and maintaining the input / output direction of the signal line during normal operation.

For this reason, it is possible to easily detect an abnormality in serial data transfer without imposing a burden on the CPU or the processing program, and even in a processing circuit having no CPU. For example, when the processing circuit is an integrated circuit such as an ASIC,
By mounting a relatively simple test circuit on the integrated circuit itself, the cost of the product itself and the number of components are not increased.

As test data, 1-byte data having a start bit and a stop bit as shown in FIG. 4 or block transfer (1 byte data is successively transferred to several bytes in order, in this case, Is the first one
(Information indicating test data in byte)
The test data received by the test data comparing unit 1
It is desirable that the judgment that there is no abnormality be given by accidental matching at 21.

It is also possible to switch between test A and test B so that the test mode transmitting side and the test mode receiving side are reversed. When the number of wires between the serial data transfer circuits is odd, the serial data transfer circuit 100 may be on the transmission side and perform one round trip check, and then the serial data transfer circuit 200 may be on the transmission side and perform one round trip check. As a result, although there are wirings to be double-checked, a test can be performed on an odd number of signal lines.

It is also desirable to replace the test mode transmitting side with the test mode receiving side when no abnormality is detected in any one of the tests. Further, it is preferable that the apparatus further comprises a time measuring means, and wherein the mode setting means interchanges the test mode transmitting side and the test mode receiving side based on the measurement result of the time measuring means. In these cases, when the transmission side is the test mode transmission side, it is desirable to give a certain margin to the time measurement.

In the above operation, it is desirable to set the test mode for a certain period of time after the system is turned on. This makes it possible to automatically test the signal lines each time the power is turned on. After a lapse of a certain time, the mode is shifted to the normal mode.

When the power-on timing is different between the serial data transfer circuit 100 and the serial data transfer circuit 200, the test mode transmission side should start the test data transmission after a lapse of a certain time in consideration of a margin. Is desirable.

In each of the above cases, when the time measuring means is not provided, it can be dealt with by providing a switching instruction means externally. In each of the above cases, if the transmission lines from the test data transmission unit 111 reach the test data comparison unit 121 due to the intersection of the signal lines, an abnormality cannot be detected. In order to detect such an abnormality, it is sufficient to provide a selector capable of sequentially checking the test data one by one.
In this case, if there is no abnormality in one round trip, the next one round trip,
Or two reciprocations, the first one reciprocation and the next one reciprocation,
What should I do?

According to the present embodiment as described above, in a case where a plurality of processing circuits, a plurality of circuit boards, a plurality of semiconductor integrated circuits, and the like exist in various devices and data transfer is performed between them. In addition, various verifications on wiring become possible.

In this case, even if the test data from the transmitting side has passed through, the test data is not sent to the test data comparing section on the transmitting side. When receiving, the data is read after detecting the start bit, and if there is no start bit, there is a wiring error such as a broken wire.

In this case, the test data from the test mode transmitting side returns to the test data comparing unit 121 in the circuit of FIG. Therefore, as described above, by providing the selector for checking one reciprocation at a time, it is possible to detect the abnormality of the intersection.

For example, if the capacitor constant is incorrect and the signal waveform is dull enough to be unreadable (signal degradation), the test mode transmitting side cannot read the test data output by itself, and An error occurs in the data comparison unit 121. Conversely, if the test data comparison unit 121 confirms a match, it can be determined that the component constants on the wiring are within a range in which there is no problem with transmission and reception.

[0065]

As described in detail above, the following effects can be obtained. In the present invention, the test data transmitted from one processing circuit serving as the test mode transmitting side is turned back between the other processing circuit serving as the test mode receiving side and circulated through all the signal lines. To return to one of the processing circuits on the test mode transmitting side.

Thus, in the data transfer of two signal processing circuits having serial data transfer means requiring two or more signal lines, it is determined whether or not there is an abnormality on the signal line without increasing the number of signal lines or the number of parts. Abnormality can be automatically detected without increasing the load on the CPU or the processing program and maintaining the input / output direction of the signal line during normal operation.

For this reason, no burden is imposed on the CPU or the processing program, and an abnormality in serial data transfer can be easily detected even in a processing circuit having no CPU. For example, when the processing circuit is an integrated circuit such as an ASIC,
By mounting a relatively simple test circuit on the integrated circuit itself, the cost of the product itself and the number of components are not increased.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a configuration and a connection state of a serial data transfer system according to an embodiment of the present invention.

FIG. 2 is a functional block diagram illustrating a configuration and a connection state of a serial data transfer system according to an embodiment of the present invention.

FIG. 3 is a functional block diagram showing an operation state of the serial data transfer system according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram schematically showing a state of test data used in the embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 serial data transfer circuit 110 transmitting means 111 test data transmitting section 120 receiving means 121 test data comparing section 200 serial data transferring circuit 210 transmitting means 211 test data transmitting section 220 receiving means 221 test data comparing section

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B083 AA04 BB06 CC06 DD09 DD10 DD11 DD14 EE11 EE16 GG08 GG09 5K035 AA02 AA04 EE02 GG02 GG06

Claims (8)

[Claims] A first processing circuit and a second processing circuit each having a receiving means and a transmitting means as serial data transfer means, wherein a transmitting means of the first processing circuit and a second processing circuit of the second processing circuit are provided. In a serial data transfer system for performing data transfer between a receiving unit and a transmitting unit of the second processing circuit and a receiving unit of the first processing circuit, one of the processing circuits serving as a test mode transmitting side First switching means for transmitting test data from a transmission means through a signal line of a communication request signal, and leading test data received through a signal line of reception data to the reception means; and a test from a signal line of a communication permission signal. Second switching means for returning the data to the transmission data signal line and returning the test data from the communication request signal signal line to the communication permission signal signal line, and circulating through each signal line Detecting means for detecting an abnormality based on the received test data, and returning the test data from the signal line of the communication request signal to the signal line of the communication permission signal in the other processing circuit on the test mode receiving side, and receiving the test data. A serial switching means for returning test data from a data signal line to a communication request signal signal line and returning test data from a communication permission signal signal line to a transmission data signal line; Data transfer system. 2. The serial data transfer system according to claim 1, wherein said detecting means detects an abnormality by comparing the transmitted test data with the received test data. 3. The apparatus according to claim 1, wherein the detecting unit detects an abnormality based on a time interval from when the test data is transmitted to when the test data is received. Serial data transfer system. 4. A mode setting means for setting a test mode; and a mode discriminating means for discriminating whether the test mode is set. The first switching means and the second switching means according to a discrimination result of the mode discriminating means. 4. The serial data transfer system according to claim 1, wherein a signal transmission state of said means and said third switching means is switched. 5. The serial data transfer system according to claim 4, wherein said mode setting means sets a test mode for a fixed time from when the power of the system is turned on. 6. The mode setting unit according to claim 1, wherein, when no abnormality is detected by the detection unit, the mode setting unit switches a test mode transmission side and a test mode reception side. A serial data transfer system as described in 7. The apparatus according to claim 1, further comprising a time measuring unit, wherein the mode setting unit switches between a test mode transmitting side and a test mode receiving side based on a measurement result of the time measuring unit. Item 6. The serial data transfer system according to any one of Items 5. 8. A first processing circuit and a second processing circuit each having a receiving means and a transmitting means as serial data transfer means, wherein a transmitting means of the first processing circuit and a second processing circuit of the second processing circuit are provided. An abnormality detection method for detecting an abnormality in a serial data transfer system that performs data transfer between a receiving unit and a transmitting unit of the second processing circuit and a receiving unit of the first processing circuit. One of the processing circuits is set as a test mode transmission side, and the other processing circuit is set as a test mode reception side. The test mode transmission side transmits test data from the transmission means through a signal line of a communication request signal. On the receiving side, the test data from the signal line of the communication request signal is looped back to the signal line of the communication permission signal, and on the transmission side in the test mode, the test is performed from the signal line of the communication permission signal. Data is returned to the data signal line, the test mode receiving side returns the test data from the data signal line to the communication request signal signal line, and the test mode transmitting side transmits the test data from the communication request signal signal line. The test mode receiving side loops back the test data from the communication enable signal signal line to the data signal line, and the test mode transmitting side loops the test data received on the data signal line to the receiving means. An abnormality detection method for a serial data transfer system, wherein the abnormality is detected by comparing the transmitted test data with the received test data.