KR930006894B1 - Signal terminal group matching circuit - Google Patents

Abstract

The signal terminal group interfacing circuit interfaces a terminal group with a signal terminal network and a signal message processor unit according to the capacity of signal terminal and signal message processor unit. The circuit includes an interfacing unit (40) for interfacing the signal terminal network node and the signal message processor unit, a signal terminal group loop-back unit (50) for loopint transmission-reception data line and an assertion signal detector (60) for sending long time out signal, enable request send signal, and RTS block signal according to clear to send period signal input.

Description

Signal terminal group matching circuit of electronic exchange

1 is a signal terminal group configuration in a common line signal apparatus to which the present invention is applied.

2 is a processor configuration diagram of a signal terminal group maintenance apparatus to which the present invention is applied.

3 is a block diagram of a logic unit of a signal terminal group maintenance apparatus to which the present invention is applied.

4 is a block diagram showing a configuration of the present invention.

* Explanation of symbols for main parts of the drawings

1: Data bus transfer group 2: Signal terminal control device

3: Signal terminal group maintenance device 4: Maintenance signal group

5 signal terminal network node 6 level 1 matching device

A: processor section B: logic section

20: central processing unit circuit

21: logic part and level 1 matching device matching circuit

22: signal terminal bus transceiver circuit 23: self-duplex control circuit

30: input / output port circuit 31: interrupt control circuit

32: redundant control circuit 33: data transmission bus monitoring circuit

34: data receiving bus monitoring circuit 35: clock generating circuit

36: maintenance command transmission and signal terminal status reading circuit

37: triple signal monitoring circuit 38: signal terminal bus matching circuit

39: signal terminal group matching circuit

40: signal terminal network node / signal message processing unit matching circuit

41: signal terminal network node / signal message processing unit matching buffer

42: matching control circuit for signal terminal network node / signal message processing unit

50: signal terminal group bus loopback circuit 51: lamp driving circuit

60: long time signal message processing unit transmission occupancy detection circuit

61: multivibrator 62: counter

63: instruction block transmission latch command latch

64: long time signal message processing unit transmission occupied interrupt generation latch

The present invention relates to a signal terminal group matching circuit of an electronic exchange, and more particularly to a signal terminal group matching circuit of an electronic exchange in a signal terminal maintenance device implemented in a common line signaling device of an electronic exchange.

In the signal terminal group, a plurality of signal terminal control apparatuses and a signal terminal group maintenance apparatus exist and are interconnected.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal terminal group matching circuit of an electronic switch that can match a signal terminal network node or a signal message processing unit, which is an upper block, so that message transmission and reception can be performed smoothly.

In order to achieve the above object, the present invention provides a signal terminal group matching circuit of an electronic switch, comprising: a signal terminal network node / signal processing unit matching means and a signal terminal network node / signal message processing unit matching means for looping transmission and reception data lines. And a long term signal message processor transmission occupancy detecting means connected to the signal terminal group bus loopback means, which is connected to the signal terminal network node / signal message processor matching means, sends an LTO signal, an ENRTS signal, and an RTSB signal and inputs an STSP signal. do.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

1 is a structural diagram of a signal terminal group in a common line signaling apparatus to which the present invention is applied. The signal terminal group includes a signal terminal control apparatus 2, a signal terminal bus and a signal terminal group maintenance apparatus 3, and the signal terminal group. The bus is divided into a data transfer bus group 1 and a maintenance signal group 4, and the signal terminal group maintenance apparatus 3 is composed of a redundant processor unit A and a redundant logic unit B.

The data transfer bus group 1 is a serial bus that can accommodate up to 32 signal terminals, and includes five signals such as a data transmission bus, a data reception bus, a data transmission / reception clock, a synchronization signal, and a data transmission bus occupied signal. Each signal is tripled and operated in Triple Modular-Redundancy (TMR).

The data transmitting bus and the data receiving bus are serial communication buses, each of which is a signal terminal for transmitting and receiving data. The data receiving bus is a signal terminal network node 5 serving as a transmitter of data, and each signal terminal control apparatus ( 2) becomes a receiver of data. Accordingly, the signal terminal control apparatus 2 may receive a message whose destination address is the same as its own address among the messages on the data receiving bus. However, in the case of the transmission bus, the receiver of the data is the signal terminal network node (5) and the transmitter is the signal terminal control apparatus (2), so that there are a plurality of data transmitters. Therefore, only one signal terminal at a time is used to prevent data collisions. Should be sent.

For such data transmission bus arbitration, an 8-bit arbitration counter is placed in each signal terminal control device and the signal terminal group maintenance device, and a synchronization signal and a data transmission bus occupancy signal are provided. Is preset to different binary values by the synchronization signal and then increased by the clock for data transmission and reception. At this time, when the arbitration counter reaches the maximum value that can be increased, the signal terminal control device 2 transmits a data transmission bus occupied signal and sends a message when there is a message to be transmitted. It is transmitted to the signal terminal control unit 2 and the signal terminal group maintenance unit 3 so that all arbitration counters are stopped at the same time. On the other hand, the signal terminal control device (2) that asserted the data transmission bus occupied signal negates the data transmission bus occupied signal when the transmission of its message ends, causing all arbitration counters to continue to increase. Since the counter is preset to different values by the synchronization signal, no message is sent from two or more signal terminals at the same time. Also, the arbitration counter in the signal terminal group maintenance device 3 is preset to a value smaller than the initial value of all other arbitration counters when preset by the synchronization signal, and sends a synchronization signal when this value reaches the maximum value. The possession of the data transmission bus is distributed equally to all signal terminals in the signal terminal group.

In this way, the signal terminal control apparatus 2 can receive the received message transmitted from the signal terminal network node 5 at any time. In the case of the transmission message, the transmission turn is returned in a round robin manner. Full duplex communication with the signaling terminal network node 5 is enabled, and each signal terminal must wait for data transmission by determining a maximum occupancy time that can occupy the data transmission bus at once. Allows the maximum time to operate as a constant data transmit / receive bus.

The maintenance signal group 4 includes a signal terminal group division signal, a signal terminal division signal, a clock speed division signal, a signal terminal group maintenance device command transmission and signal terminal status read signal, a signal terminal group alarm signal, and a data transmission confirmation signal. It consists of a data acknowledgment signal and a data acknowledgment request signal. The signal terminal group division signal is a signal indicating physical division between groups when two or more signal terminal groups are accommodated in a common line signaling device. The signal terminal group division signals are transmitted to all signal terminals in the same signal terminal group in the form of a bus, and each signal terminal is needed. You can find out by accessing the corresponding I / O port. The signal terminal division signal indicates a physical address of a signal terminal in the same signal terminal group, and the signal terminal can access the corresponding input / output port. The clock speed classification signal is a red-and-white signal for informing each signal terminal of the rate of transmit / receive data designed to be changeable. Each signal terminal is used as reference data for error detection associated with its own data transmission, and the data transmission confirmation signal is a signal. As a signal indicating that the terminal is in possession of the data transmission bus from the terminal to the maintenance circuit, the maintenance circuit compares and analyzes these signals to detect an error related to the occupation of the data transmission bus.

The data acknowledgment signal and the data acknowledgment request signal are signals for detecting an error in the operation of the data receiving bus. The maintenance circuit checks the receiving address of the message on the data receiving bus and sends a data acknowledgment request signal to the corresponding signal terminal. When the terminal is receiving data, the terminal transmits a data acknowledgment signal to detect a case where the received data is lost. Signal terminal group maintenance device It is a bus signal designed to transmit various commands such as system reset without passing through the data transfer bus as well as to identify the cause of failure for each signal terminal. Signal terminal group alarm signal is a bus signal that each signal terminal detects its own fault condition and informs the maintenance circuit. In the maintenance circuit, the signal terminal reads the status of each signal terminal when the signal terminal group alarm signal is detected. The location of the failure in the group can be known and appropriate action can be taken accordingly.

The signal terminal group maintenance apparatus 3 is largely divided into the logic unit B of the processor unit A. Each of the signal terminal group maintenance apparatus 3 is doubled as (a) and (b) and operated in an active and standby manner (active / standby). The redundancy control is performed between the processor unit (a) and (b), and the self redundancy control is performed between the logic unit (a) and (b). The operation and standby state can be determined. The logic unit B receives all input signals regardless of the operation state or the standby state, and all output signals are driven only in the logic unit in the operating state and maintain tri-atate in the logic unit in the standby state. In the processor unit A, the control signal outputted to the logic unit B is driven only by the processor unit in an operating state, thereby enabling cross connection control between the processor unit A and the logic unit B. do.

2 is a processor unit (A) of a signal terminal group maintenance apparatus to which the present invention is applied, collects and analyzes various fault information in the signal terminal group collected by the logic unit (B), and analyzes the result through a data transfer bus. It is controlled by the logic section of each signal terminal according to the maintenance related command received from the system maintenance center or level 3 function or according to the maintenance related command received from the system maintenance center or level 3 function. The processor unit has a function of controlling the level 1 matching device in the same manner as the logic unit. The redundant processor unit may occupy the data transfer bus regardless of an operation or standby state if there is no obstacle in the function of transmitting or receiving a message through the data transfer bus, and thus may perform different tasks according to the operation or standby state of the processor unit.

In order to perform the above functions, the processor unit is composed of a central processing unit circuit 20, a self-redundancy circuit 23, a logic unit and a level 1 matching device matching circuit 21, and a signal terminal bus transmitting and receiving circuit 22. The central processing unit circuit 20 is composed of a general-purpose CPU, a memory, a program, and a peripheral circuit thereof, and analyzes fault information immersed in a logic unit and transmits the information to a higher function or a signal terminal according to a command received from a higher function. It centrally controls each signal terminal, logic section and level-1 matching device in the group. The signal terminal bus transmission / reception circuit 22 provides a means for transmitting and receiving a level 3 function and a message to the signal terminal bus so that the processor can communicate with a higher function. The redundant processor unit occupies the signal terminal bus regardless of operation and standby state. It can communicate with the higher level functions, but can control the logic unit and level 1 matching device only in the processor unit which is in the operating state. The logic unit and the level 1 matching device 21 have a function of extending the address bus and the data bus, which are the system buses of the processor unit, to the logic unit and the level 1 matching device, and receive interrupts from the logic unit and the level 1 matching device. The function sends a reset signal to the logic unit and the level 1 matching circuit, and collects the redundant state and controls the redundant state of the logic unit and the level 1 matching device. When the processor unit is initialized, the self-redundancy control circuit 23 always keeps only one side of the operating state. If one side is removed, the mounted board becomes the operating state and the receiving side receives a "fault" signal from the other side. It will be in operation and the bobbin will be in standby.

Also, put the switch for operation and standby state on each board so that the switch is turned on. If both boards send a "failure" mode, one of them will continue to operate.

3 is a logic unit (B) of a signal terminal group maintenance apparatus to which the present invention is applied, and performs a processor unit matching function, a node matching function, and a maintenance related function together with a self-duplexing function. Maintenance-related functions generate first synchronization signal and data transmission / reception clock and supply them to the entire group of signal terminals, and at the same time, monitor the normality of these signals. Second, determine whether the signal terminal in accordance with the transmission order is sending a message. When two or more signaling terminals send messages at the same time, they distinguish between these signaling terminals and detect that one signaling terminal occupies the data transmission bus for more than the specified time. Third, the destination address that indicated the message on the data receiving bus. Fourth, it determines whether a signal terminal is receiving a message, and, fourthly, maintains a group of signal terminals that can isolate the detected signal terminal from the signal bus, reset the system for a particular signal terminal, or require self-testing of the signal terminal. Device command transfer function and fault source of faulty signaling terminal It puts the ability to check. Fifth, among the three signal lines of each signal operated by the TMR method, a signal line whose logic state at the data determination moment is not the same as the other two signal lines is detected to identify a signal line in which an error occurs.

In order to perform the above functions, the logic unit has an input / output port circuit 30, an interrupt control circuit 31, a redundant control circuit 32, a data transmission bus monitoring circuit 33, a maintenance command transmission and a signal terminal status reading circuit. (36), a data receiving bus monitoring circuit 34, a clock generating circuit 35, a bus triple signal monitoring circuit 37, a signal terminal bus matching circuit 38, and a signal terminal group matching circuit 39. .

The input / output port circuit 30 analyzes the contents of the address bus and data bus inputted from the processor unit and operates a related maintenance circuit according to a command of the processor unit, or transfers necessary data from the related maintenance circuit to the processor unit. Perform.

The clock generation circuit 35 generates the data transmission / reception clock, which is a signal terminal bus clock, and a node clock of the same frequency having the same phase, and supplies them to the signal terminal bus and the signal terminal network node, respectively, and to synchronize the signal terminal bus. Generate and supply a signal. The data transmission / reception clock and node clock can be selected from 1 MHz, 2 MHz, 4 MHz or an external clock, and the selected clock speed is known to all signal terminals and processor units in the signal terminal group through a clock speed division signal. Only the logic unit which is an operating state among the redundant logic units can transmit a signal to the outside.

The redundancy control circuit 32 detects a failure in the logic board that is operated in an operation and standby manner and informs the counterpart board so that the counterpart board is in an operating state. The processor may determine the redundancy status, but this is used when necessary for maintenance. When the logic unit is initialized, the same operation as the processor's own redundancy control circuit 23 is performed. When a change occurs in the operation and the standby state of the logic unit, the board, which is operated in the standby state, sends a level 1 interrupt to the processor unit.

The logic unit operating by the interrupt control circuit 31 can send a level 1 interrupt to the processor. There are eight types of level 1 interrupts, seven of which are interrupts generated by the logic section and one type of interrupts generated by the level 1 matching device. Since there are seven level 1 interrupts generated in the logic section, it is necessary to know the cause when an interrupt occurs. This can be done by reading the status register in the logic section. You can also do this by reading the status register in the logic section. In addition, an interrupt enable register may be provided in the logic unit to enable or disable interrupts for each cause. The data transmission bus monitoring circuit 33 has three functions as follows.

First, a function to monitor whether a signal terminal in accordance with the transmission order is sending out a message. The logic unit has a function for extracting a counter indicating the unique number of the signal terminal or processor unit currently being transmitted and the address portion of the message on the data transmission bus. If the counter value does not match the value of the extracted address, the two values are stored and a level 1 interrupt is generated.

The processor may find a signal terminal in which a failure occurs by reading a stored value by using an input / output port circuit. The second function is to monitor the case where two or more signal terminals or processor units transmit data at the same time. If two or more signals become valid at the same time by examining the data transmission confirmation signals sent from each signal terminal and processor unit, the failed signal is detected. It stores information so that the terminal or processor unit can be found and sends a level 1 interrupt to the processor unit. Third, if the data transmission bus occupies a signal and maintains data transmission state over one transmission terminal or transmission time specified in the signal unit or processor unit, it stores information to distinguish the signal terminal or processor unit and sends level 1 interrupt to the processor unit. Function. The data receiving bus monitoring circuit 34 determines whether the signal terminal or the processor receives a message currently being transmitted on the data receiving bus. To do this, the logic unit extracts the address portion of the message when the message is being transmitted to the data receiver bus, and determines whether a data acknowledgment signal is generated from the signal terminal or the processor unit. Send an interrupt.

Among the signal terminal bus signals, data transmission / reception clock, synchronization signal, data transmission bus occupancy signal, data transmission bus and data receiving bus are transmitted by triplex TMR method. When receiving, the value of two signal lines with the same logic level of the signal among three signal lines is received. Will be accepted. Therefore, if a fault occurs in one signal line, it is ignored, and if a fault occurs in two signal lines, it is not treated as a fault. Therefore, if a fault occurs in one of the tripled signal lines, it is quickly detected and repaired. It is necessary to do

To this end, the logic unit monitors the tripled signal lines, and when a failure occurs in any one signal line, a bus triple signal monitoring circuit 37 is provided to store the generated portion in a buffer and to send an interrupt to the processor unit.

When it is determined that normal transmission and reception of a message through the signal terminal bus is impossible due to a failure in the signal terminal, the signal terminal group maintenance apparatus may attempt to control the hardware signal to each signal terminal. This function is performed by the maintenance command transmission and signal terminal status reading circuit 36. Commands that can be sent to the signal terminal include clear signal terminal alarm status, allow signal terminal bus occupancy, disable signal terminal bus occupancy, and require signal terminal test. And a signal terminal reset request.

The signal terminal group matching circuit 39 supplies a node clock to a signal terminal network node and converts the signals of the triplexed data transmission bus and data receiving bus into differential signals without modification or buffering and sends them to the signal terminal network node. It performs a function of receiving an alarm signal from a reverse function and a signal terminal network node.

In addition, the signal terminal group matching circuit 39 is located in the redundant logic unit and is matched with different signal terminal network nodes. In this case, the logic unit and the node transmit and receive data or the logic unit and the node transmit and receive data according to the operation and standby state of the logic unit in a state where there is no obstacle between the logic unit and the node. Only the logic part that is in operation sends data in the node width and sends the data received from the node to the signal terminal bus. At this time, if an alarm signal is received from a node transmitting or receiving data, the signal terminal group matching circuit 39 automatically connects to another node that does not send an alarm, and transmits and receives a message and then reconnects to a normal state when a failure is recovered. In the connection between the group and the signal terminal network node, cross connection is realized to maximize the reliability of the signal terminal group.

The logic unit configures the above functions as logic circuits, and when an error is detected, an interrupt is sent to the processor unit so that the processor unit collects necessary data from the logic unit to determine a failure state and take necessary actions. In addition, the processor unit carries out the signal terminal group maintenance unit command or reads the signal terminal state through the logic unit. For this purpose, the data bus and address bus, instruction latch signal, interrupt, and logic unit are redundant between the processor unit and the logic unit. Put the control signal.

4 is a block diagram of a signal terminal group matching block in the logic unit B of the signal terminal group maintenance apparatus of the present invention. Signal terminal network node / signal message processing unit matching circuit 40 matches the signal terminal network node / signal message processing unit. In the signal terminal group bus loop back circuit 50 connected to the circuit 40 and the signal terminal network node / signal message processor matching circuit 40, Receive (Clear to Send Period) (Enable RTS) and (RTS Block) and LTO (Long Time Out) signal long time signal message processing unit transmission occupancy detection circuit 60 is configured according to the number of signal terminals and signal message processing unit signal terminal network node matching circuit 39 or signals The hardware is directly matched with a message processing unit (not shown) to handle the transmission and reception of messages. When there are a large number of signal message processing units, a signal terminal group and a signal terminal network are matched to communicate with a corresponding signal message processing unit, and when a small signal link is used, that is, two sets of signal message processing units and one signal terminal group are configured. In this case, it is possible to directly interwork with the signal terminal group and the signal message processing unit without the signal terminal network node, resulting in cost reduction effect due to the reduction of hardware quantity. In order to connect up to 32 signal terminals and signal terminal maintenance devices connected to the signal terminal bus with higher-level hardware, a common interface must exist so that the logic part B of the signal terminal maintenance device can realize this.

The signal terminal network node / signal message processing unit matching circuit 40 includes a signal terminal network node / signal message processing unit matching buffer 41 and a signal terminal network node / signal message processing unit matching control circuit 42. It enables physical connection with the terminal network node 5 and the signal message processor. The signal terminal network node / signal message processing unit matching buffer 41 is composed of a plurality of drivers / receivers transmitted and received as differential signals, and is selected by the signal terminal network node / signal message processing unit matching control circuit 42 under the control of the selected signal terminal network node. Communicate with the signal message processor. Signal terminal The signals communicating with the network node / signal message processing unit are received data (URXD), receive clock (RXCLK), transmit data (UTXD), transmit clock (UTXCLK), transmit alarm (UTXALM) and receive information (URXALM) signals. It is configured to be used when connecting with signal terminal network node or signal message processing unit, and RTS (Request to Send) and CTS (Clear to Send) signals are used only when communicating with signal message processing unit. Data (URXD, UTXD) is transmitted and received in synchronization with the clock (URXCLK, UTXCLK), the timing is adjusted to be sent on the falling edge of the clock and received on the rising edge of the clock. The signal terminal network node / signal message processing unit matching control circuit 42 is received from the signal terminal network node / signal message processing unit matching buffer 41. , ALM (Alarm) signal and bus selection status signal (SEL) received from the redundancy control circuit, mode selection signal ( / DIR), which is output from the counter 62 (Enable RTS) signal, the signal message processing unit transmission blocking instruction latch 63 is input from the received RTSB (RTS Block) signal, the long time signal message processing unit transmission occupancy interrupt generation latch 64 It implements PAL (Programming Array Logic) method using (Long Time Out) signal and determines communication path with higher level. The data and clock to be transmitted and received are implemented to be transmitted between the normal signal terminal maintenance unit logic unit and the normal signal terminal network node / signal message processing unit.

Even if a failure occurs in one of the devices, the protocol is set to transmit and receive from a normal device. If all devices are normal, the initial state is given priority to communicate in the determined direction. In case of directly interworking with the signal message processing unit, data collision occurs when two sets of signal message processing units transmit data to one set of signal terminal groups. To use RTS and CTS signals. If one side of the signal message processing unit is in an error state, the RTS and CTS signals are meaningless. If all of the signals are normal, if there is a message to be sent by the signal message processing unit, the RTS signal is applied and the output of the counter 62 serving as an arbitration role is output. The CTS signal is transmitted to the signal message processing unit corresponding to the PAL type using the signal. The signal message processor that receives the CTS signal transmits data and recovers the RTS signal, thereby providing a transmission opportunity to the counter signal message processor.

The signal terminal group bus loopback circuit 50 receives an inverter I to which an LPBK (loop-back) signal is input, an output signal of the signal terminal network node / signal message processing unit matching buffer 41, and receives RXD (Recelve Data). (B1) and TXD (Transmit Data) are inputted to the enable terminal and LPBK (Loop-Back) signal is input to the enable terminal, RXD is sent out, and the output of the inverter (I) is transmitted to the enable terminal. A ramp driving circuit 51 is connected to an input buffer B2, an enable terminal of the buffer B2, and an output terminal of the inverter I.

The signal terminal group bus loop back circuit 50 loops the transmission / reception data lines using the LPBK signal of the input / output port circuit 30 to be useful for performing the signal terminal group bus test at the signal terminal network node / signal message processing stage. Can be used. The long time signal message processing unit transmission occupancy detection circuit 60 includes a multivibrator 61, a counter 62, a signal message processing unit transmission interruption instruction latch circuit 63, and a long time signal message processing unit transmission occupation interrupt generation latch circuit 64. When interworking with the signal message processing unit, it detects the signal message processing unit occupying the RTS signal for more than a specified time, and simultaneously transmits the transmission opportunity to the other signal message processing unit. It performs the function. The multivibrator 61 is a signal indicating that data is being transmitted from the signal message processor. When the time is measured by inputting (CTS Period) and the RTS signal is occupied for the maximum message transmission time or more, the clock CK is generated to generate the INTCTS (Interrupt CTS) signal. The counter 62 uses NTXCLK2 (Network Transmit Clock) of the clock generation circuit. Generates (Enable RTS) signal It is used to act as a mediator to stop when a signal is received. On the other hand, the signal inputted by the signal message processing unit which generates an RTSB (RTS Block) signal by using the IDB0-IDB1 of the processor unit and the RTSBLK (RTS Block) signal of the input / output port circuit. Block reception.

The long term signal message processor transmission occupancy interrupt generation latch 64 is transmitted by the signal terminal network node / signal message processor matching control circuit 42. Receive the signal Sends a signal and receives the clock CK from the multivibrator 61 Send a signal.

As described above, the present invention is configured to enable signal terminal network node matching and direct matching with the signal message processing unit according to the signal terminal capacity and the signal message processing unit in matching signal terminal groups in the common line signal device of the electronic exchange. Economical and effective

Claims (5)

In a signal terminal group matching circuit of an electronic exchange; A signal terminal group bus loopback means 50 connected to the signal terminal network node / signal message processing unit matching means 40, the signal terminal network node / signal message processing unit matching means 40, and looping transmission and reception data lines; Connected to the terminal network node / signal message processing unit matching means 41 Long Time Out signal Send the (Enable Request to Send) signal and the RTSB (RTS Block) signal. (Clear to Send Period) A signal terminal group matching circuit, characterized in that it comprises a long time signal message processing unit transmission occupancy detecting means (60) for inputting a signal. The signal terminal network node / signal message processing unit matching means 40 includes: received data URGD, received clock URGCLK, received alert URGALM and RTS; Receive (Clear to Send) signal and transmit data (UTXD), transmit clock (UTXCLK), transmit alarm (UTXALM), CTS (Request to Send) and a signal terminal network node / signal message processing unit matching buffer means 41 for transmitting an ALM (Alarm) signal, a bus selection status signal SEL, a mode selection signal ( / DIR), (Enable RTS), (Long Time Out), RTSB (RTS Block) And ALM signals and are connected to the signal terminal network node / signal message processing unit matching buffer means 41. Wow And a signal terminal network node / signal message processing unit matching control means (42) for transmitting a signal (CTS Period). The signal terminal group bus loop back means 50 is connected to an inverter I to which an LPBK (Loop-Back) signal is input, and to the signal terminal network node / signal message processor matching means 41. The first buffer B1, TXD (Transmit Data) is input, the RXD is transmitted, and the enable terminal is the inverter. The output signal is input, the RXD (Receive Data) is transmitted, and the LPBK signal is input to the enable terminal. The second buffer (B2) is connected to the output terminal of (I), the enable terminal of the second buffer (B2) and the lamp driving means 51 connected to the output terminal of the inverter (I) Signal terminal group matching circuit. 2. The signal occupancy transmitter 60 according to claim 1, wherein said long term signal message processor transmission occupancy detecting means 60 is connected to said signal terminal network node / signal message processor matching control means 42. Connected to the signal terminal network node / signal message processing unit matching control means 42 for receiving a signal and transmitting a clock CK; Receive the signal and receive the NTXCLK2 (Network Transmit Clock) signal. It is connected to the counter 62 for transmitting a signal and the signal terminal network node / signal message processing unit matching control means 42 to output an RTSB by inputting an RTSBLK (RTC Block) signal and an IDB0-IDB7 (Internal Data Bus). A signal message processing unit transmission block command latching means 63 and the signal terminal network node / signal message processing unit matching means 42 and the multivibration 61 are connected to the LTO signal. A signal terminal group matching circuit comprising a long time signal message processor transmission occupancy interrupt generation latch means 64 for receiving a signal and a clock CK and transmitting an INTCTS signal. The signal terminal group matching circuit according to claim 2, wherein the signal terminal network node / signal message processing unit matching control means (42) is constituted by a programmable array logic (PAL).