JPS56149625A - Data transfer control system - Google Patents

Data transfer control system

Info

Publication number
JPS56149625A
JPS56149625A JP5254680A JP5254680A JPS56149625A JP S56149625 A JPS56149625 A JP S56149625A JP 5254680 A JP5254680 A JP 5254680A JP 5254680 A JP5254680 A JP 5254680A JP S56149625 A JPS56149625 A JP S56149625A
Authority
JP
Japan
Prior art keywords
instruction
bytes
adaptor
channel
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5254680A
Other languages
Japanese (ja)
Other versions
JPH0146890B2 (en
Inventor
Tomohito Shibata
Noboru Yamamoto
Tomoharu Hoshino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5254680A priority Critical patent/JPS56149625A/en
Publication of JPS56149625A publication Critical patent/JPS56149625A/en
Publication of JPH0146890B2 publication Critical patent/JPH0146890B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To prevent a malfunction of an I/O, by performing a check through an I/O adaptor with every instruction (2 bytes) given from a channel and then sending the instruction to the I/O only when the 2 bytes are normal. CONSTITUTION:When the I/O adaptor 9 receives an instruction (composed of the 1st and 2nd bytes) given from the main processor 1 or channel 2, the adaptor 9 stores the 1st byte A of the instruction in the buffer register 3 to perform a parity check 7 and then produces the final signal F with detection of an error to complete a transfer of instruction with the channel. At the same time, a parity check 7 is given also to the 2nd byte B to detect an error as well as complete a transfer of instruction with the channel 2. Then the adaptor 9 transmits in series both the 1st and 2nd bytes A and B of the registers 5 and 4 to the I/O 13 via the gate 6 only when the two bytes of instruction are normal.
JP5254680A 1980-04-21 1980-04-21 Data transfer control system Granted JPS56149625A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5254680A JPS56149625A (en) 1980-04-21 1980-04-21 Data transfer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5254680A JPS56149625A (en) 1980-04-21 1980-04-21 Data transfer control system

Publications (2)

Publication Number Publication Date
JPS56149625A true JPS56149625A (en) 1981-11-19
JPH0146890B2 JPH0146890B2 (en) 1989-10-11

Family

ID=12917784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5254680A Granted JPS56149625A (en) 1980-04-21 1980-04-21 Data transfer control system

Country Status (1)

Country Link
JP (1) JPS56149625A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220819A (en) * 1983-05-30 1984-12-12 Fujitsu Ltd Resetting circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220819A (en) * 1983-05-30 1984-12-12 Fujitsu Ltd Resetting circuit
JPH037983B2 (en) * 1983-05-30 1991-02-04 Fujitsu Ltd

Also Published As

Publication number Publication date
JPH0146890B2 (en) 1989-10-11

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