JPS57159353A - Failure processing system - Google Patents

Failure processing system

Info

Publication number
JPS57159353A
JPS57159353A JP56045815A JP4581581A JPS57159353A JP S57159353 A JPS57159353 A JP S57159353A JP 56045815 A JP56045815 A JP 56045815A JP 4581581 A JP4581581 A JP 4581581A JP S57159353 A JPS57159353 A JP S57159353A
Authority
JP
Japan
Prior art keywords
output
gate
response signal
system control
continuance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56045815A
Other languages
Japanese (ja)
Inventor
Hiroshi Iiyama
Akinori Usui
Mitsuo Ibori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56045815A priority Critical patent/JPS57159353A/en
Publication of JPS57159353A publication Critical patent/JPS57159353A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Abstract

PURPOSE:To achieve early detection of bugs and efficient sytem operation, by setting either one mode of system control continuance or system control interruption in accordance with the types of a failure. CONSTITUTION:An FF6 determines the continuance of system control when an output is at (0) with the instruction of the software or the hardware and determines interruption when (1). When the output of the FF6 is at (0), if an error takes place, and AND gate 17 is at on-state and the selected output of a selection circuit 9 is tranmitted to a computer system via the gate 17. An AND gate 16 is also at on-state and a response signal from a register control circuit 8 is transmitted to a processor 2 via the gate 16. The device 2 analyzes the response signal and makes rewrite processing as required. On the other hand, when the output of FF6 is at (1), if an error takes place, the output of an NAND gate goes to (0), the gates 16 and 17 turn off, and the generation of the error can be recognized, because the device 2 has no response signal.
JP56045815A 1981-03-28 1981-03-28 Failure processing system Pending JPS57159353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56045815A JPS57159353A (en) 1981-03-28 1981-03-28 Failure processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56045815A JPS57159353A (en) 1981-03-28 1981-03-28 Failure processing system

Publications (1)

Publication Number Publication Date
JPS57159353A true JPS57159353A (en) 1982-10-01

Family

ID=12729739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56045815A Pending JPS57159353A (en) 1981-03-28 1981-03-28 Failure processing system

Country Status (1)

Country Link
JP (1) JPS57159353A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59101830A (en) * 1982-12-01 1984-06-12 Canon Inc Printing and exposure device for semiconductor
JPS59116858A (en) * 1982-12-23 1984-07-05 Fujitsu Ltd Machine check interruption processing system
JPH01233630A (en) * 1988-03-15 1989-09-19 Nec Corp File processing system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028239A (en) * 1973-07-11 1975-03-22
JPS51146143A (en) * 1975-06-11 1976-12-15 Hitachi Ltd Wedging process mode when logic device generates error action

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028239A (en) * 1973-07-11 1975-03-22
JPS51146143A (en) * 1975-06-11 1976-12-15 Hitachi Ltd Wedging process mode when logic device generates error action

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59101830A (en) * 1982-12-01 1984-06-12 Canon Inc Printing and exposure device for semiconductor
JPH0141012B2 (en) * 1982-12-01 1989-09-01 Canon Kk
JPS59116858A (en) * 1982-12-23 1984-07-05 Fujitsu Ltd Machine check interruption processing system
JPS6322339B2 (en) * 1982-12-23 1988-05-11 Fujitsu Ltd
JPH01233630A (en) * 1988-03-15 1989-09-19 Nec Corp File processing system

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