JPS63240658A - Memory device - Google Patents

Abstract

PURPOSE:To shorten the memory access time and to decrease the number of input/output pins of a memory controller MCU by outputting the data read out of a RAM directly onto a system bus. CONSTITUTION:A data part and an error correction code are outputted to a system bus 5 from a RAM 200 and sent back directly to a requester by the read requests given from an arithmetic processor EPU 3 and input/output controllers IOC 41 and 42. In this case, an MCU 100 checks the presence or absence of a correctable error of the data part of the data outputted onto the bus 5. If no correctable error is detected, this fact is informed to the requester and the data is processed as it is. When an error is detected, the RAM 200 is inactivated and the corrected data is outputted onto the bus 5. Thus the requester reads out the corrected data and uses it as its request data. Therefore no intervention of the MCU 100 is needed so that the memory access time is shortened and the number of pins of the MCU 100 is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to memory devices, and more particularly to memory devices connected to a system bus in a data processing system.

[Conventional technology]

There are many types of memory devices that add a parity section to the data section to be transmitted and are connected to the transmission system bus and store information having an error correction code. It was constructed as shown in Figure 3.

In the data processing system shown in FIG.
Controller UniL) 6 and a memory element (hereinafter referred to as RAM (Random Access M
An arithmetic processing unit (hereinafter referred to as EPU)
) 8 and the input/output side 1n
Vjt'll (hereinafter referred to as IOC (Input 0ut
put Contr.

(1 unit) 91 and 92.

In this data processing system, data read from the RAM 7 is error checked by the MCU 6 and output to the system bus IO. Furthermore, if a correctable error is detected in the output from the RAM 7, the error is corrected by the MCU 6 and then output to the system bus 10.

In addition, in the case of writing information with an error correction code to the RAM 7, an error correction code based on the data part of the information with an error correction code is added by the MCIJ 6, and is supplied to the RAM 7 and written together with the data part.

[Problem that the invention seeks to solve]

In the conventional memory device described above, the data read from the RAM 7 is once input to the MCL164 and output to the system bus 10 after error checking, although it is not necessary if there is no correctable error. Therefore, there is a drawback that the delay time for information to pass through the MCU 6 increases and the number of input/output pins of the MCL 16 increases.

This drawback cannot be ignored and is being viewed as a problem, especially in recent years when logic elements and storage elements constituting data processing systems are becoming more and more VLSI-based, in consideration of other processing times and device volumes.

In view of the above-mentioned points, an object of the present invention is to output read data from RAM directly to a system bus, thereby making it possible to improve memory access time and
An object of the present invention is to provide a memory device that can reduce the number of input/output bins.

[Means for solving problems]

A memory device of the present invention is a memory device that is connected to a system bus that transmits information whose data section is protected by a parity section, and that stores information transferred by the system bus with an error correction code added thereto. data part output means for outputting a data part of information with an error correction code stored in a storage element at a designated address to the system bus in response to a read request sent through the system bus and returning the data part to the read request source; In response to a read request sent via the system bus, the error correction code of the information with error correction code stored in the storage element at the specified address is output to the system bus, and a part of the error correction code is output. error correction code output means for returning the parity part to the read request source, and reception means for inputting the data part outputted to the system bus by the data part output means and the error correction code outputted by the error correction code output means. Then, the presence or absence of a correctable error is determined based on the data part and error correction code inputted by the receiving means, and when a correctable error is detected, the data part output means and the error correction code output means are inactivated. an error detection and correction circuit that outputs a correctable error report signal onto the system bus, notifies the read request source of the error, corrects the data portion, generates a parity portion based on the corrected data portion, and outputs the correctable error report signal; An error correction data register that receives and holds the corrected data section output by the error detection and correction circuit and the parity section based on the corrected data section, and the corrected data held in this error correction data register. and a parity part based on the corrected data part to the system bus and return it to the read request source.

C Effect] In the memory device of the present invention, the data portion output means responds to a read request sent via the system bus and outputs the data portion of the information with error correction code stored in the storage element at the specified address. The error correction code output means outputs the error correction code to the system bus and returns it to the read request source, and the error correction code output means responds to the read request sent via the system bus. The error correction code of the information is output to the system bus, a part of the error correction code is read as a parity part, and returned to the source of the read request, and the receiving means outputs the data part and the error correction code output to the system bus by the data part output means. The error correction code outputted by the output means is input, and the error detection and correction circuit determines the presence or absence of a correctable error based on the data part and the error correction code inputted by the reception means, and when a correctable error is detected. The data part output means and the error correction code output means are made inactive, a correctable error report signal is outputted onto the system bus, the read request source is notified of the error, and the data part is corrected and the parity part is based on the corrected data part. The error correction data register receives and holds the corrected data part output by the error detection and correction circuit and the parity part based on the corrected data part, and the register information output means detects the error. The corrected data portion held in the corrected data register and the parity portion based on the corrected data portion are output to the system bus and returned to the read request source.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the memory device of the present invention.
100, a RAM 201 that stores the data part, and a RAM 202 that stores the error correction code (R
AM200 (a part of which is representatively shown in FIG. 2).

MC [Jloo is driver circuit 101, IO2,
103.

106 and 109 (driver circuits 102 , 103 and 106 can have their operating states controlled by control circuit 114 ), and receiver circuits 104 , 105 , 1
07 and 108, and an error detection and correction circuit (hereinafter referred to as EC
CCError Checking and C.

110
and error correction data register (ECR).
or Correcting data Reg
ister) 111, and an error correction code generation circuit (hereinafter referred to as ECG) 111.
code GeneraLor) 112
, an address determination circuit 113 , and a control circuit 114 .

RAM2O1 is configured to include a receiver circuit 210 and a driver circuit 220 (the operating state of which can be controlled from the control circuit 114 of MCUloo).

The RAM 202 includes a receiver circuit 211 and a driver circuit 221 (the operating state of which can be controlled by the MCUloo control circuit 114).

Typical signals transmitted by the system bus 5 (see Figure 2) to which this memory device is connected include:
A bus request signal (hereinafter referred to as a bus request signal) is a signal that indicates the contents of a command such as a memory read command and requests processing along with information such as an address signal (hereinafter referred to as an ADR signal) and a data bit signal (hereinafter referred to as a DTB signal).
BRQ (referred to as No. 3) and notification of write operation completion when there is a write request, and D when there is a read request.
An acknowledge signal (hereinafter referred to as ACK signal) that notifies the timing of returning the TB signal and an address of the RAM 200 are specified (for example, when specifying an address space of 1 megaword as I, 20 data bits and ADH signal, a 16-bit DTB signal indicating the data section, and a 2-bit parity signal (part of which indicates the parity section).
When a read request is made in accordance with the PTY signal (hereinafter referred to as the PTY signal), the PTY signal is expressed as a 5ED-DED-3BD code (see Figure 4) that is directly returned to the read request source and indicates an error correction code. An error correction digit signal (hereinafter referred to as ECD signal) consisting of 8 bits and a RAM
If a correctable error occurs in the data section read from RAM 200, a correctable error report signal (hereinafter referred to as COR) notifies that the data section directly returned from RAM 200 requires correction and must not be used. There is a signal (called a signal).

In addition, from the control circuit 114 of MCUloo, the above-mentioned (7)
)ACK signal and RAM201 (D driver circuit 22
The operating state of the driver circuit 221, etc. of 0 and RAM M2O2 is enabled (operable state; the same applies below).
A read enable signal (hereinafter referred to as the REN signal) and a write enable signal (hereinafter referred to as the REN signal) that enables information to be written to the cells of RAM M2O1 and RAM202.
WEN signal) and MCUloo driver circuit 1
A write cycle signal (hereinafter referred to as WCY signal) that enables the operating state of MCUloo 06 and a correction cycle signal (hereinafter referred to as CCY signal) that enables the operating state of MCUloo driver circuits 102 and 103. Output.

In addition, in FIG. 1, receiver circuits 107 and 10
The function of the control circuit 114 to output the data part stored in the RAM M2O1 etc. to the system bus 5 by driving the driver circuit 220 etc. based on the input by B and the determination by the address judgment circuit +13 realizes the data part output means. Then, based on the input by the receiver circuits 107 and 108 and the judgment by the address 1'11 constant circuit +13, the error correction code 412 recorded in the RAM2O2 etc. is output to the system bus 5 by driving the driver circuit 221 etc. The function of the control circuit 114 realizes an error correction code output means, the function of the receiver circuits 104 and 105 which inputs the DTB signal and ECD signal to the ECC 110 realizes a receiving means, and the driver circuit 1
The function of the control circuit 114, which outputs the information held in the ECRIII to the system bus 5 by driving the registers 02 and 103, realizes register information output means.

FIG. 2 is a block diagram showing the configuration of a data processing system implemented including the memory device of this embodiment. This data processing system includes an EPU 3 that executes programs (command words) stored in the memory device of this embodiment and performs calculations;
A system bus 5 (for example, IEEE E796 Mul L 1-Bus) that provides a data transfer path (also transfers address information) between
A bus is used in which a parity line is added to the address line and data line of the I to enhance data integrity), input/output devices such as magnetic tape devices and magnetic disk devices (not shown), and books. It is configured to include 10Cs 41 and 42 that control data transfer with the memory device of this embodiment, and MCUloo and RAM 200 that constitute the memory device of this embodiment.

Referring to FIG. 4, the error correction code (ECD signal code) employed in the memory device of this embodiment is a code that corrects 1-bit errors and detects errors of 4 bits and 7 bits or less. , rlBMJournal or
RES, DEVELOP-VOL23・No2 M
ARCH'84Error-Correcting
CodeFor Sem1conductor
Mem.

ry AppliCaLiOnS:5Late-or
-the-Art ReviewJ rSED
-DED-3BD (Single Error C
orrecLing, DoubleError De
tecting and stingle byt
This code is introduced as e Error DeLecLing)J.

In FIG. 4, the exclusive OR of the bits shown as "1" among the 16 bits of the data bit (DTB) corresponds to "1" among the 8 pins of the error correction digit (ECD).
The bit shown by is corrected.

Therefore, digits 2 and 3 of this error correction code
(2nd bit, bit and 3rd bit) are the parity pins of byte 0 (0th to 7th bits) of the 0th to 7th bits of data bits (O of PTY) and byte 1, respectively.
(8th to 15th bits) respectively match the parity bit (1 of PTY).

Note that it goes without saying that other error correction codes can be applied to the memory device of the present invention as long as part of the error correction code corresponds to the parity bit added to the data bits.

Next, the operation of the memory device of this embodiment configured as described above will be explained.

BR indicating the memory read command that is the content of the read request output from El"U3 and 1Oc41 and 42.
The Q signal is received by the MCUloo receiver circuit 108 via the system bus 5, and the ADR signal indicating the address to be accessed, which is output together with the BRQ signal, is received by the MCUloo receiver circuit 107 via the system bus 5.

The received ADR signal is decoded by the receiver circuit 107, and the address determination circuit 113 determines whether the address is within the address range of RAM M2O0 including RAMs 201 and 202.
Br? through the receiver circuit 10B. The read request is notified by the Q signal). Further, the ADR signal is also distributed to the RAMs 201 and 202, etc.

When the address determination circuit 113 determines that an address in the RAM 200 is selected by the ADR signal (here, it is assumed that an address in an area including RAM M2O1 and 202 is selected), the control circuit 11
4, the PEN signal is distributed to the RAMs 201, 202, etc.

The ADR+ε signal decoded by the receiver circuit 107 and output from MCUloo is sent to RAM M2O1 and 20.
2, etc., the area of the cell corresponding to the address indicated by the ADR signal is read, and the PEN signal output from the control circuit 114 causes the RAM 201 and 202 to be read.
Driver circuits 220 and 22 provided at the output section of
The first class is enabled and driven. As a result, the DTB signal and the 2-bit PT
An 8-bit ECD signal including the Y signal is output, and a DTB signal indicating the data section and a PTY signal indicating the parity section are directly returned from the RAM 200 to the read request sources of the EPU 3 and [0C41 and 42 via the system bus 5. (
(The signal line that transmits 6 bits other than the PTY signal among the 8 bits of the ECD signal is not connected to the read request source.)
.

The DTB signal (data part) output to the system bus 5 and the ECD signal (error correction code) output from the RAM2O2 etc. are received by the receiver circuits 104 and 105 of MCUloo, and the ECCll0 detects a correctable error in the data part. Presence is checked.

If no correctable error is detected in the data section during this check, the control circuit 114 is notified of this, and
8CK (No. 3 is connected to the driver circuit 10 by the control circuit 114
9 to the EPU 3 and 1Oc 41 and 42 which are the sources of the read request.

When a correctable error is detected in the data portion by checking ECCll0, the driver circuit 101 is driven and a COR signal is transmitted to the read request source via the system bus 5 to notify the error.

Along with this, a corrected data section and a parity section based on the data section are generated in ECCll0 and ECRI
II.

Furthermore, if a correctable error is detected by ECCll0, the control circuit 114 will no longer output the PEN signal.
Driver circuit tPI22 such as RAM M2O1 and 202
0, 221, etc. are placed in a disabled state (inoperative state; the same applies hereinafter).

Furthermore, a correction cycle (a series of operations for correcting the correctable error) is activated, and the CCY
The signal is output to enable the driver circuits 102 and 103, and the corrected data section stored in the ECR 111 and the parity section based on the corrected data section are output on the system bus 5 as DTB (1 and PTY signals). The corrected data part and parity part are output to the IEPU 3 and 10C 41o and 42, which are the sources of read requests.
K signal is output).

EPU3 and IOC41 and 42 that are the read request sources
In this case, the data section directly sent from RAM M2O0 is invalidated by the notification of the COR signal, and the ECRI
Data section etc. sent from II (ACK without COR signal)
The timing of the return is notified by a signal) is used as the target information of the read request.

Finally, as a premise that the read operation is performed as described above, the operation in the case where a write request is made from the EPU 3 and the 10Cs 41 and 42 to the MCUloo and the RAM 2O0 will be described.

In this write operation, address determination and ADR signal distribution are the same as in the read operation described above.
DTB indicating the data part of the information written to RAM M2O0
(No. 3 and the PTY signal indicating the parity section are transmitted from the system bus 5 to the RA via receiver circuits 210 and 211, etc.)
It is directly supplied to M201 and 202, etc.

On the other hand, the 6 bits other than the parity part of the ECD signal indicating the error correction code are generated by the ECG 112 based on the DTB signal received via the receiver circuit 105 in the MCU 100 (the PTY signal is also input to the ECG 112 via the receiver circuit 104). The driver circuit 106 is driven to send the ECD signal to the RAM 2O via the system bus 5.
(Driver l!iJ path 106 is supplied to
It is enabled and driven by the wcy signal output from the control circuit 114 based on the Q signal).

In this way, the error correction coded information is stored in the RAM 20.
0, R A M2O0 instructed by the ADR signal from the control circuit 114 in MCU too
area of addresses within (for example, RAM 201 and 20
The WEN signal is output to the area (including area 2), and information with an error correction code is written into the RAM 200.

When this writing is completed, an ACK signal is output from the control circuit 114 via the driver circuit 109, and the EPU 3, 10c 41, and 42 that requested the writing are notified of the completion of the writing.

〔Effect of the invention〕

As explained above, the present invention makes it possible to improve memory access time by directly outputting the data part and parity part of information with error correction codes stored in the RAM to the system bus, thereby making it possible to improve the memory access time. This has the effect of reducing the number of input/output pins.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a data processing system including the memory device of this embodiment, and FIG. 3 is a block diagram showing the configuration of a data processing system including the conventional memory device. FIG. 4 is a block diagram showing the configuration of the processing system. FIG. 4 is a diagram showing the relationship between error correction codes and data bits used in the memory device of this embodiment. In the figure, 3...EPU. 5...System bus, 41, 42...IOc. 100...MCLI. 101, 102.103.106.109.220,2
21 ・Driver circuit, 104.105,107,1
08,210,211...Receiver circuit, 110
...ECC. 111...ECR. 112...ECG. 113... Address determination circuit, 114
. . . Control circuit, 200 to 202 . . . RAM.

Claims (1)

[Claims] A memory device in which a parity part is connected to a system bus for transmitting protected information, and the memory device stores information transferred by the system bus with an error correction code added thereto. a data part output means for outputting a data part of information with an error correction code stored in a storage element at a specified address to a system bus in response to a read request sent by the system; In response to a read request sent via the bus, an error correction code for information with an error correction code stored in a storage element at a specified address is output to the system bus, and a part of the error correction code is parity-coded. an error correction code output means for returning the error correction code to the read request source as a part; and a reception means for inputting the data part outputted to the system bus by the data part output means and the error correction code outputted by the error correction code output means. , The presence or absence of a correctable error is determined based on the data part and error correction code inputted by the receiving means, and when a correctable error is detected, the data part output means and the error correction code output means are put into an inoperable state. an error detection and correction circuit that outputs a correctable error report signal onto a system bus to notify a read request source of an error, corrects a data section, generates a parity section based on the corrected data section, and outputs the error; an error correction data register that receives and holds a corrected data section output by the detection and correction circuit and a parity section based on the corrected data section; and a corrected data section held in the error correction data register. and register information output means for outputting a parity part based on the corrected data part to a system bus and returning it to a read request source.