JPS58199498A - Memory system - Google Patents

Abstract

PURPOSE:To improve system performance by providing a memory with minimum write bit width array of data, plural unit arrays having ECC bit width arrays corresponding to them, and data line which are plural times as many as write and ECC bit width. CONSTITUTION:A memory bus 5 has a data line 6 whose bit width is twice as great as the 32-bit width of an RAM chip array for transmitting and receiving read/ write data, an ECC information line 7 whose bit width is twice the 7-bit width corresponding to it, an address line 8, and a timing and mode signal line 9 for the RAM chip arrays 1a and 1b stored with, for example, 32-bit data and RAM unit arrays of RAMs 2a and 2b stored with 7-bit ECC codes. Consequently, the compatibility between computers which differ in access width is obtained easily and the system performance is improved.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention uses an error detection/correction code (hereinafter referred to as a Hamming code) to improve reliability.
The present invention relates to a main storage device (hereinafter referred to as memory) system which is equipped with a frror Correcting Code.

[Background technology of the invention]

Conventionally, in memory systems equipped with ECC, the memory access width (read/write bit width) has been expanded in order to improve system performance.
The above ECC needs to generate a constant for the access unit width (number of bits), so when writing in a unit smaller than the access width when writing to memory, the data read from memory and the data to be written are I repacked it, generated ECC, and wrote it.

[Problems with background technology]

As described above, the conventional writing method has the disadvantage that two memory cycles are required when writing data whose width is narrower than the access unit.

[Purpose of the invention]

The present invention is an arithmetic and control unit (hereinafter referred to as CPU) that uses memory.
In order to improve the system performance by shortening the write time to the memory that is used most often by the channel device (CM) and the channel device (hereinafter referred to as CM), we also aim to improve the system performance. The purpose of CH incompatibility due to differences in access width is to prevent system performance from deteriorating.

[Summary of the Invention] In order to achieve the above object, the present invention provides a memory with a plurality of unit arrays each having a minimum input bit width array for data and a corresponding ECC bit width array; A data line having a bit width multiple times the Y bit width and an FCC code line having a bit width multiple times the VCC bit width as described above are provided so that the unit arrays can be accessed by arbitrarily combining them. This is what I did.

[Embodiments of the invention]

FIG. 1 is a block diagram showing one embodiment of the present invention. In the same figure, (1) [(la), (lb)...
] are RAM chip arrays each storing, for example, 32 bits of data, (2) C(2a), (2b)...
] is a GCC chip array composed of a RAM each storing, for example, a 7-bit ECC code. (3)
C(3a), (3b)...] are addresses for accessing both chip arrays.

This is a driver and timing generation circuit. (4) is this address driver/timing generation circuit (3a).

This is a control circuit for starting access for (3b). (5) is a memory bus to which a memory board having the above circuit is connected, a RAM for transmitting/receiving read/write data, and a 32-bit chip array multiplied by m (in the example of Fig. 1, m = The data line (6) has a bit width of 2), and a timing and mode signal line (9) for controlling information on the memory bus.

Next, the operation shown in FIG. 1' will be explained. The data line (6) and ECC information line (7) on the memory bus have widths of, for example, 64 bits and 14 bits, respectively.

Also, the R built in the memory board connected to the memory bus
32-bit data of each of the AM chip arrays (la) and (lb) and the ECC chip array (2a).

Two circuits of the 7-bit ECC code of (2b) are the (64+14)-bit data line (6) of the memory bus.
interfaced to.

The above memory board allows address modes of read (64 bits), write word (32 bits), and write-enabled double word (64 bits).

For 64-bit read/write, the control circuit (4) discriminates the mode signal and timing signal placed on the access mode line (9), and the address driver/timing generation circuit (3a), (3b) ), the access start signal is transmitted to the RAM chip play (ta),
(tb), 64-bit memory access is performed to the ECC chip arrays (2a) and (2b). The same goes for the write word (32 bits), but in the control circuit (4), the RAM, ECC chip playback (la
, 2a) or RAM, ECC chip array (lb, 2
b) to be accessed using the address line (8).
) is determined based on the address information that overlaps with the address driver and timing generator circuit (3a) or (3).
A 32-bit write is performed by passing a meta signal to b). In addition, these are ECC in units of 32 bits.
This is possible because the code and ECC chip arrays (2a) and (2b) are added.

〔Effect of the invention〕

The present invention is as described above, and (1) most memory write operations are completed in one memory cycle, resulting in improved system performance.

1i) Connection compatibility such as channel configuration is facilitated between computer systems with the same architecture but different memory access for performance reasons. There are other effects.
□

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention.゛la, lb...; iAM chip array that stores data 2a, 2b...; ECC that stores UCC
Chip array 3a, 3b...; Address driver/timing generator circuit 4; Control circuit 5; Memory bus □ 6; Data line 7; Ece information line 8; Address line 9; Timing and mode signal line (3257) agent Patent Attorney Inoue - Male Figure 1

Claims (1)

[Claims] This memory system has an error detection/correction code added, and this memory system has a data line consisting of rLxm bits, where the minimum bit width for writing to the memory is a path bit, and an error code corresponding to the path bit. If the bit width of the detection/correction code is X bits, x
a memory bus having an error detection/correction code line consisting of xm bits, and a memory bus having an error detection/correction code line consisting of
+ A memory board with a Z-bit RAM array on the shoulder side,
A memory system characterized in that each of the RAM arrays described above can operate independently and can be accessed in any combination.