CN116959540A - Data verification system with writemask - Google Patents
Data verification system with writemask Download PDFInfo
- Publication number
- CN116959540A CN116959540A CN202311031939.XA CN202311031939A CN116959540A CN 116959540 A CN116959540 A CN 116959540A CN 202311031939 A CN202311031939 A CN 202311031939A CN 116959540 A CN116959540 A CN 116959540A
- Authority
- CN
- China
- Prior art keywords
- memory
- data
- bit
- bits
- written
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013524 data verification Methods 0.000 title claims abstract description 17
- 230000015654 memory Effects 0.000 claims abstract description 203
- 238000013500 data storage Methods 0.000 claims abstract description 20
- 238000004590 computer program Methods 0.000 claims abstract description 13
- 230000003068 static effect Effects 0.000 claims description 15
- 238000012795 verification Methods 0.000 claims description 10
- 238000012545 processing Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 11
- 230000000875 corresponding effect Effects 0.000 description 71
- 230000008569 process Effects 0.000 description 7
- 239000002699 waste material Substances 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000002596 correlated effect Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention relates to the technical field of chips, in particular to a data verification system with a write mask, which comprises N chip internal memories { M } arranged in a preset chip 1 ,M 2 ,…,M n ,…M N Memory and processor storing computer program, where M n The method comprises the steps of presetting an nth internal memory in a chip; m is M n The corresponding ECC bit number is A n The number of bits of the ECC check code is G n ，M n The corresponding write mask bit number is B n ，M n The corresponding data writing bit width is C n ，M n The corresponding memory bit width is D n ，C n ≥A n ，C n ≥B n ，M n Comprises a check identification bit G n Bit ECC check code stores bits and C n Bits are written to the data storage bits. The invention improves the flexibility of data verification and reduces the chip surfaceAnd the product is wasted, and the chip performance is improved.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a data verification system with a write mask.
Background
The chip may include a plurality of different on-chip memories, such as Static Random Access Memory (SRAM), latch Array (Latch Array), etc. When the internal memory of the chip is impacted by high-energy particles, errors may exist in the stored data due to radiation interference, so that an error correction code (Error Correcting Code, abbreviated as ECC) can be set for the internal memory of the chip, and the accuracy of the data is checked through the ECC code. Each chip internal memory has a corresponding write data bit width, but typically not all data corresponding to the write data bit width is updated at the same time, so that only the data that needs to be changed is changed by masking the data that does not need to be changed with a write mask (Writemask).
In the prior art, an ECC protection mechanism is usually implemented separately for a memory inside a chip, or a write mask is implemented separately, if the ECC protection mechanism and the write mask are required to be implemented simultaneously for the same memory inside the chip, the ECC bits and the write mask bits need to be aligned strictly, otherwise, data collision occurs. As the exponent of the ECC number of bits increases, the corresponding parity number of bits increases linearly. For example, in a certain chip, the number of bits of the write mask corresponding to 10% of operations is 8 bits, and the number of bits of the write mask corresponding to 90% of operations is 32 bits, if the operations with 32 bits of the write mask are processed, if the number of bits of the ECC is set to 32 bits, each 32 bits of data corresponds to 7 bits of check bits, the number of check bits can be greatly reduced, and 90% of operations can be protected. If the protection completeness is considered, the ECC protection needs to be 8bit granularity, and each 8bit data corresponds to 5bit check bits, so that the chip area is wasted. Therefore, the aligned ECC bits and the write mask bits are arranged on different internal memories of the same chip, so that the chip area is wasted, data verification with smaller granularity than the ECC bits cannot be realized, and the data verification flexibility is poor. In addition, if the ECC bits and the write mask bits are not aligned, the data stored in the chip at the present can be read by the position corresponding to the write mask, and then the data is spliced with the data to be written currently to generate the ECC check code, but a large amount of time is consumed, the number of times of reading the data is increased, and the performance of the chip is reduced.
Disclosure of Invention
The invention aims to provide a data verification system with a writing mask, which improves the flexibility of data verification, reduces the waste of chip area and improves the chip performance.
According to a first aspect of the present invention, there is provided a data verification system with a writemask, comprising a memory device arranged to store dataPresetting N chip internal memories { M 1 ,M 2 ,…,M n ,…M N Memory and processor storing computer program, where M n N is a value range of 1 to N for an N-th internal memory in a preset chip; m is M n The corresponding ECC bit number is A n The number of bits of the ECC check code is G n ，M n The corresponding write mask bit number is B n ，M n The corresponding data writing bit width is C n ，M n The corresponding memory bit width is D n ，C n ≥A n ，C n ≥B n ，M n Comprises a check identification bit G n Bit ECC check code stores bits and C n Writing bits into the data storage bits; when the processor executes the computer program, the following steps are implemented:
step S1, obtaining M n The data information to be written comprises data to be written, write mask information to be processed and address information to be written;
step S2, if the information of the to-be-processed writing mask is empty, executing step S3, otherwise, judging A n Whether or not to be equal to B n If so, executing step S3, if not, setting the check identification bit corresponding to the address information to be written as a first identification bit, and storing the data to be written into C corresponding to the address information to be written n Writing the bits into the data storage bits, wherein if the check identification bits are the first identification bits, ECC check operation is not performed when the data of the corresponding written data storage bits are read;
step S3, M is taken as n Setting a check identification bit corresponding to address information to be written into as a second identification bit, performing ECC processing on data to be written into to generate an ECC check code, and storing the ECC check code into G corresponding to the address information to be written into n Bit ECC check code stores bits, and stores the data to be written into C corresponding to the address information to be written n Writing the bits into the data storage bits, wherein if the check identification bit is the second identification bitAnd when the data of the corresponding written data storage bit is read, performing ECC check operation.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the data verification system with the writing mask provided by the invention can achieve quite technical progress and practicality, has wide industrial utilization value, and has at least the following beneficial effects:
the system can flexibly set the number of bits of the write mask and the number of bits of the ECC, and has the flexibility of setting the number of bits of the ECC and the area of a chip, so that the flexibility of data verification is improved, the waste of the area of the chip is reduced, and the performance of the chip is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a data verification process with writemask provided by an embodiment of the invention;
fig. 2 is a flow of generating a target combined memory according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
Example 1
An embodiment one provides a data verification system with write mask, comprising N chip internal memories { M } arranged in a preset chip 1 ,M 2 ,…,M n ,…M N A memory storing a computer program, and a processor.
Note that, since memories in chips are various, the memory bit widths of N memories in chips may be different, and the number of address lines may be different. For example, the chip internal memory may include an internal memory with a size of 1024×32, or may include an internal memory with a size of 32×16, and the internal memory of the chip may be specifically a Static Random Access Memory (SRAM) or a Latch Array (Latch Array), etc.
Wherein M is n The value range of N is 1 to N, and N is the total number of the internal memories of the chip. M is M n The corresponding ECC bit number is A n The number of bits of the ECC check code is G n I.e. M n In A way n ECC encoding for granularity, every A n Bit data generation G n Bit ECC check code, and with A n Is increased by an index of (C), corresponding to G n Is linearly increasing. For example, A n When equal to 8, corresponding G n Equal to 5; a is that n Equal to 16, corresponding G n Equal to 6; a is that n Equal to 32, corresponding G n Equal to 7, etc. M is M n The corresponding write mask bit number is B n I.e. M n In B way n A writemask operation is performed for granularity. M is M n The corresponding data writing bit width is C n ，M n The corresponding memory bit width is D n ，C n ≥A n ，C n ≥B n ，Wherein (1)>Representing an upward rounding. M is M n Comprises a check identification bit G n Bit ECC check code stores bits and C n Bits are written to the data storage bits. I.e. each M n The number of ECC bits and the number of writemask bits may be set according to the specific case of the memory, and may not be aligned exactly. For example, for data write bit width C n Equal to1024, and can use the ECC bits A according to the application requirement n Set to 512, corresponding G n Equal to 11, 1024 bits of data requires 22 bits of storage ECC check code. However, if the number of ECC bits and the number of writemask bits are required to be kept aligned, the number of writemask bits, ECC bits and the number of writemask bits, are set to 8, then A is required to be n Setting to 8, every 8 bits need to store 5 bits of ECC check code, 1024 bits of data need 640 bits of ECC check code, and huge area is needed to be consumed, so that the ECC bits and the write mask bits are flexibly set, waste of memory bits in a chip can be avoided, and the area of the chip is greatly reduced.
As shown in fig. 1, when the processor executes the computer program, the following steps are implemented:
step S1, obtaining M n The data information to be written comprises data to be written, write mask information to be processed and address information to be written.
Wherein, in particular, by connection to M n The first connection line of (2) acquires the data to be written by being connected to M n The second connection line of the memory card obtains the information of the write mask to be processed by being connected to M n And acquiring the address information to be written in by the third connecting line. It is understood that the first connection line is a data line and the third connection line is an address line. The write mask information includes information whether each bit in the current data to be written requires a write mask operation, such as may be identified by 0 and 1, specifically by 1 to identify that the bit requires a mask operation, 0 to identify that the bit does not require a mask operation, and mask operation B n Is performed for particle size.
Step S2, if the information of the to-be-processed writing mask is empty, executing step S3, otherwise, judging A n Whether or not to be equal to B n If so, executing step S3, if not, setting the check identification bit corresponding to the address information to be written as a first identification bit, and storing the data to be written into C corresponding to the address information to be written n Bit writing data storage bit, wherein if the check identification bit is the first identification bit, ECC check operation is not performed when reading the data of the corresponding writing data storage bit。
Step S3, M is taken as n Setting a check identification bit corresponding to address information to be written into as a second identification bit, performing ECC processing on data to be written into to generate an ECC check code, and storing the ECC check code into G corresponding to the address information to be written into n Bit ECC check code stores bits, and stores the data to be written into C corresponding to the address information to be written n And writing the bits into the data storage bits, wherein if the check identification bits are the second identification bits, ECC check operation is performed when the data of the corresponding written data storage bits are read.
It can be understood that if the write mask information to be processed is null, no conflict between the write mask and the ECC check occurs, and therefore, the corresponding ECC check code is directly written and generated. If the information of the to-be-processed write mask is not null, at A n Equal to B n In this case, since the write mask and the ECC check do not collide with each other, the corresponding ECC check code may be directly written and generated. When A appears n Not equal to B n When the data to be written is written, the conflict between the writing mask and the ECC check occurs, and whether the data to be written is subjected to ECC protection or not is marked by adding a one-bit check identification bit in the internal memory of the chip. It should be noted that, although the conflict between the write mask and the ECC check occurs, the current data to be written is directly not subjected to ECC protection, on the one hand, a will be caused by n And B n The arrangement of the chip is very flexible, and the area of the chip is greatly reduced; on the other hand, in the whole chip, it is necessary to add A n And B n The transmission scene ratio set as unaligned is very low and is not more than 10 percent, in addition, the probability of error of the internal memory of the chip is very low, and the obtained error rate is lower by multiplying the two, so that the chip can tolerate. Therefore, the invention can also carry out ECC protection on more than ninety percent of data on the basis of greatly saving the chip area, and the probability of error occurrence of unprotected data is extremely low. And the subsequent logic of the chip can also carry out protection operations such as reset and the like at intervals, and can further process error data.
As an embodiment, when the processor executes the computer program, the following steps are also implemented:
step S100, reading M n Target verification identification bit corresponding to the target address in the computer system, if the target verification identification bit is the first identification bit, directly reading C corresponding to the target address n The data in the bit write data storage bits is used as target data corresponding to the target address.
It can be understood that if the target verification identification bit is the first identification bit, it is indicated that the data is not subjected to ECC protection, and ECC verification is not required, so that error reporting is avoided.
As an embodiment, when the processor executes the computer program, the following steps are also implemented:
step S10, reading M n A target verification identification bit corresponding to the target address in the computer system, and if the target verification identification bit is a second identification bit, reading C corresponding to the target address n The bit is written to the data in the data storage bit as the first data to be tested.
Step S20, reading M n G corresponding to the target address n The bit ECC check code stores the ECC check code of the bit and corresponds to the G of the target address n And decoding the ECC check code of the bit ECC check code storage bit to generate second data to be detected.
And step S30, if the first data to be tested is matched with the second data to be tested, determining the data to be tested as target data corresponding to a target address, otherwise, generating ECC error reporting prompt information.
It can be understood that if the target check flag is the second flag, it indicates that the pen data has a corresponding ECC protection, and thus ECC check is required.
According toIt can be seen that M can be used to avoid memory waste n Is set equal toM n The corresponding memory bit width may be an integer power other than 2, and when M n With the corresponding target frequency requirement, it is highly likely that the target frequency and target size requirements cannot be met directly with a single block of memory. In the prior art, two independent memories may be directly adopted, one is used for storing data to be written, and the other is used for storing an ECC check code, so that the chip area is definitely increased, and the chip performance is reduced. Based on this, M can be generated using a plurality of small-sized memory combinations n As an example, M n From one or more dimensions smaller than M n And the frequency is greater than or equal to M n Is generated in combination with a memory of the target frequency of (a). Multiple dimensions smaller than M n And the frequency is greater than or equal to M n The memory of the target frequency of (a) is the same memory or belongs to two different memories. Multiple dimensions smaller than M n And the frequency is greater than or equal to M n The target frequency of the memory combination of (a) is X rows and Y columns of memory, each row comprises at least one memory, and the memories of each column are the same. X is an integer power of 2, and the system adopts a mode of chip selection logic to M n Data is stored therein. The specific combination strategy of the memory will be described in detail in the second embodiment, and will not be described here again.
The first embodiment of the system can flexibly set the number of bits of the writing mask and the number of bits of the ECC, and has the flexibility of setting the number of bits of the ECC and the area of a chip, so that the flexibility of data verification is improved, the waste of the area of the chip is reduced, and the performance of the chip is improved.
It should be noted that, in addition to the case where the ECC operation and the writemask operation are performed simultaneously as described in the first embodiment, the memory needs to be generated in combination, and in the case where the size requirement and the frequency requirement cannot be met by the whole memory, the second embodiment is further proposed by the present invention.
Example two
A second embodiment provides a system for generating a target combined memory, comprising a pre-generated memory database, a memory storing a computer program, and a processor, the memory database for storing a plurality of memory records, the memory records comprising memory identification, memory size, memory frequency, memory area, memory dynamic power consumption, and memory static power consumption. The memory in the memory database may be specifically a Static Random Access Memory (SRAM) or a Latch Array (Latch Array), etc.
As shown in fig. 2, when the processor executes the computer program, the following steps are implemented:
and C1, traversing the memory database, determining a memory with a memory size smaller than a target size and a memory frequency larger than the target frequency as a candidate memory, and generating a candidate memory set.
It can be understood that in step C1, all memories in the memory database, which meet the memory size smaller than the target size and the memory frequency greater than the target frequency, are extracted to generate a candidate memory set.
And C2, traversing the candidate memory set, selecting one or two candidate memories from the candidate memory set as a combination unit, combining to generate a candidate combination memory, and generating a candidate combination memory set, wherein the difference value of the size of the candidate combination memory minus the target size is P, and P is more than or equal to 0.
It is to be understood that, in the case of performing memory combination, the limitation is not limited to the size, and parameters such as the physical aspect ratio, which need to be focused, may be set to generate a combination that meets the limitation.
It should be noted that, in some cases, only one candidate memory is selected as a combining unit to meet the combination requirement, and the combination complexity is low. However, in some cases, only one candidate memory is selected as a combination unit, which cannot meet the combination requirement and may cause excessive area waste, and two candidate memories are selected as combination units, which is more flexible, can meet the combination requirement and avoid excessive area waste. When more than two combination units are selected, the flexibility is better, but the combination complexity is greatly improved, so the invention sets one or two candidate memories to be selected as the combination units. In step C2, all the combination units meeting the requirements need to be traversed.
And step C3, based on the corresponding memory records of the selected combination units in the memory database, acquiring the combination area and the combination power consumption of each candidate combination memory.
And C4, acquiring a comprehensive performance value corresponding to each candidate combined memory based on the combined area and the combined power consumption of each candidate combined memory and the preset area weight and power consumption weight.
It should be noted that, the preset area weight and the power consumption weight are set according to the specific application requirement.
And C5, determining the candidate combined memory with the minimum comprehensive performance value in the candidate combined memory set as a target combined memory.
As an embodiment, the step C1 further includes:
and step C10, acquiring all memory size information corresponding to the memory information generating software.
The memory information generating software is conventional software, and can generate detailed memory information by inputting memory size information, and specifically includes a memory frequency, a memory area, a GDS file, and the like. The GDS file is a file format for a circuit layout. The memory information generating software needs several minutes or even twenty minutes to generate the memory information based on one memory size information, and the speed is very slow, so that the memory information corresponding to all the memory size information is extracted in advance to generate the memory database, the memory information can be quickly acquired in the process of combining the memories, and the efficiency of generating the target combined memory is improved.
And step C20, inputting each memory size information into the memory information generating software to obtain the corresponding memory frequency and memory area.
And step C30, setting corresponding memory identifications for each group of memory frequency and memory area, acquiring corresponding dynamic power consumption and static power consumption, generating a memory record and generating the memory database. By generating the memory database in advance, the parameter information of the memory can be obtained from the memory database quickly later, so that the efficiency of generating the target combined memory is improved.
It should be noted that the memories of the same size may generate memories of various configurations, and thus, each set of the memory frequencies and the memory areas is set with a corresponding memory identifier. The memory information generating software cannot directly generate the static power consumption and the dynamic power consumption corresponding to the memory, and the static power consumption and the dynamic power consumption of the existing memory need to be calculated, and all the existing ways of calculating the static power consumption and the dynamic power consumption of the memory fall into the protection scope of the invention, and are not repeated herein.
The size of the memory is not an integer power of 2, when there is a number of memory address lines or a width of the memory bits is not an integer power of 2, the area is not necessarily smaller than the number of memory address lines and the width of the memory bits is not an integer power of 2, for example, the area of the memory of 1024×31 may be larger than the area of 1024×32, and the performance of 1024×32 is better than 1024×31, so 1024×32 may be also included in the candidate memory set, and as an embodiment, the step C1 further includes:
step C01, obtaining a preset memory size e×f, where E represents a preset memory address line number, and F represents a preset memory bit width.
Step C02, if E is equal to the integer power of 2, setting u=e, and if E is not equal to the integer power of 2, setting the value of U to be greater than E and the integer power of 2 with the smallest difference with E; if F is equal to an integer power of 2, v=e is set, and if F is not equal to an integer power of 2, the value of V is set to an integer power of 2 that is greater than F and has the smallest difference from F.
And C03, determining U.V as the target size.
Based on the value U.V of the target size adjusted by the preset size of the memory, a more reasonable candidate memory set can be obtained, and the performance of the target combined memory is improved.
As an example, the step C2 includes:
and C21, traversing the candidate memory set, selecting one or two candidate memories from the candidate memory set as combination units, combining to generate a candidate combination memory, wherein the combination memory is a memory array of L rows and K columns, each row of the memory array comprises at least one combination unit, the combination units of each column of the memory array are identical, L is an integer power of 2, and storing data into the candidate memories in a chip selection logic mode.
If L is not an integer power of 2, full address decoding is required, so that the area of the chip is greatly increased and the speed of the chip is affected, and if L is set to be an integer power of 2, data can be stored in the candidate memory by adopting a chip selection logic mode, so that the area of the chip is greatly reduced. The existing ways of implementing the chip selection logic fall within the protection scope of the present invention, and are not described herein.
As an example, the step C3 includes:
and step C31, based on the corresponding memory records of the selected combined units in the memory database, acquiring the memory area of each combined unit in the candidate combined memory.
It will be appreciated that since the memory database is pre-configured, the memory area of each unit of combination in the candidate combination memory can be quickly obtained.
And step C32, acquiring the total area of the combined units based on the area of each combined unit in the candidate combined memory and the corresponding number.
And step C33, acquiring the corresponding chip selection combination logic circuit area based on the chip selection logic corresponding to the candidate combination memory, wherein the chip selection combination logic circuit area and the chip selection number are positively correlated.
It will be appreciated that the number of chip choices is positively correlated with L.
And step C34, determining the sum of the total combined unit area corresponding to the candidate combined memory and the corresponding chip selection combined logic circuit area as the combined area of the candidate combined memory.
As an example, the step C3 includes:
and step C301, based on the corresponding memory records of the selected combined units in the memory database, acquiring the corresponding static power consumption and dynamic power consumption of each combined unit in the candidate combined memory.
It can be appreciated that, since the memory database is preset, the static power consumption and the dynamic power consumption corresponding to each combination unit in the candidate combination memory can be quickly obtained.
And step C302, obtaining a sum a of static power consumption and a sum b of dynamic power consumption corresponding to each row based on the number of combined units in each row in the candidate combined memory and the corresponding static power consumption and dynamic power consumption.
Step C303, obtaining corresponding combined power consumption W based on a sum a of static power consumption and a sum b of dynamic power consumption corresponding to each row in the candidate combined memory:
W＝b+L*a。
although the larger the number of rows, the larger the area is, only one row is running at a time, and the other rows have only static power consumption, which reduces the overall power consumption. Therefore, the candidate combination memory with the highest comprehensive performance is finally selected as the target candidate combination memory based on the comprehensive consideration of the power consumption and the area of each candidate combination memory.
As an example, the memory record further comprises RTL code of the memory, and the step C5 further comprises:
and step C6, automatically generating the RTL code of the target combined memory based on the RTL code of the memory of the combined unit corresponding to the target combined memory, the combination logic and the chip selection logic among the combined units in the target combined memory.
And automatically generating the RTL code of the target combined memory through the RTL code of the memory of the combined unit corresponding to the target combined memory, the combination logic and the chip selection logic among the combined units in the target combined memory, and presenting the RTL code as an integral memory.
As an example, the step C5 further includes:
and step C7, inputting the parameter information corresponding to the target combined memory into memory information generating software to generate a corresponding GDS file.
It should be noted that, when the RTL code and the GDS file of the target combined memory are obtained, the subsequent chip production operation can be performed.
It should be noted that, the target combined memory generated in the second embodiment may adopt the scheme described in the first embodiment to implement data verification with a write mask, and details of implementation are described in the first embodiment and are not described herein.
According to the system, the target combination memory which accords with the target size and the target frequency is generated by quickly selecting the small-size memory combination based on the memory database which is generated in advance, so that the chip area is reduced, the chip power consumption is reduced, and the chip performance is improved.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (8)
1. A data verification system with a writemask, wherein,
comprising a chip arranged in a preset chipN chip internal memories { M 1 ,M 2 ,…,M n ,…M N Memory and processor storing computer program, where M n N is a value range of 1 to N for an N-th internal memory in a preset chip; m is M n The corresponding ECC bit number is A n The number of bits of the ECC check code is G n ，M n The corresponding write mask bit number is B n ，M n The corresponding data writing bit width is C n ，M n The corresponding memory bit width is D n ，C n ≥A n ，C n ≥B n ，M n Comprises a check identification bit G n Bit ECC check code stores bits and C n Writing bits into the data storage bits; when the processor executes the computer program, the following steps are implemented:
step S1, obtaining M n The data information to be written comprises data to be written, write mask information to be processed and address information to be written;
step S2, if the information of the to-be-processed writing mask is empty, executing step S3, otherwise, judging A n Whether or not to be equal to B n If so, executing step S3, if not, setting the check identification bit corresponding to the address information to be written as a first identification bit, and storing the data to be written into C corresponding to the address information to be written n Writing the bits into the data storage bits, wherein if the check identification bits are the first identification bits, ECC check operation is not performed when the data of the corresponding written data storage bits are read;
step S3, M is taken as n Setting a check identification bit corresponding to address information to be written into as a second identification bit, performing ECC processing on data to be written into to generate an ECC check code, and storing the ECC check code into G corresponding to the address information to be written into n Bit ECC check code stores bits, and stores the data to be written into C corresponding to the address information to be written n Writing the data storage bit into the bit, wherein if the check identification bit is the second identification bit, thenAnd when the data of the corresponding written data storage bit is read, performing ECC check operation.
2. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
in the step S1, by connecting to M n The first connection line of (2) acquires the data to be written by being connected to M n The second connection line of the memory card obtains the information of the write mask to be processed by being connected to M n And acquiring the address information to be written in by the third connecting line.
3. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
when the processor executes the computer program, the following steps are also implemented:
step S100, reading M n Target verification identification bit corresponding to the target address in the computer system, if the target verification identification bit is the first identification bit, directly reading C corresponding to the target address n The data in the bit write data storage bits is used as target data corresponding to the target address.
4. A system according to claim 1 or 3, wherein,
when the processor executes the computer program, the following steps are also implemented:
step S10, reading M n A target verification identification bit corresponding to the target address in the computer system, and if the target verification identification bit is a second identification bit, reading C corresponding to the target address n Writing data in the data storage bit as first to-be-tested data;
step S20, reading M n G corresponding to the target address n The bit ECC check code stores the ECC check code of the bit and G corresponding to the target address n The bit ECC check code stores the ECC check code of the bit as second data to be tested;
and step S30, if the first data to be tested is matched with the second data to be tested, determining the data to be tested as target data corresponding to a target address, otherwise, generating ECC error reporting prompt information.
5. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
M n is a static random access memory or latch array.
6. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
M n from one or more dimensions smaller than M n And the frequency is greater than or equal to M n Is generated by a memory combination of target frequencies of a plurality of sizes smaller than M n And the frequency is greater than or equal to M n The memory of the target frequency of (a) is the same memory or belongs to two different memories.
7. The system of claim 6, wherein the system further comprises a controller configured to control the controller,
multiple dimensions smaller than M n And the frequency is greater than or equal to M n The target frequency of the memory combination of (a) is X rows and Y columns of memory, each row comprises at least one memory, and the memories of each column are the same.
8. The system of claim 7, wherein the system further comprises a controller configured to control the controller,
x is an integer power of 2, and the system adopts a mode of chip selection logic to M n Data is stored therein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311031939.XA CN116959540B (en) | 2023-08-16 | 2023-08-16 | Data verification system with writemask |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311031939.XA CN116959540B (en) | 2023-08-16 | 2023-08-16 | Data verification system with writemask |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116959540A true CN116959540A (en) | 2023-10-27 |
| CN116959540B CN116959540B (en) | 2024-03-01 |
Family
ID=88446309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311031939.XA Active CN116959540B (en) | 2023-08-16 | 2023-08-16 | Data verification system with writemask |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116959540B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117311988A (en) * | 2023-11-27 | 2023-12-29 | 沐曦集成电路(南京)有限公司 | Protocol operation optimization method, device and equipment with mask and medium |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58199498A (en) * | 1982-05-18 | 1983-11-19 | Toshiba Corp | Memory system |
| EP0653707A2 (en) * | 1993-11-17 | 1995-05-17 | International Business Machines Corporation | Error handling in memory subsystem |
| US20110320918A1 (en) * | 2010-06-24 | 2011-12-29 | International Business Machines Corporation | Error correction and detection in a redundant memory system |
| CN102903394A (en) * | 2011-07-26 | 2013-01-30 | 爱思开海力士有限公司 | Semiconductor memory apparatus and semiconductor system having the same |
| CN105335247A (en) * | 2015-09-24 | 2016-02-17 | 中国航天科技集团公司第九研究院第七七一研究所 | Fault-tolerant structure and fault-tolerant method for Cache in high-reliability system chip |
| US9823966B1 (en) * | 2013-11-11 | 2017-11-21 | Rambus Inc. | Memory component with error-detect-correct code interface |
| CN107436821A (en) * | 2016-05-31 | 2017-12-05 | Arm 有限公司 | It is the apparatus and method for the block generation error code for including multiple data bit and address bit |
| US10275306B1 (en) * | 2017-02-09 | 2019-04-30 | Cadence Design Systems, Inc. | System and method for memory control having adaptively split addressing of error-protected data words in memory transactions for inline storage configurations |
| CN115981913A (en) * | 2022-12-26 | 2023-04-18 | 芯弦半导体(苏州)有限公司 | ECC (error correction code) checking method and device based on SRAM (static random Access memory) |
-
2023
- 2023-08-16 CN CN202311031939.XA patent/CN116959540B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58199498A (en) * | 1982-05-18 | 1983-11-19 | Toshiba Corp | Memory system |
| EP0653707A2 (en) * | 1993-11-17 | 1995-05-17 | International Business Machines Corporation | Error handling in memory subsystem |
| US20110320918A1 (en) * | 2010-06-24 | 2011-12-29 | International Business Machines Corporation | Error correction and detection in a redundant memory system |
| CN102903394A (en) * | 2011-07-26 | 2013-01-30 | 爱思开海力士有限公司 | Semiconductor memory apparatus and semiconductor system having the same |
| US9823966B1 (en) * | 2013-11-11 | 2017-11-21 | Rambus Inc. | Memory component with error-detect-correct code interface |
| CN105335247A (en) * | 2015-09-24 | 2016-02-17 | 中国航天科技集团公司第九研究院第七七一研究所 | Fault-tolerant structure and fault-tolerant method for Cache in high-reliability system chip |
| CN107436821A (en) * | 2016-05-31 | 2017-12-05 | Arm 有限公司 | It is the apparatus and method for the block generation error code for including multiple data bit and address bit |
| US10275306B1 (en) * | 2017-02-09 | 2019-04-30 | Cadence Design Systems, Inc. | System and method for memory control having adaptively split addressing of error-protected data words in memory transactions for inline storage configurations |
| CN115981913A (en) * | 2022-12-26 | 2023-04-18 | 芯弦半导体(苏州)有限公司 | ECC (error correction code) checking method and device based on SRAM (static random Access memory) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117311988A (en) * | 2023-11-27 | 2023-12-29 | 沐曦集成电路(南京)有限公司 | Protocol operation optimization method, device and equipment with mask and medium |
| CN117311988B (en) * | 2023-11-27 | 2024-03-12 | 沐曦集成电路(南京)有限公司 | Protocol operation optimization method, device and equipment with mask and medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116959540B (en) | 2024-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106409344B (en) | Data storage device and operation method thereof | |
| US20150339073A1 (en) | Selection of redundant storage configuration based on available memory space | |
| US20070214403A1 (en) | Method and apparatus for error detection and correction | |
| CN101916173B (en) | RAID (Redundant Array of Independent Disks) based data reading and writing method and system thereof | |
| CN116959540B (en) | Data verification system with writemask | |
| US20120144272A1 (en) | Probabilistic multi-tier error correction in not-and (nand) flash memory | |
| US20080148130A1 (en) | Method and apparatus of cache assisted error detection and correction in memory | |
| US20090150747A1 (en) | Correction of errors in a memory array | |
| US20130166991A1 (en) | Non-Volatile Semiconductor Memory Device Using Mats with Error Detection and Correction and Methods of Managing the Same | |
| CN103631670A (en) | Storage device of storage, storage controller and data processing method | |
| US7401269B2 (en) | Systems and methods for scripting data errors to facilitate verification of error detection or correction code functionality | |
| CN111078462B (en) | Data verification method and circuit | |
| JP2008192240A (en) | Semiconductor memory and semiconductor memory system | |
| CN104658609A (en) | Error-correcting code distribution method and system for memory system | |
| CN116974813B (en) | Register data management method and device, register module and computer equipment | |
| US9959166B2 (en) | Error correction for non-volatile memory | |
| Lv et al. | Efficient repair analysis algorithm exploration for memory with redundancy and in-memory ECC | |
| CN116741255B (en) | System for generating target combined memory | |
| US11836044B2 (en) | Error coalescing | |
| CN105027084A (en) | Apparatus and method for controlling memory in mobile communication system | |
| CN115827308A (en) | Solid state disk data error correction method and solid state disk | |
| CN113241112A (en) | Bad block screening method and device, computer readable storage medium and electronic equipment | |
| US9104596B2 (en) | Memory system | |
| US20060117134A1 (en) | System and method for prolonging usage lifetime of a non-volatile memory | |
| US11874734B2 (en) | Memory and operation method of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |