JP2008192240A - Semiconductor memory and semiconductor memory system - Google Patents

Semiconductor memory and semiconductor memory system Download PDF

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JP2008192240A
JP2008192240A JP2007025864A JP2007025864A JP2008192240A JP 2008192240 A JP2008192240 A JP 2008192240A JP 2007025864 A JP2007025864 A JP 2007025864A JP 2007025864 A JP2007025864 A JP 2007025864A JP 2008192240 A JP2008192240 A JP 2008192240A
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block
defective
number
data
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Tomoji Takada
知二 高田
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Toshiba Corp
株式会社東芝
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Abstract

A semiconductor memory and a semiconductor memory system capable of further improving the yield are provided.
A semiconductor memory has a plurality of blocks, each block is composed of a plurality of pages, and each page has a plurality of memory cells. A block in which all pages in the block have no more than N bad bits (N is an integer of 0 or more) stores the first data indicating a normal block and has more bad bits than N places. A block that includes at least one page and does not have any page having M or more defective bits (M is an integer of M> N) has second data indicating a pseudo-pass block as a pseudo-normal block. A block that stores and includes at least one page that includes M or more defective bits stores the third data as a defective block.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile memory such as a NAND flash memory, and more particularly to a semiconductor memory and a semiconductor memory system capable of relieving a defective bit before and after shipment.

  In recent years, the bit capacity of a nonvolatile memory has been rapidly increasing with the progress of semiconductor miniaturization technology. For this reason, in the memory chip selection test method based on the premise that all the bits of the memory are non-defective products at the time of manufacture, defective products frequently occur and it is difficult to ensure a sufficient yield. Therefore, various techniques for relieving defective bits that enable a memory chip having some defective bits to be used as non-defective chips have been put to practical use as follows.

(1) Redundancy technology for relieving defective bits in a memory chip As this redundancy technology, there are a column redundancy technology for replacing a defective column with a non-defective column and a block redundancy technology for replacing a defective block with a non-defective block. Hereinafter, the simultaneously erasable area is called an erase block, and this erase block unit is simply called a block. One block includes a plurality of pages as write / read units, and each page is constituted by a plurality of memory cells.

(2) Defective bit remedy technology executed by the controller mounted in the non-volatile memory As this defective bit remedy technology, error correction technology using ECC (Error Check and Correction) circuit, or defective column is skipped and replaced with normal column There are a bad column skip technique to perform the defective block replacement technique and a defective block replacement technique to substitute a defective block with a normal block.

(3) Memory chip test technology As a test technology, there is a pseudo-pass technology for ignoring even a small number of defective bits in a page and making a pseudo-normal page on the premise of correction by an ECC circuit. Yes (see, for example, Patent Document 1).

  Among the above-described technologies, the ECC technology is particularly powerful as a defective bit repair technology, and has a feature that a flexible ECC circuit can be designed according to the required error correction strength if an increase in circuit scale is allowed. .

  The pseudo-pass technique is based on the premise of correcting defective bits by the ECC technique, thereby realizing a significant improvement in memory yield. The correction unit (referred to as ECC unit) by the ECC circuit is, for example, 512 bytes. By assuming the ECC technology of 4 bits / 512 bytes that can correct 4 or less defective bits in this ECC unit, 1 A two-bit pseudo-pass technique for making a normal page even if there are two defects per page (2 kbytes = 2048 bytes) has been put into practical use.

  In recent years, the nonvolatile memory mounted on a memory card or the like has been rapidly increasing in the number of bits that can be written / read at a time = page size in order to meet the demand for higher speed. Conventionally, NAND flash memory of 130 nm or earlier used 512 bytes (small block) for one page, but after 90 nm, one page is 2 kbytes (large block), and will be 4 kbytes and 8 kbytes in the future. There is a tendency to increase. For this reason, in the ECC circuit, the number of bits corrected at one time tends to increase. However, the ECC circuit has a problem that the circuit scale rapidly increases as the ECC unit increases. Therefore, in the 70 nm NAND flash memory, one page (2 kbytes) is divided into four 512-byte portions, and ECC correction is performed in four steps. Such a deviation between the page size and the ECC unit tends to become larger in the future.

  For example, when the number of defective locations (defective bits) that can be corrected by the ECC circuit is X locations, the defective location ignored by the pseudo-pass technique is Y location, and correction is performed by dividing one page into Z ECC units, Even if M defects are concentrated in one ECC unit, the ECC correction capability cannot be exceeded, so the relationship of equation (1) is established.

X ≧ M (1)
Here, α = X−M. α is the number of allowable defective bits that are generated later, and is the allowable number of defective bits that are generated later after the screening test that is performed before the shipment of the nonvolatile memory. In the case of α = 0, if a late bit failure occurs even at one location, the ECC correction capability will be exceeded, and the memory system will be in a dangerous state. For this reason, in consideration of the use of the memory system and the strength of data retention of the semiconductor memory, for example, deterioration of the memory cell due to repeated writing and erasing of the memory cell, α = 0 is not normally set. Therefore, as shown in the equation (2), the defective portion Y to be ignored by the pseudo-pass technique is set so that the number of allowable defective bits α is 1 or more.

Y = X−α, α ≧ 1 (2)
In the example of the 70 nm multi-level cell NAND flash memory described above, Z = 4 (page size 2 kB / ECC unit 512 bytes), Y = 2 (2-bit pseudo-pass), X = 4 (4 bits / 512 bytes relief), α = 2 has been put into practical use.

As described above, the page size and the ECC unit tend to become larger in the future. When the difference between the page size and the ECC unit becomes large, the following problem occurs. That is, the upper limit of the number of allowable defective bits in the pseudo-pass technique is defined by the equation (2), but as the difference between the page size and the ECC unit increases, that is, as the number Z of ECC units increases, 1 The probability that all M defects are concentrated in one ECC unit in the page is drastically reduced. That is, the upper limit of the expression (2) is the upper limit of M places where correction by the ECC circuit is guaranteed even in the worst case where the occurrence probability is very small. Actually, in most cases, defects at M locations are appropriately scattered within Z ECC units, so even with M locations exceeding Equation (2), an ECC circuit that corrects X locations can be corrected sufficiently. Is possible. Therefore, in the conventional pseudo-pass technique, the relationship between the setting of the M location and the ECC correction capability X means that a nonvolatile memory chip that can still be used as a non-defective product is determined as a defective product. For this reason, further yield improvement is desired.
JP 2002-140899 A

  The present invention is intended to provide a semiconductor memory and a semiconductor memory system capable of further improving the yield.

  A semiconductor memory according to a first aspect of the present invention includes a plurality of blocks, each block is configured by a plurality of pages, and each page is a semiconductor memory having a plurality of memory cells, all of the blocks in the block The block having no more than N bad bits (N is an integer greater than or equal to 0) stores first data indicating a normal block, and at least one page having more bad bits than N places is stored. A block having no defective page at least M locations (M is an integer of M> N) stores second data indicating a pseudo-pass block as a pseudo-normal block, and M A block including at least one page including defective bits at more than one location stores the third data as a defective block.

  A semiconductor memory system according to a second aspect of the present invention is a semiconductor memory system including the semiconductor memory according to the first embodiment and a controller having an error correction function, and the controller stores the first data. The block in which the third data is stored is not used as a defective block. The block in which the second data is stored is used for each error correction unit of each page. If the number of bad bits detected for each error correction unit is larger than the number that can be corrected, the bad bits in all error correction units are not recognized and used as a bad block. If the number is less than the number that can be corrected, it is used as an available block.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor memory and semiconductor memory system which can improve a yield further can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  The following embodiments will be described using a NAND flash memory. However, the present embodiment is not limited to the NAND flash memory, and the present embodiment can be applied to other nonvolatile memories.

  FIG. 2 shows an example of a storage device to which the present embodiment is applied, for example, a memory card.

In FIG. 2, a host device (hereinafter referred to as a host) 10 includes hardware and software (system) for accessing a connected memory card. The host 10 accesses the memory card 1 such as data read, data write, and data erase.

  When the memory card 1 is connected to the host 10, the memory card 1 operates by being supplied with power, and performs processing according to access from the host 10. For example, in accesses such as data read, data write, and data erase, processing such as mapping of physical addresses and logical addresses, ECC error correction, and access to the NAND flash memory is performed.

As described above, the memory card 1 includes the NAND flash memory 2 and the controller 3.

  The controller 3 includes a memory interface unit 4, a host interface unit 5, a buffer 6, a CPU 7, a ROM (Read Only Memory) 8, a RAM (Random Access Memory) 9, and an error correction circuit (ECC circuit) 11.

  The memory interface unit 4 performs interface processing between the controller 3 and the NAND flash memory 2. The host interface unit 5 performs interface processing between the controller 3 and the host 10.

  The buffer 6 temporarily stores a certain amount (for example, one page) of data when data sent from the host 10 is written to the NAND flash memory 2, or data read from the NAND flash memory 2. When a message is sent to the host 10, a certain amount of data is temporarily stored. The ECC circuit 11 corrects an error in data read from the NAND flash memory 2. For example, a Reed-Solomon method or a BCH (Bose-Chaudhuri-Hocquenghem) method is applied as an error correction method, but other methods can also be applied.

  The CPU 7 controls the operation of the entire memory card 1. For example, when power is supplied to the memory card 1, the CPU 7 starts processing according to firmware (control program) stored in the ROM 8. That is, the CPU 7 creates various tables (management data) necessary for processing on the RAM 9 and accesses the corresponding area on the NAND flash memory 2 in response to a write command, a read command, and an erase command from the host 10. When the NAND flash memory 2 is accessed, the logical address and physical address from the host are converted, and the data transfer process is controlled through the buffer 6.

  The ROM 8 is a memory that stores a control program used by the CPU 7. The RAM 9 is a volatile memory that is used as a work area for the CPU 7 and stores various tables and the like.

  The example shown in FIG. 2 is a case of a 2 Gbyte (= 16 Gbit) NAND flash memory having a page size of, for example, 4 kbytes / page and 124 pages = 4 kblocks of 512 kbytes in size. It is assumed that the ECC circuit 11 can correct four locations per 512 bytes.

  The present embodiment realizes a system in which the relief of the NAND flash memory is made maximally efficient by dividing into the following two steps.

  The first step is a NAND flash memory selection test. This selection test is performed, for example, at the time of manufacturing the NAND flash memory 2 shown in FIG.

  The second step is a test performed in a state in which the NAND flash memory 2 selected in the first step is assembled as a memory card including a controller, for example, as shown in FIG. The test in the second step may be performed before shipment of the product or after shipment. Further, the test in the second step may be executed as part of a normal operation after power-on such as an initialization operation of the memory card system.

(First step)
FIG. 3 shows the configuration of the screening test as the first step. This selection test is performed using the memory tester 21. That is, the memory tester 21 is connected to the NAND flash memory 2 and the test data is written and written to all pages constituting each block of the NAND flash memory 2 in which an N-bit error per page is allowed by the pseudo-pass technique. Check later state. According to this check result, it is divided into three categories: normal blocks (hereinafter referred to as pass blocks), defective blocks, and pseudo-pass B blocks. Here, the pseudo-pass B block is a block determined by the pseudo-pass technique that is likely to be usable on the premise of correction by ECC from a block set as a defective block. The definition of each category is as follows.

(1) A block that does not include any defects in all pages in the block (complete pass block) and a block that has no more than N defective bits (pseudo pass block) are pass blocks.

(2) A block that includes at least one page having more than N defects and does not have any page having M or more defective bits (M is an integer of M> N) is pseudo-normal. The block is a pseudo path B block.

(3) A block including at least one page having M or more defective bits is defined as a defective block.

  Each block divided into such categories is marked according to the category.

  FIG. 4 shows an example of marking. For example, a defective mark storage area 31 is provided on the first page of each block. For example, “FF” (hexadecimal) is stored in the defective mark storage area 31 of the pass block, and “00”, for example, is stored in the defective mark storage area 31 of the defective block, and the defective mark storage of the pseudo-pass B block. For example, “0F” is stored in the area 31.

  FIG. 1 shows the operation of the memory tester 21 and shows a flowchart of the selection test. The screening test will be described with reference to FIG.

  The example shown in FIG. 1 is a case of a 2 Gbyte (= 16 Gbit) NAND flash memory in which the size of one page is, for example, 4 kbytes and 124 pages = 4 kblocks having a size of 512 kbytes. The ECC circuit 11 can correct four locations per 512 bytes. In addition, the number of allowable defective bits is 2 as the specified value of the pseudo path, the number of allowable defective bits M and N as the specified value of the pseudo path B is M = 6 and N = 3, respectively, This is a case where α is set to α = 1.

  First, the block address B is initialized to “0” (S1). Thereafter, the page address P is initialized to “0”, and data “FF” indicating the pass block is written in the defective mark storage area 31 of the block address “0” and the page address “0” (S2). Next, the test of the block address “0” and the page address “0” is executed (S3). In this test, for example, test data is written to a block address “0” and a page address “0”, and the written data is verified. As a result of the verification, it is determined whether or not the number of defective bits in the page is 6 or more (S4). As a result, when the number of defective bits in the page is 6 or more, the data in the defective mark storage area 31 is rewritten with data “00” indicating a defective block.

  On the other hand, if the number of defective bits in the page is less than 6 in step S4, it is determined whether or not the number of defective bits in the page is 4 or more (S6). As a result, when the number of defective bits is 4 or more, the data in the defective mark storage area 31 is rewritten to data “0F” indicating the pseudo pass B block (S7). If the number of defective bits in the page is 3 or less, the page is normal and the data in the defective mark storage area 31 remains “FF” indicating the pass block and cannot be rewritten. Thereafter, it is determined whether or not the page address P is the last page (S8). As a result, if it is not the last page, the page address P is incremented (S9), the process proceeds to step S3, and the test for the next page is executed in the same manner as described above.

  If it is the last page, and if the defective block is detected and “00” indicating the defective block is written in the defective mark storage area 31, it is determined whether it is the final block (S6). As a result, if it is not the last block, the block address B is incremented (S7), and the process proceeds to step S2. The same processing as described above is executed for the next block.

  With the above operation, as shown in FIG. 4, a mark indicating the state of the block is stored in the defective mark storage area 31 of each block.

  FIG. 5 shows a specific example of step S3 of FIG. This modification is applied to a NAND flash memory having a function of outputting the number of write errors.

  In FIG. 5, first, write data as test data is received, and this write data is held in, for example, a latch circuit (S3-1). Next, the held write data is written to the designated page of the designated block (S3-2). Thereafter, the written data is read (S3-3) and compared with the write data held in the latch circuit (S3-4). As a result of this comparison, read data different from the write data, that is, the number of error data is obtained and output (S3-5). Based on the number of output error data, the process shown in FIG. 1 is executed.

  FIG. 6 shows a specific example of steps S4 and S6. The NAND flash memory having the pseudo pass function described above can output information indicating whether or not all bits have been written and the number of errors as a result of the verify read. In this example, using the pseudo pass function, data writing and verification are executed in a state where the allowable number of defective bits (also referred to as a specified value) is set in advance, and the writing is completed within the set allowable number of defective bits. Determine if you did. A defective block, a pseudo-pass B block, or a pass block is determined according to the determination result.

  In FIG. 5, first, the number of allowable defective bits recognized as the pseudo path B is set to, for example, “5” (S4-1). Thereafter, the test data is written to the designated page of the designated block (S4-2). The written data is repeatedly verified a specified number of times, for example (S4-3). As a result of this verification, when the number of defective bits exceeds the prescribed value of the pseudo pass B, a mark “00” indicating a defective block is written in the defective mark storage area 31 as a defective block (S5).

  On the other hand, if the result of the verification is within the specified value of the pseudo path B, the number of allowable defective bits recognized as the pseudo path B is set to, for example, “3” (S6-1). Thereafter, the test data is written to the designated page of the designated block (S6-2). The written data is repeatedly verified a specified number of times, for example (S6-3). As a result of this verification, if the number of defective bits exceeds the prescribed value of the pseudo pass B, a mark “0F” indicating a pseudo pass block is written in the defective mark storage area 31 as a pseudo pass (S7). If the number of errors is equal to or less than the specified value of the pseudo path B as a result of the verification, it is determined as a path block.

(Second step)
As described above, the second step is to combine the marked NAND flash memory and the controller having a pseudo-pass function into a memory card system, for example, and then the controller 3 shown in FIG. The whole block of 2 is searched to detect the marking of each block, and the following processing is executed. In the second step, the definitions of the number of defective bits M and N are the same as in the first step.

(1) The pass block is used as it is.

(2) Do not use any bad blocks.

(3) The pseudo pass B block performs the following processing on each page.

  For each of Z (= 8) ECC units included in each page, data is written and read, and the number of defective bits detected for each ECC unit is the number that can be corrected by the ECC circuit- (later allowable defect) If the number of bits is greater than α), the block is recognized as a defective block and is not used thereafter. If the number of defective bits detected for every ECC unit is less than or equal to the number correctable by the ECC circuit, the block is used as an available block.

  As described above, some pages in the pseudo-pass B block include the number of defective bits within a range that can be corrected by the ECC circuit. Therefore, when the number of defective bits increases later, it is difficult to correct by the ECC circuit. It becomes. Even in such a case, the controller can test the state of the pseudo-pass B block and check the state, so that the defective block can be relieved.

  FIG. 7 shows an example of the operation of the controller 3.

  In FIG. 7, first, the allowable number of defective bits in the pseudo path B block is set to N (S11). Next, test data is written to one page of the write target block of the NAND flash memory 2 using the pseudo-pass function (S12). Thereafter, status reading is executed on the NAND flash memory 2 to read the status indicating the quality of writing (S13), and the status is confirmed (S14). That is, when the read status indicates “normal (pass)”, the process proceeds to the next block (S24). When the read status indicates “failure (fail)”, the number of allowable defective bits of the pseudo path B block is set to M (> N) (S15).

  That is, some pages in the pseudo-pass B block include more than N defective bits, so the status may be “bad”. In addition, the number of defective bits may also be greater than N in a block determined as “pass” due to the occurrence of defective bits later. Even in such a case, if error correction is possible, it can be used as a pseudo path B block. For this reason, after setting the number of allowable defective bits of the pseudo-pass B block to M, test data is written again into the NAND flash memory using the pseudo-pass function (S16). Next, status reading is executed on the NAND flash memory 2 to read the status indicating the quality of writing (S17), and the status is confirmed (S18).

  That is, when the read status indicates “defective”, the block to be written is treated as a defective block (S22). If the read status indicates “pass”, data is read from the NAND flash memory 2 (S19), and error correction of the data is executed by the ECC circuit 11 (S20). (S21). As a result, if error correction is possible, the writing target block is handled as a pseudo-pass B block (S23). If error correction is impossible, the writing target block is treated as a defective block (S22). Thereafter, when all the blocks have not been tested, the same operation as described above is performed on the next block (S24).

  According to the above embodiment, in the first step, using the pseudo-pass function, the NAND flash memory block is divided into three categories: a pass block, a defective block, and a pseudo-pass B block. In the second step, NAND-type flash memory including blocks divided into three categories is incorporated in a memory card, for example, the number of defective parts detected per ECC unit for the pseudo-pass B block in the second step is ECC corrected. When it is larger than the possible number-(number of defective bits α), it is not used as a defective block, and when it is equal to or less than the number that can be corrected by ECC, it is determined as a usable block. For this reason, a block that has been determined to be a bad block by the conventional pseudo-pass technique can be used as a pseudo-pass B block. Therefore, the repair efficiency of defective blocks can be improved and the yield can be improved.

  In addition, even when the number of defective bits increases later, the pseudo-pass B block can be used within a range where error correction is possible. Therefore, a block that could not be used as a defective block in the past can be relieved, and the yield can be improved.

  The effect of the said embodiment is demonstrated concretely. The following description is based on the assumption of a 2 Gbyte (= 16 Gbit) NAND flash memory having a 4 k block with a page size of 4 kbytes / page and 125 pages = 512 kbytes. Further, this NAND flash memory is a case where the number of allowable defective bits of the pseudo-pass function is N = 3, M = 6, and the number of allowable allowable defective bits α = 1 in the first step described above. An ECC circuit capable of correcting 4 bits per 512 B is assumed.

  In this example, if the rate that includes even one bit per 512 bytes (raw error rate) is 1/10, the number of errors that occur in one page (4 Kbytes), the occurrence rate, and the average occurrence The number and the cumulative number of occurrences are as shown in FIG. Here, the value of 1/10 used is normally used as an error rate allowed using an appropriate ECC circuit, assuming an error rate comparable to that of a conventional NAND flash memory. It is a general value.

As shown in FIG. 8, 43.0% of pages with no error at one location (the probability of no error per 512 bytes is 9/10. The probability of no error in 4 Kbytes (512 * 8)) (Occurrence rate) is (9/10) 8 = 0.430) 38.3% of pages with 1 location error, ..., below, 214 pages with 5 location errors, 6 location errors There are 12 pages, and there are few pages that have more errors than can be ignored.

  The number of pages having errors at five or more locations is very small compared to the total number of pages. That is, since it is 0.040%, the probability that there are two or more defective pages having five or more errors in one block is small enough to be ignored. That is, there are 226 (= 214 + 12) blocks including at least one page having errors at five or more locations, and only 12 blocks including pages having errors at six or more locations.

There are 214 blocks that contain a page with a 5-point error. Among them, the probability that all five errors are concentrated in one ECC unit (512B) is
8 C 1 * (1/8) 5 = 1/4096
It is. Therefore, the average number of blocks in which five errors out of 214 blocks are all concentrated in one ECC unit is only 0.052.

In addition, the probability that four errors are concentrated in one ECC unit (512B) is
8 C 1 * (1/8) 4 * 7 C 1 * (1/8) = 7/4096
There is an average of 0.37 out of 214 blocks.

  Accordingly, there are an average of 0.42 blocks out of 214 blocks in which errors at four or more locations are concentrated in one ECC unit (512B).

  In the second step, the true number of defective blocks obtained from the repair algorithm by the controller 3 can be counted as the sum of the following two types of defective blocks (1) and (2).

(1) A block having a page (4 KB) including errors at six or more locations. There are 12 on average.

(2) A block having pages including errors at five locations and having pages where four or more of the five locations are concentrated in one ECC unit (512B). This is an average of 1 or less (0.42).

  The meaning of (2) above is that 213 blocks out of blocks with 5 error-containing pages have only 3 or less error locations concentrated in one ECC unit, and these should be used in relief. Means you can.

  In this way, 213 out of 226 (= 214 + 12) blocks including pages having defects at five or more locations, which were conventionally regarded as non-use as defects, can be used as blocks that can be relieved by ECC. That is, 94.2% of the blocks that have been regarded as defective so far can be used, and the yield of the NAND flash memory can be greatly improved.

  If the controller 3 cannot handle the pseudo path B block, the pseudo path B block is identified as a bad block and is not used. For this reason, the NAND flash memory having the pseudo path B block can also be applied to the controller 3 that cannot handle the pseudo path B block.

  FIG. 9 is a first modification showing the operation of the controller 3.

  In FIG. 9, first, the allowable number of defective bits in the pseudo path B is set to M (S31). Next, test data is written into the NAND flash memory using the pseudo-pass function (S32). Thereafter, status reading is performed on the NAND flash memory (S33), and the status is confirmed (S34). As a result, when the read status indicates “pass”, the process proceeds to the next block (S36). If the read status indicates “defective”, the block to be written is handled as a defective block (S35). Thereafter, the process proceeds to the next block (S36).

  Also according to the first modification shown in FIG. 9, the same effect as that of the above embodiment can be obtained.

  FIG. 10 is a second modification showing the operation of the controller 3.

  In FIG. 10, first, it is determined whether the write target block is a pass block or a pseudo-pass B block (S41, S42). As a result, if it is a pass block, the number of allowable defective bits of the pseudo path function is set to N (S43), and if it is a pseudo path B block, the allowable number of defective bits of the pseudo path function is set to M ( S44). Thereafter, data is written into one page of the write target block of the NAND flash memory 2 using the pseudo-pass function (S45). Next, status reading is executed on the NAND flash memory (S46), and the read status is confirmed (S47, S48). As a result, when the block to be written is a pass block and the read status indicates “pass”, the process proceeds to the next block (S49).

  If the read status is a pass block and the read status indicates “fail”, the number of allowable defective bits of the pseudo-pass function is set to M (S50), and the same as in the above-described embodiment. Execute the operation. That is, the test data is written again into the NAND flash memory using the pseudo pass function (S51). Next, status reading is executed on the NAND flash memory 2 to read the status indicating the quality of writing (S52), and the status is confirmed (S53).

  As a result, when the read status indicates “defective”, the block to be written is treated as a defective block (S57). If the read status indicates “pass”, the data is read from the NAND flash memory 2 (S54), and the error correction of the data is executed by the ECC circuit 11 (S55). (S56).

  As a result, if error correction is possible, the writing target block is handled as a pseudo-pass B block thereafter (S57). If error correction is impossible, the write target block is treated as a defective block (S58). After this, if all the blocks have not been tested, the same operation as described above is executed for the next block (S49).

  According to the second modified example, the test block is written by setting the allowable defective bit number N in the pass block and setting the allowable defective bit number M in the pseudo-pass B block. If the status indicates “Bad”, the number of allowable defective bits of the pseudo-pass function is increased to M, data is written, and the status check is performed again. If the status is “Pass”, the error can be corrected by error correction. Judgment whether or not. For this reason, even when errors increase in the path block later, it can be used as a pseudo path B block as long as error correction is possible. Therefore, an increase in defective blocks can be prevented, and the yield of the NAND flash memory can be improved.

  FIG. 11 is a third modification showing the operation of the controller 3.

  A third modification is a case where a NAND flash memory having a function of returning the number of defective bits to the controller 3 together with the status is used.

  In FIG. 11, the controller 3 first writes test data to the NAND flash memory 2 (S61). Thereafter, status reading is executed on the NAND flash memory 2 (S62), and the status is confirmed (S63). That is, according to the number of defective bits indicated in the status, the block to be written is classified into the above three categories (S64). That is, for example, a block in which all pages in the block have N or less defective bits is a pass block. A block that includes at least one page having more than N defects and does not have any page having M or more defective bits (M is an integer of M> N) is a pseudo-pass B block. A block including at least one page having M or more defective bits is defined as a defective block.

  According to the third modified example, even when a defective bit is generated later, by dividing the block into each category according to the number of defective bits, it is possible to suppress the occurrence of a defective block and to use the blocks Can be prevented.

  In the above-described embodiment, the pseudo-pass technique is described as ignoring even a small number of defective bits in a page on the premise of correction by the ECC circuit, and pseudo-normal technique. In a broad sense, for example, even if writing of all bits in a page is not completed, writing is completed if the number of unwritten bits is equal to or less than a predetermined number.

  Moreover, although the said embodiment demonstrated the case where NAND type flash memory was applied to a memory card, it is not limited to this, For example, it is also applicable to electronic devices, such as a USB memory.

  Of course, various modifications can be made without departing from the scope of the present invention.

The flowchart which concerns on embodiment of this invention and shows a selection test. The block diagram which shows an example of the memory card to which this embodiment is applied. The block diagram which shows the outline at the time of a selection test. The figure which shows the example of the marking memorize | stored in each block. The flowchart which shows the one part specific example of FIG. The flowchart which shows the one part specific example of FIG. The flowchart which shows an example of operation | movement of a controller. The figure shown in order to demonstrate the effect of this embodiment. The flowchart which shows operation | movement of a controller and shows the 1st modification. The flowchart which shows operation | movement of a controller and shows the 2nd modification. The flowchart which shows operation | movement of a controller and shows the 3rd modification.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory card, 2 ... NAND type flash memory, 3 ... Controller, 11 ... ECC circuit, 21 ... Memory tester, 31 ... Defect mark storage area.

Claims (5)

  1. A semiconductor memory having a plurality of blocks, each block being composed of a plurality of pages, each page having a plurality of memory cells,
    A block in which all pages in the block have N or less bad bits (N is an integer greater than or equal to 0) stores the first data indicating a normal block and stores more than N bad bits. The second data indicating a pseudo-pass block as a pseudo-normal block is a block that includes at least one page and has no M or more (M is an integer of M> N) defective bits. And a block including at least one page including M or more defective bits stores third data as a defective block.
  2. A semiconductor memory system comprising the semiconductor memory according to claim 1 and a controller having an error correction function,
    The controller uses the block in which the first data is stored as a normal block, identifies the block in which the third data is stored as a bad block, does not use it, and stores the second data If the number of defective bits detected for each error correction unit is greater than the number that can be corrected, the block is recognized and used as a defective block. When the number of defective bits in all error correction units is equal to or less than the number capable of error correction, the block is used as an available block.
  3. A semiconductor memory system comprising the semiconductor memory according to claim 1 and a controller having an error correction function,
    The controller uses the block in which the first data is stored as a normal block, identifies the block in which the third data is stored as a bad block, does not use it, and stores the second data The block is subjected to a test for each error correction unit of each page, and the number of defective bits detected for each error correction unit is more than the number that can be error-corrected -α (α is the number of allowable defective bits later). If it is large, it is not recognized and used as a defective block, and if the number of defective bits in all error correction units is equal to or less than the error correctable number -α, it is used as an available block.
  4.   The semiconductor memory according to claim 1 is a NAND flash memory having a page size of 1 kB or more, includes a controller having an error correction function at four or more locations per 512 bytes, and N ≧ 3 and M> 4. Features.
  5. A semiconductor memory system comprising the semiconductor memory according to claim 1 and a controller having an error correction function,
    When the controller cannot handle the pseudo-pass block, the block in which the second data is stored is identified as a bad block and is not used.
JP2007025864A 2007-02-05 2007-02-05 Semiconductor memory and semiconductor memory system Pending JP2008192240A (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010237822A (en) * 2009-03-30 2010-10-21 Toshiba Corp Memory controller and semiconductor storage device
JP2011123964A (en) * 2009-12-11 2011-06-23 Toshiba Corp Semiconductor memory
JP2012069180A (en) * 2010-09-21 2012-04-05 Toshiba Corp Semiconductor storage device
JP2012203965A (en) * 2011-03-25 2012-10-22 Toshiba Corp Semiconductor storage device
JP2012212487A (en) * 2011-03-30 2012-11-01 Toshiba Corp Memory system
JP2017054351A (en) * 2015-09-10 2017-03-16 株式会社東芝 Memory system
US10275165B2 (en) 2016-09-12 2019-04-30 Toshiba Memory Corporation Memory controller
US10431322B1 (en) 2018-03-19 2019-10-01 Toshiba Memory Corporation Memory system

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010237822A (en) * 2009-03-30 2010-10-21 Toshiba Corp Memory controller and semiconductor storage device
JP2011123964A (en) * 2009-12-11 2011-06-23 Toshiba Corp Semiconductor memory
JP2012069180A (en) * 2010-09-21 2012-04-05 Toshiba Corp Semiconductor storage device
JP2012203965A (en) * 2011-03-25 2012-10-22 Toshiba Corp Semiconductor storage device
JP2012212487A (en) * 2011-03-30 2012-11-01 Toshiba Corp Memory system
JP2017054351A (en) * 2015-09-10 2017-03-16 株式会社東芝 Memory system
CN106531223A (en) * 2015-09-10 2017-03-22 株式会社东芝 Memory system
US10170202B2 (en) 2015-09-10 2019-01-01 Toshiba Memory Corporation Memory system
US10275165B2 (en) 2016-09-12 2019-04-30 Toshiba Memory Corporation Memory controller
US10431322B1 (en) 2018-03-19 2019-10-01 Toshiba Memory Corporation Memory system

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