KR20100027787A - Operating method of non volatile memory device - Google Patents

Operating method of non volatile memory device Download PDF

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Publication number
KR20100027787A
KR20100027787A KR1020080086837A KR20080086837A KR20100027787A KR 20100027787 A KR20100027787 A KR 20100027787A KR 1020080086837 A KR1020080086837 A KR 1020080086837A KR 20080086837 A KR20080086837 A KR 20080086837A KR 20100027787 A KR20100027787 A KR 20100027787A
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KR
South Korea
Prior art keywords
bits
cells
fail
ecc processing
fail bits
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KR1020080086837A
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Korean (ko)
Inventor
양해종
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주식회사 하이닉스반도체
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Priority to KR1020080086837A priority Critical patent/KR20100027787A/en
Publication of KR20100027787A publication Critical patent/KR20100027787A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

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  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for operating a non-volatile memory device is provided to operate the non-volatile memory device by setting outermost cells as dummy cells according to the occurrence of failure. CONSTITUTION: An external input data is stored in a first buffer and a non-volatile memory(310). The data stored in the non-volatile memory is read and stored in a second buffer(320). The data stored in the first buffer and the data stored in the second buffer are compared(330). The number of fail bits is verified. It is determined whether the fail bits are generated in outermost cells(340). If fail bits are generated in the outermost cells, it is verified whether the number of fail bits is more than the number of error correcting code(ECC) processing bits(342). If the number of fail bits is more than the number of the ECC processing bits, the corresponding outermost cells are set as dummy cells(370).

Description

Operating method of non volatile memory device

The present invention relates to a method of operating a nonvolatile memory device.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory cell is an electric program / eraseable device that performs program and erase operations by changing a threshold voltage of a cell while electrons are moved by a strong electric field applied to a thin oxide film.

A nonvolatile memory device typically includes a memory cell array in which cells in which data is stored is formed in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in the specific cell. The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling whether the specific bit line and the sensing node is connected.

Among the memory cells of the nonvolatile memory device, the memory cells adjacent to the source select transistor or the drain select transistor have different characteristics from other memory cells. In particular, after the program / erase count is increased, there is a problem in that a probability of generating a fail bit is higher than that of other memory cells.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of operating a nonvolatile memory device which operates by setting corresponding cells as dummy cells according to a fail generation state of outermost cells.

According to an aspect of the present invention, there is provided a method of operating a nonvolatile memory device, storing external input data in a first buffer and a nonvolatile memory, reading data stored in the nonvolatile memory, and storing the external input data in a second buffer. Determining the number of fail bits by comparing the data stored in the first buffer and the second buffer, determining whether the fail bit has occurred in the outermost cells, and determining the fail bit. Determining whether the number of fail bits is greater than the number of error correcting code (ECC) processing bits when they occur in outer cells; and when the number of fail bits is greater than the number of ECC processing bits, corresponding outermost cells are referred to as dummy cells. It characterized in that it comprises a step of setting.

According to the above-described problem solving means of the present invention can operate by setting the corresponding cells as a dummy cell according to the number of fail bits of the outermost cells. Since the number of fail bits has a characteristic that varies depending on the number of program / erase times, it is possible to operate by setting the outermost cells as dummy cells in accordance with the number of program / erase times.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1 is a diagram illustrating a relationship between a nonvolatile memory device and a host according to an exemplary embodiment of the present invention.

The host 110 may be various application devices that store data in the nonvolatile memory device 120 or read and use data stored in the nonvolatile memory device 120. Various application devices such as an MP3 player, a digital camera, a mobile phone, and a navigation using the nonvolatile memory device 120 as a main storage device are included.

The nonvolatile memory device 120 includes a nonvolatile memory 124 in which data transferred from the host 110 is stored, a controller 130 for controlling various operations of the nonvolatile memory device 120, and the host 110. The first buffer 126 is temporarily stored in the input data delivered from), and the second buffer 128 is temporarily stored in the data read from the nonvolatile memory 124 device.

The controller 130 reads data from the nonvolatile memory 124 to check whether an error occurs, and corrects the error, and includes an error correcting code (ECC) processor 132, a first buffer 126, and a second buffer ( The data comparison unit 134 confirms whether or not the data is identical to the data of the processor 128, and a repair circuit unit 136 for bad-blocking the memory cell block including the memory cells to be compared according to the result of the data comparison unit and applying a repair algorithm. It includes.

The ECC processing unit 132 may correct an error when there are fail bits below the threshold value among the read data, and when there are more fail bits, error correction is impossible. Therefore, even if a fail bit occurs in a specific page, when the threshold value is less than or equal to, the corresponding cells are determined as normal cells. However, if the number of fail bits exceeds the threshold, ECC processing is impossible and thus the memory cell block including the corresponding cell is bad-blocked.

For example, assuming that 8-bit error correction is possible per 512byte, if a 9-bit fail bit occurs, error correction is impossible and thus the corresponding block is bad-blocked. However, if an 8-bit fail bit occurs, error correction is possible, and thus the error correction is performed through the ECC processing unit 132.

In this case, the number of occurrences of fail bits is determined using the first buffer 126 and the second buffer 128. Input data transmitted from the host is stored in the first buffer 126. Since data read from the nonvolatile memory 124 is stored in the second buffer 128, the number of occurrences of fail cells is compared by comparing them. You can judge. The first buffer and the second buffer are composed of DRAM or SRAM.

The nonvolatile memory 124 may include a memory cell array including a plurality of nonvolatile memory cells, various high voltage generators, a page buffer, and the like. Among them, a detailed configuration of the memory cell array will be described.

2 is a diagram illustrating a memory cell array structure of a nonvolatile memory device according to the present invention.

 The illustrated memory cell array 200 is a single memory cell block. The memory cell array 200 may include memory cells MC0 to MCn that store data, word lines WL0, WL1,..., WLn that select and activate the memory cells, and the memory cells. It includes bit lines (BLe, BLo) for inputting and outputting data, the plurality of word lines and a plurality of bit lines are arranged in a matrix form. The memory cell array includes a drain select transistor DST connected between a bit line and a memory cell, and a source select transistor SST connected between a memory cell and a common source line CSL. In addition, the memory cell may include memory cells connected in series between the source select transistor SST and the drain select transistor DST.

Gates of the memory cells are connected to word lines, and a set of memory cells connected to the same word line by a page is called a page. A plurality of cell strings connected to each bit line are connected in parallel to a common source line to form a block.

Meanwhile, the memory cells 210 adjacent to the drain select transistors DST and the memory cells 220 adjacent to the source select transistors SST have different characteristics from those of other memory cells. Memory cells 210 and 220 adjacent to each of the select transistors have a higher probability of failing than other memory cells when the program and erase operations are repeatedly performed. In particular, in the erase operation, the erase speed of the memory cells 210 and 220 is decreased by the coupling of the selection transistors DST and SST, thereby causing an erase fail phenomenon. In the program operation, failure due to hot carrier injection (HCI) causes the program operation to occur even in the erase target cell. This phenomenon occurs after the program / erase count is increased to some extent than the initial operation.

 As described above, since the probability of occurrence of a fail cell is high in the memory cells adjacent to each of the select transistors, that is, the outermost cells, the present invention intends to apply the ECC processing algorithm and the repair algorithm by distinguishing the outermost cells from the other memory cells. do.

3 is a flowchart illustrating a method of operating a nonvolatile memory device according to an exemplary embodiment of the present invention.

First, external input data transmitted from the host 110 is stored in the first buffer 126 and the nonvolatile memory 124 (step 310).

The external input data is not only stored in the nonvolatile memory 124 through a program operation but also stored in the first buffer 126 so that data can be compared at a later stage.

Next, the nonvolatile memory 124 is read, and the read data is stored in the second buffer (step 320).

Next, the number of fail bits is determined by comparing the data of the first buffer and the second buffer (step 330). Ideally, the data stored in each buffer should be identical. However, since a fail may occur in a program operation process or a read process for the nonvolatile memory, the number of fail bits is determined by checking whether each data is identical. If the data stored in the second buffer is different from the data stored in the first buffer, the data is determined to be a fail bit.

Next, as a result of the comparison, it is determined whether a fail bit has occurred in the cells 210 and 220 adjacent to each selection transistor (step 340). Since data is compared and determined for each page, and addresses are different for each page, it may be determined whether a page in which a fail bit is generated is a page adjacent to each selection transistor.

If the fail bit is a general memory cell instead of the outermost cell, processing is performed according to a conventional algorithm. That is, the number of fail bits is compared with the number of ECC processing bits (step 342). If the number of fail bits is smaller than the number of processing bits of the ECC processing unit 132, the ECC processing unit 132 applies and processes the ECC algorithm. (Step 360). However, if the number of fail bits is larger than the number of processing bits of the ECC processing unit 132, the ECC processing unit 132 may not process it, and thus a repair algorithm is performed on the corresponding cell (step 344).

However, if the fail bit is the outermost cell, processing is performed according to an embodiment of the present invention (step 350). That is, when the number of fail bits is smaller than the number of processing bits of the ECC processing unit 132, the processing is performed by applying the ECC algorithm through the ECC processing unit 132 (step 360). However, if the number of fail bits is larger than the number of bits of the ECC processor 132, the ECC processor 132 may not process the outermost cells, so the outermost cells are set as dummy cells (step 370).

The dummy cell is inserted between the memory cell and the select transistors to block interference between the memory cell and the select transistor during a program or erase operation. Recently, a configuration of inserting a dummy cell has been used to perform this role. In the present invention, when the number of fail bit occurrences of the outermost cells increases as the number of programs / erases increases, this is set and used as a dummy cell. Therefore, the memory cell block including the cell does not have to be treated as a bad block. In general, considering that generation of fail bits is concentrated in the outermost cells in one memory cell block, the amount of bad blocks processed according to this measure may be reduced.

If the fail bit is greater than the number of ECC processing bits only in the cell 210 adjacent to the drain source select transistor, only the corresponding cells are set as dummy cells. Similarly, if the fail bit is more than the ECC processing bit number only in the cell 220 adjacent to the source select transistor, only the corresponding cells are set as dummy cells.

For the set dummy cell, a pass voltage is applied to the word lines of the dummy cells during a program or read operation (step 380).

The set dummy cells do not allow external data to be programmed. In addition, a pass voltage is applied to the word lines of the dummy cells so that the program operation is not performed. Likewise, during a verify operation or a read operation, a pass voltage is applied to continuously turn on corresponding cells. However, the level of the pass voltage applied during the program operation may be different from the level of the pass voltage applied during the verify / read operation. In the erase operation, like the other cells, the target is erased.

As described above, when the number of fail bits generated in the outermost cells exceeds a specific number, the cells are set as dummy cells to operate.

1 is a diagram illustrating a relationship between a nonvolatile memory device and a host according to an exemplary embodiment of the present invention.

2 is a diagram illustrating a memory cell array structure of a nonvolatile memory device according to the present invention.

3 is a flowchart illustrating a method of operating a nonvolatile memory device according to an exemplary embodiment of the present invention.

Claims (15)

Storing the external input data in the first buffer and the nonvolatile memory; Reading data stored in the nonvolatile memory and storing the data in a second buffer; Comparing the data stored in the first buffer and the second buffer to determine the number of fail bits; Determining whether the fail bit has occurred in the outermost cells; Determining whether the number of fail bits is greater than an error correcting code (ECC) processing bit when the fail bits occur in outermost cells; And setting the outermost cells as dummy cells when the number of fail bits is greater than the number of ECC processing bits. The method of claim 1, wherein the determining of the number of fail bits is performed based on data in units of pages. The method of claim 1, wherein the determining of the number of fail bits comprises: If the data stored in the second buffer is different from the data stored in the first buffer, determining the corresponding data as a fail bit. The method of claim 1, wherein the determining of whether the fail bit has occurred in the outermost cells is performed based on data in units of pages. The method of claim 1, wherein the determining whether the number of fail bits is greater than the number of ECC processing bits is performed. And comparing the number of fail bits of the cells adjacent to the drain select transistor with the size of the number of ECC processing bits. The method of claim 1, wherein the determining whether the number of fail bits is greater than the number of ECC processing bits is performed. And comparing the number of fail bits of the cells adjacent to the source select transistor with the size of the number of ECC processing bits. The method of claim 1, wherein the determining whether the number of fail bits is greater than the number of ECC processing bits is performed. And comparing the sum of the number of fail bits of the cells adjacent to the source select transistor and the number of fail bits of the cells adjacent to the drain select transistor with the size of the number of ECC processing bits. . 2. The method of claim 1, further comprising performing error correction through an ECC processing algorithm when the number of fail bits is smaller than the number of ECC processing bits. The method of claim 1, wherein when the number of fail bits is greater than the number of ECC processing bits, setting the outermost cells as dummy cells And setting the cells adjacent to the source select transistor as dummy cells when the number of fail bits of the cells adjacent to the source select transistor is greater than the number of ECC processing bits. The method of claim 1, wherein when the number of fail bits is greater than the number of ECC processing bits, setting the outermost cells as dummy cells And setting the cells adjacent to the drain select transistor as dummy cells when the number of fail bits of cells adjacent to the drain select transistor is greater than the number of ECC processing bits. The method of claim 1, wherein when the number of fail bits is greater than the number of ECC processing bits, setting the outermost cells as dummy cells If the sum of the number of fail bits of the cells adjacent to the drain select transistor and the number of fail bits of the cells adjacent to the source select transistor is greater than the number of ECC processing bits, setting the cells adjacent to the drain select transistor as dummy cells. A method of operating a nonvolatile memory device. The method of claim 1, further comprising: determining whether the number of fail bits is greater than the number of ECC processing bits when the fail bits occur in cells other than the outermost cell; And applying a repair algorithm to corresponding cells when the number of fail bits is greater than the number of ECC processing bits. The method of claim 12, further comprising performing error correction through an ECC processing algorithm when the number of fail bits is smaller than the number of ECC processing bits. The method of claim 1, further comprising applying a first pass voltage to cells configured as the dummy cell during a program operation. The method of claim 1, further comprising applying a second pass voltage to the cells set as the dummy cells in a read operation.
KR1020080086837A 2008-09-03 2008-09-03 Operating method of non volatile memory device KR20100027787A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9620246B2 (en) 2014-12-18 2017-04-11 SK Hynix Inc. Operating method of memory system
US9754677B2 (en) 2015-02-02 2017-09-05 SK Hynix Inc. Semiconductor memory device, memory system including the same, and operating method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9620246B2 (en) 2014-12-18 2017-04-11 SK Hynix Inc. Operating method of memory system
US9754677B2 (en) 2015-02-02 2017-09-05 SK Hynix Inc. Semiconductor memory device, memory system including the same, and operating method thereof

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