JPS6226120B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory circuit that requires read operation.

2. Description of the Related Art In recent years, semiconductor memory circuits that require playback operations have been widely used in computers, measuring instruments, and the like. 1st
The figure shows a block diagram of a conventional semiconductor memory circuit. In the read operation, the address signal AX is applied to the address buffer (X) circuit section 11, and the row selection circuit section,
12, one row of the cell matrix 13 is selected, and the remaining address signal AY is also applied to the address buffer (Y) circuit section 14 in the same way as AX, and is passed through the column selection circuit section 15 to select one row of the cell matrix 13. Part 13
This is executed by selecting a column of , and passing the information of the selected cell through the sense amplifier circuit section 16, and through the input/output control circuit section 17, and extracting it as read data DO. Next, in the write operation, cell matrix selection is performed in the same way as in the read operation, but as is clear from the read/write timing diagram in FIG. 2, the write instruction signal WE and write data DI are input. The write data is applied to the control circuit section 17 and is executed by being stored in the cell matrix 13 via the sense amplifier circuit section 16. For other read and write operations, a memory circuit activation signal CE is applied to the timing generation circuit section 18 for generating internal timing of the memory circuit, and an element selection signal CS is applied to the input/output control circuit section 17.

As is clear from this, errors in the information in the cell matrix 13 are output as they are as output data DO. As a method for solving the disadvantages of the conventional example, a semiconductor memory circuit having a built-in error correction circuit inside the element has been proposed. This is shown in FIG. Read operation uses address signal
Applying AX to the address buffer X circuit section 21,
The data is passed through the row selection circuit section 22, selects one row of the cell matrix 23, and the data read out by the cell matrix 23 is passed through the sense amplifier circuit section 26, error correction circuit section 30, and data buffer circuit section 29, and then is sent to the address. The column selection circuit section 25 selects column data based on the remaining address AY applied to the buffer (Y) circuit section 24, transfers it to the input/output control circuit section 27, and outputs corrected correct data.
This is executed by outputting it as DO. Next, in the write operation, row selection of the cell matrix is performed in the same way as in the read operation, but the write data DI is passed through the input/output control circuit section 27, and the data output from the sense amplifier circuit section 26 is used to buffer the data buffer. Parity data is generated by the parity generation circuit section 20 together with the data that has passed through the circuit section 29, passes through the sense amplifier circuit section 26, and is written into a selected row of the cell matrix 23 as a new row data group. During other write and read operations, a memory circuit activation signal CE for generating internal timing of the memory circuit is applied to the timing generation circuit section 28, and an element selection signal CS is applied to the input/output control circuit section 27. As is clear from this, errors in the information in the cell matrix 23 are corrected and output as output data DO. Such a semiconductor memory circuit has the disadvantage that the read speed is slow because errors are always corrected in the error correction circuit section 30 during reading.

The present invention relates to a semiconductor memory circuit that eliminates such conventional drawbacks.

According to the present invention, in a semiconductor memory circuit in which internal memory cells are arranged in a matrix of a plurality of rows and a plurality of columns and which requires a data reproducing operation, a predetermined number of additional bit cells are provided in each row, and when writing, Information from the memory cells in the plurality of columns in the selected row is read, and an error code is generated based on the information written in the memory in the selected column and the information in other memory cells in the selected row. The error code is written to the additional bit located in the selected row, the error correction operation is prohibited during reading, and the error correction of the memory cell in the selected row and the data regeneration operation are performed only during the data reproduction operation. A semiconductor memory circuit which is characterized by the above characteristics and is highly reliable and has no delay in read speed can be obtained.

FIG. 4 shows an embodiment of the present invention, and FIG. 5 shows an example of an operation timing diagram. Address buffer (X) circuit section 121, address buffer Y circuit section 124, row selection circuit section 122, cell matrix circuit section 12
3. Timing generation circuit section 128, parity generation circuit section 120, sense amplifier circuit section 126, error correction circuit section 130, data buffer circuit section, 12
9. Column selection circuit section 125, input/output control circuit section 12
7, and a reproduction operation detection circuit section 100.

The write operation is performed by address buffer (X) circuit section 1.
21, the address AX is applied to the row selection circuit section 12.
Select one row of the cell matrix 123 that has passed through 2 and write data to the input/output control circuit section 127.
By applying DI, write signal WE, and element control signal CS, the parity signal generation circuit section 120
This is executed by writing the parity bit generated from the row data and write data that have passed through the data buffer 129 together with the write data DI into the selected row of the cell matrix. As is clear from the operation timing diagram of FIG. 5, the read operation is similar to the write operation, but since the reproduction operation instruction signal RS is not activated and the reproduction operation detection circuit section 100 is not in the reproduction instruction state, No error correction is performed on the data, and the data read from the cell matrix 123 passes through the sense amplifier circuit section 126 and the data buffer circuit section 129, and is then read out from the column data selected by the column selection circuit section 125 to which the address AY is applied. This is executed by taking out as output data DO via the input/output control circuit section 127. For other read/write operations, the memory circuit activation signal CE is supplied to the timing generation circuit section 1 for internal timing generation.
28.

As is clear here, since the error correction circuit section 130 is not activated during reading, the drawback that the reading speed is delayed can be eliminated. Next, the reproducing operation is similar to the reading operation, but by applying the reproducing operation instruction signal RS to the reproducing operation detecting circuit section 100, the reproducing operation detecting circuit section 100 is activated, and the address signal applied from the outside is activated. One row of the cell matrix selected by AX passes through the sense amplifier circuit section 126, and when the reproduction operation detection circuit section is activated, the error correction circuit section 130 is activated, and the corrected data is sent to the data buffer circuit section. 129, the sense amplifier circuit section 126, and is rewritten into the cell matrix 123.

During this reproducing operation, the semiconductor memory circuit that requires the reproducing operation is unable to read or write, so using this time to check for errors in the cell matrix is not recommended at the expense of operating speed. This leads to a significant improvement in reliability without any additional processing, and a highly reliable high-speed semiconductor memory circuit can be obtained.

As described above, the present invention provides a semiconductor memory circuit that improves the reliability of conventional memory circuits and alleviates the speed disadvantage, and various modifications may be made without departing from the scope of the present invention as defined in the appended claims. Obviously, changes are possible.

[Brief explanation of the drawing]

FIG. 1 is a conventional example of a semiconductor memory circuit, FIG. 2 is a read/write timing diagram of a conventional example, FIG. 3 is a conventional example of a semiconductor memory circuit with an error correction function, and FIG. 4 is an example of an embodiment of the present invention. FIG. 5 is an operation timing diagram of the present invention. 11: Address buffer, 12: Row selection circuit,
13: Cell matrix.

Claims (1)

[Claims] 1. In a semiconductor memory circuit in which memory cells are arranged in a matrix of a plurality of rows and a plurality of columns and requires a data reproducing operation, a predetermined number of additional bit cells are provided in each row, and a predetermined number of additional bit cells are provided in a selected row at the time of writing. The information from the memory cells in the plurality of columns is read, an error code is generated based on the information written to the memory in the selected column and the information in the other memory cells in the selected row, and the error code is Writes to the additional bit located in the selected row, prohibits error correction operation when reading,
A semiconductor memory circuit characterized in that error correction of memory cells in a selected row and data reproduction operation are performed only during data reproduction operation.