JPS56129952A - Error correction system - Google Patents

Error correction system

Info

Publication number
JPS56129952A
JPS56129952A JP3221380A JP3221380A JPS56129952A JP S56129952 A JPS56129952 A JP S56129952A JP 3221380 A JP3221380 A JP 3221380A JP 3221380 A JP3221380 A JP 3221380A JP S56129952 A JPS56129952 A JP S56129952A
Authority
JP
Japan
Prior art keywords
data
transfer
memory unit
error
transferred
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3221380A
Other languages
Japanese (ja)
Inventor
Toru Tejima
Hiroki Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3221380A priority Critical patent/JPS56129952A/en
Publication of JPS56129952A publication Critical patent/JPS56129952A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Abstract

PURPOSE:To enable to reduce the data transfer time remarkably, by retransferring the code with error after error correction, in the system transferring data through the use of error correction code. CONSTITUTION:When the transfer instruction C is delivered to the transfer instruction reception circuit 1 of the external memory unit FM from the central processing unit CPU, the data D to be transferred is read out from the memory unit 2, and it is transmitted to the transfer circuit 5' directly via the path 6 and the data D is transferred to the main memory unit MM. Simultaneously, the data D read out from the memory unit 2 is detected for error via the path 7 and corrected and transferred to the transfer circuit 5', and it is further transferred to the main memory unit MM address the same as the transfer data not corrected for error, which is transmitted to the transfer circuit 5' via the path 6, allowing to correct the transfer data. Since the probability of error detection is very low generally, the data transfer time can remarkably be reduced.
JP3221380A 1980-03-14 1980-03-14 Error correction system Pending JPS56129952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3221380A JPS56129952A (en) 1980-03-14 1980-03-14 Error correction system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3221380A JPS56129952A (en) 1980-03-14 1980-03-14 Error correction system

Publications (1)

Publication Number Publication Date
JPS56129952A true JPS56129952A (en) 1981-10-12

Family

ID=12352635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3221380A Pending JPS56129952A (en) 1980-03-14 1980-03-14 Error correction system

Country Status (1)

Country Link
JP (1) JPS56129952A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2400393A2 (en) 2010-06-24 2011-12-28 Fujitsu Limited Data processing circuit and data processing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2400393A2 (en) 2010-06-24 2011-12-28 Fujitsu Limited Data processing circuit and data processing method
JP2012010108A (en) * 2010-06-24 2012-01-12 Fujitsu Ltd Data processing circuit and data processing method
US8539306B2 (en) 2010-06-24 2013-09-17 Fujitsu Limited Data processing circuit and data processing method

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