JPS5476033A - Interruption method for high-level data transmission control system - Google Patents

Interruption method for high-level data transmission control system

Info

Publication number
JPS5476033A
JPS5476033A JP14341477A JP14341477A JPS5476033A JP S5476033 A JPS5476033 A JP S5476033A JP 14341477 A JP14341477 A JP 14341477A JP 14341477 A JP14341477 A JP 14341477A JP S5476033 A JPS5476033 A JP S5476033A
Authority
JP
Japan
Prior art keywords
reception
circuit
channel
register
operation result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14341477A
Other languages
Japanese (ja)
Other versions
JPS6049351B2 (en
Inventor
Tomohito Shibata
Tadaaki Imai
Kazuo Shimomichi
Kanzo Noda
Masaaki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP52143414A priority Critical patent/JPS6049351B2/en
Publication of JPS5476033A publication Critical patent/JPS5476033A/en
Publication of JPS6049351B2 publication Critical patent/JPS6049351B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To decrease the information transfer between the channel of the circuit control and the line adaptor by transmitting the interruption signal when the end flag is received and the result of the cyclic redundancy check is correct.
CONSTITUTION: The reception of the end flag by transmission/reception 12 of line adaptor 3 at the data reception time is informed to transmission/reception control circuit 8. In this case, frame check sequence FCS which is stored in 32-bit check register 9-1 and 9-2 is not trnasmitted to channel 1 of the circuit control. The results the CRC operation from the address to FCS are stored in cyclic redundancy check CRC register 11, and circuit 8 reads out the operation result of register 11 with reception of the above information. And in case the operation result is in the fixed value, circuit 8 transmits the interruption signal to channel 1 to indicate that the frame has the normal end and that the CRC operation result is all right.
COPYRIGHT: (C)1979,JPO&Japio
JP52143414A 1977-11-30 1977-11-30 Interrupt method of high-level data transmission control system Expired JPS6049351B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52143414A JPS6049351B2 (en) 1977-11-30 1977-11-30 Interrupt method of high-level data transmission control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52143414A JPS6049351B2 (en) 1977-11-30 1977-11-30 Interrupt method of high-level data transmission control system

Publications (2)

Publication Number Publication Date
JPS5476033A true JPS5476033A (en) 1979-06-18
JPS6049351B2 JPS6049351B2 (en) 1985-11-01

Family

ID=15338205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52143414A Expired JPS6049351B2 (en) 1977-11-30 1977-11-30 Interrupt method of high-level data transmission control system

Country Status (1)

Country Link
JP (1) JPS6049351B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5614752A (en) * 1979-07-17 1981-02-13 Nec Corp Processing system for received data signal
JPS6073764A (en) * 1983-09-30 1985-04-25 Toshiba Corp Interruption controller
JPH0338943A (en) * 1989-06-29 1991-02-20 Internatl Business Mach Corp <Ibm> Terminal adapter having many adlc communication channel receiver

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5391543A (en) * 1977-01-24 1978-08-11 Hitachi Ltd Installation system for hdlc circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5391543A (en) * 1977-01-24 1978-08-11 Hitachi Ltd Installation system for hdlc circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5614752A (en) * 1979-07-17 1981-02-13 Nec Corp Processing system for received data signal
JPS6073764A (en) * 1983-09-30 1985-04-25 Toshiba Corp Interruption controller
JPH0338943A (en) * 1989-06-29 1991-02-20 Internatl Business Mach Corp <Ibm> Terminal adapter having many adlc communication channel receiver

Also Published As

Publication number Publication date
JPS6049351B2 (en) 1985-11-01

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