JPS56122251A - Synchronous control system - Google Patents

Synchronous control system

Info

Publication number
JPS56122251A
JPS56122251A JP2470580A JP2470580A JPS56122251A JP S56122251 A JPS56122251 A JP S56122251A JP 2470580 A JP2470580 A JP 2470580A JP 2470580 A JP2470580 A JP 2470580A JP S56122251 A JPS56122251 A JP S56122251A
Authority
JP
Japan
Prior art keywords
pattern
reception
phase shift
address
bit number
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2470580A
Other languages
Japanese (ja)
Other versions
JPS6024616B2 (en
Inventor
Kyoji Koseki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55024705A priority Critical patent/JPS6024616B2/en
Publication of JPS56122251A publication Critical patent/JPS56122251A/en
Publication of JPS6024616B2 publication Critical patent/JPS6024616B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Facsimile Transmission Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To enable to make a decision of reception of the synchronous signal for a data processor, by extracting the number of the phase shift bits to a certain pattern in the form of the reception data and an address and from the fact that the bit number of the same phase shift has emerged with a probability larger than the prescribed value. CONSTITUTION:In case a certain pattern signal M0 is transmitted 10 times from the transmission side, it is not necessarily at the reception side that the pattern signal is received with the same phase maintained or without causing an error bit. In general the pattern Mn that is shifted from the pattern M0 by n bits is received at the shift register 4 via the RD terminal. This Mn pattern is sent to the data processor 1 to extract the phase shift bit number n to the pattern M0 and the error bit number given from the pattern M0. In other words, the reception data is sent to the address decoder 2 to give an designation to the address of ROM7. The pattern M0 is put into the ROM7 and then read out to the CPU1 for comparison.
JP55024705A 1980-02-29 1980-02-29 Synchronous control method Expired JPS6024616B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55024705A JPS6024616B2 (en) 1980-02-29 1980-02-29 Synchronous control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55024705A JPS6024616B2 (en) 1980-02-29 1980-02-29 Synchronous control method

Publications (2)

Publication Number Publication Date
JPS56122251A true JPS56122251A (en) 1981-09-25
JPS6024616B2 JPS6024616B2 (en) 1985-06-13

Family

ID=12145587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55024705A Expired JPS6024616B2 (en) 1980-02-29 1980-02-29 Synchronous control method

Country Status (1)

Country Link
JP (1) JPS6024616B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57193171A (en) * 1981-05-22 1982-11-27 Nec Corp Synchronism detecting device for facsimile signal
JPS5977745A (en) * 1982-10-22 1984-05-04 Fujitsu Ltd Transmission control system
JPS61166239A (en) * 1985-01-18 1986-07-26 Oki Electric Ind Co Ltd Timing recovery circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH035513U (en) * 1989-06-02 1991-01-21

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57193171A (en) * 1981-05-22 1982-11-27 Nec Corp Synchronism detecting device for facsimile signal
JPS6322669B2 (en) * 1981-05-22 1988-05-12 Nippon Electric Co
JPS5977745A (en) * 1982-10-22 1984-05-04 Fujitsu Ltd Transmission control system
JPS61166239A (en) * 1985-01-18 1986-07-26 Oki Electric Ind Co Ltd Timing recovery circuit

Also Published As

Publication number Publication date
JPS6024616B2 (en) 1985-06-13

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