JPS6024616B2 - Synchronous control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization control system with a simple configuration in which a fixed pattern of signals is sent out multiple times and frame synchronization is achieved during the transmission.

When transmitting data such as facsimile image information, in order to achieve frame synchronization on the receiving side, a certain pattern Mo as shown in Figure 1 is sent 10 times, followed by M.
Mo, which is the inversion of o, is sent twice, and then a data frame is started.

The fixed pattern area is a typical 15-bit random pattern, for example, “00010011010111r
is used. This pattern is recorded in a shift register on the receiving side, compared with the Mo reference pattern, the maximum 4 points of distance are detected to determine the receiving place pattern, and this and the Mo pattern having a distance of 15 bits are compared twice. The detected point becomes the frame synchronization point. This configuration becomes quite complex, especially if a circuit for synchronization pull-in when fading or burst noise is present at the data start point is introduced. SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization control system with a simple configuration in which a fixed pattern of signals is sent out a plurality of times and frame synchronization is achieved during the transmission.

In order to achieve the above object, the synchronization control method of the present invention transmits a signal with a fixed pattern consisting of a predetermined number of bits multiple times, detects the pattern signal on the receiving side, and synchronizes the frame. a pattern constant storage section storing values determined in relation to the certain pattern; a shift register storing received data; and interrupting the data processor when the shift register receives a specified number of bits. comprising a circuit;
The data processor creates a bit string by dividing the received signal into a predetermined number of bits, uses the bit string as an address to access the pattern constant storage section, and reads the constant pattern occurring in the received signal from the pattern constant storage section. The number of phase shift bits is extracted from the consecutively received signals, and synchronized signal reception is determined by extracting the same number of phase shift bits a predetermined number of times or more from the continuously received signal. The present invention is characterized in that a value is instructed to the circuit so that an interrupt is generated at the phase of a fixed pattern break in the received signal.

The present invention will be described in detail below with reference to examples.

To explain the principle of the present invention, when a signal Mo having a fixed pattern made up of 15 bits is sent multiple times from the transmitting side, the receiving side does not necessarily receive it with the same phase as the Mo pattern of the transmitting side. , it is also possible that an error bit has occurred.

15 bits (or 8 bits and 7 bits) of received data
When received, generally, M Luyatan, which is shifted by n bits from the shame pattern, is received. Send this Mn pattern to the data processor.Number of bits out of phase with the pigeon pattern.
and the number of error bits from the Mo/f turn. Bit errors in this case are detected up to 2 bits. When this n is constant and an Mn signal with a bit error of 2 bits or less is obtained three times in a row, a break in the Mo pattern is determined based on n. In other words, if n=1, 2, 3, ..., 14, each of the received Mn patterns has 15-
n=14, 13, 12, . . ., the pigeon pattern is separated at the 1st bit.

It is confirmed that the next pattern after this break is the Mo pattern, and that this Mo pattern is detected twice in a row. In this manner, frame synchronization can be entered by instructing the number of bits corresponding to n and causing an interrupt to the data processor. FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention, and shows a signal receiving circuit to which the Motooka method is applied.

As mentioned above, frame synchronization is performed from the transmitting side, so
The 15-bit Mo pattern “00010011” in FIG.
0101111" is returned over the lm line, followed by Mo twice and sent out in advance of the data. On the receiving side, this received data (RD) is stored in shift register 4 as 8 bits and 7 bits.
The data is divided into two bits and stored at a predetermined timing (RT). A data processor indicating the length of the data initially stored in the shift register 4, that is, the above-mentioned 8 bits, is given to the counter 5 from the output terminals Do to D3 of the CPUI for counting, and the carry signal (CRY) is sent to the CPU.
Parallel output Q^~Q of shift register 4 by interrupting I
H is input into the three-state gate 3, where it is switched from a high impedance state to a low impedance state under address control from the address decoder 2, and sent to the CPUI for reading. Next, data indicating the next 7 bits to be received is given to the counter 5 from output terminals Do to D3 of the CPUI, read by the CPU in the same procedure, and received as 15 bits by combining it with the above 8 bits. do. This 15-bit data is sent to address line A from the CPUI.
˜A, 5 and the fixed memory (ROM) 7 is accessed by the address decoder 2. A value indicating the deviation from the Mo pattern is output from the ROM 7 and sent to the CPUI via the data bus. In this way, the CPU outputs the parallel outputs Q^~QH of the shift register 4, and determines the number n of phase shift bits stored in the ROM 7, that is, the shift (n) between the Mo pattern series and the reception pattern used for the address.
The number of error bits is checked, and error bits of 2 or less bits are corrected using a known error correction method.
Subsequently, similar processing is performed on the next received Mn pattern, that is, detection of the number n of phase shift bits and checking of the number of error bits.

Then, when data with the same phase shift is detected three times in a row, the number of bits (15-n) up to the break of the Mo pattern related to the number of phase shift bits n is sent to the counter 5 from the output terminals Do to D3. Give and count, receive data (RD)
Determine the break position of the Mo pattern of the main button and perform phase correction of the received data (RD).

Next, the carry signal from counter 5 (
CRY) is given to the CPUI as an interrupt signal, and the Mo pattern is detected twice in succession, thereby determining the synchronization point of the data frame of the received data 4RD).

Note that the non-volatile memory (RAM) 6 stores control data such as the CPUI. As described above, according to the present invention, there is provided a data processor, a pattern constant storage unit storing values determined in relation to the certain pattern, a shift register that stores received data, and a data processor that stores a specified number of bits. and a circuit that interrupts the data processor when the shift register receives the signal, and the data processor divides the received signal into a bit string by a predetermined number of bits, and uses the bit string as an address to write to the pattern constant storage section. access, extract the number of phase shift bits from the fixed pattern occurring in the received signal from the pattern constant storage section, and synchronize when the same number of phase shift bits is extracted a predetermined number of times or more from the continuously received signal. Signal reception is determined, and a value determined from the number of phase shift bits and a predetermined number of bits is instructed to the circuit, and an interrupt is generated at the phase of a fixed pattern break in the received signal to perform frame synchronization. In this case, the configuration is relatively simple, and by changing the settings of the number of Mo patterns and the number of allowable error bits, a synchronization system that is resistant to fading, burst noise, etc. can be obtained.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a constant pattern for synchronization, and FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention. In the figure, 1 is a CPU
, 2 is an address decoder, 3 is a three-state gate,
4 is a shift register, 5 is a counter, 6 is a RAM, and 7 is a ROM. Figure 1 Figure 2

Claims (1)

[Claims] 1 In a synchronization control method in which a signal with a fixed pattern consisting of a predetermined number of bits is sent multiple times and the receiving side detects the pattern signal to achieve frame synchronization, a data processor and a value determined in relation to the fixed pattern are transmitted. The data processor includes a pattern constant storage section, a shift register for accumulating received data, and a circuit that interrupts the data processor when the shift register receives a specified number of bits. A bit string is created by dividing the signal into a predetermined number of bits, the bit string is used as an address to access the pattern constant storage section, and the phase relative to the certain pattern occurring in the received signal is determined from the pattern constant storage section. The number of phase shift bits is extracted, and synchronization signal reception is determined when the same number of phase shift bits is extracted a predetermined number of times or more from continuously received signals, and the value determined from the phase shift bit number and the predetermined number of bits is determined as described above. A synchronous control method characterized by instructing a circuit to issue an interrupt at the phase of a fixed pattern of received signals.