JPS606139B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronization circuit used in a synchronous transmission method among transmission methods used in digital transmission lines.

In the synchronous transmission method, a synchronous bit is inserted into the data every certain period of time, and the receiving side identifies or recombines the data by detecting the synchronous bit (data transmission Since parallel data is usually converted into serial data and sent out, it is necessary to recombine the serial data into parallel data on the receiving side.

In this case, the synchronization bit serves as a mark to detect the beginning of the serial data.) The section from synchronization bit to synchronization bit is called a frame. The same sardine bit is usually 1
It is made up of bits to several bits, and follows certain rules agreed upon between the transmitter and receiver so that the receiving side can confirm that it is a synchronous bit. For example, in the case of a synchronization bit consisting of one bit, set a rule such that it is always inverted every frame (if the synchronization bit in the nth frame is "1", it is "0" in the (n+1)th frame). . The frame synchronization circuit is required to detect this synchronization bit reliably and quickly, and to prevent synchronization 0 from occurring as much as possible when a code error occurs, or to recover quickly even when synchronization occurs. The secondary frame synchronization circuit compares two bits that have the same phase relationship each other for each frame synchronization, and if the conditions necessary for being a synchronization bit are met, it is set to synchronizer mode, and if the conditions are not met a certain number of times in a row, it is set to synchronizer mode. Switching to out-of-synchronization mode, checking the phase by shifting one bit for each frame, and if there is a bit that satisfies the conditions for a synchronization bit, that bit is configured as a synchronization bit and returning to synchronization mode.

Although this kind of frame synchronization circuit is robust against code errors, from the time detection starts (out of synchronization or when the system starts) until entering synchronization mode, there are no code errors and bits other than the synchronization bit are Even if the condition were to be met by chance, in the worst case, it would take time equivalent to the same number of frames as the number of frame constituent bits. For example, synchronization bit 1 bit + data bit 7
In the case of a frame consisting of 9 bits, a total of 80 bits,
It can take 80 frames to get synchronized, which is very slow. An object of the present invention is to provide a frame synchronization circuit that can shorten the time until synchronization is achieved by checking whether or not each bit is a synchronization bit, not every frame.

Next, a more detailed explanation will be given using the drawings.

FIG. 1 shows an example of the configuration of a conventional frame synchronization circuit. The frame synchronization circuit receives two inputs: serial data and a clock that provides timing for the data. Since the frame synchronization is known and only the frame phase is unknown, it is only necessary to know the frame phase, that is, the time representing the beginning of the frame, as the output of the synchronization circuit. Serial data is input from an input terminal 100 and supplied to a latch 20 and a synchronization bit determination circuit 301, and a clock is supplied from an input terminal 200 to a frame synchronization counter 10 and divided into frame frequencies. Since the frame synchronization counter o' has a number of internal states equal to the number of bits constituting the frame (frame length), the frame period output is sent to the latch 20 and the outside as a synchronization output only once per frame. Only one bit is recorded for each frame by the signal from the latch counter 10, and the signal is delayed by one frame period and sent to the synchronization bit determination circuit 301. The synchronous bit determination circuit 30 compares the stored data from the latch 20 with new data having the same phase, and determines whether the latched data is likely to be a synchronous bit or not. Counter 1 is activated by the output of the synchronization bit determination circuit 30, and when the number of times it is determined that the bit is not a synchronization bit exceeds a certain value, the out-of-synchronization mode 3 is set, and frame synchronization counter 1 is activated.
Shifts the phase of 0 by 1 bit in a certain direction. If not, continue in synchronous mode. The counter 1 is constituted by, for example, a reversible (up/down) counter, and if the judgment circuit 30 judges that it is a synchronous bit, it adds 11 if 3, otherwise adds 1, and the counted value becomes a constant value (
For example, when the condition is 0) or less, the out-of-synchronization mode is set. Such a synchronous circuit requires less memory capacity, but 1
Since only one bit is determined for each frame, if synchronization occurs, synchronization will not be restored unless the number of frames equal to the length of four frames is examined in the worst case. In a synchronous digital transmission network, loss of synchronization can affect the entire system, so recovery is required as quickly as possible. Second
The figure shows an embodiment of a frame synchronization circuit according to the present invention.

The frame synchronization counter 10, as in FIG. 1, is a counter that divides the frequency of the clock into the frame length, and ultimately generates a synchronization output and sends it to the output terminal 300'. All the data of one frame except the data input from the data input terminal 100 is stored in the storage circuit 20', and the synchronous bit judgment circuit 30' determines whether the bits of the same phase one frame before satisfy the synchronous bit condition for each bit. It will be judged. The evaluation score for each bit is stored in the additional storage circuit 21, and the score is increased or decreased for each bit by the update circuit 11' according to the output of the synchronous bit determination circuit 30'.
1 bit by bit. The output of the update circuit 11' is also applied to the score evaluation circuit 40' at the same time, and the output of the frame synchronization counter 10 indicates that the evaluation score of bits that are considered to be synchronous bits is lower than a certain value, that is, synchronous bits have been detected for a certain number of frames in the past. If it is determined that the frame synchronization counter 10 is not the same, the out-of-synchronization mode is entered, and the initial value generation circuit 50 operates when a bit whose evaluation score exceeds a certain number of points is generated among the outputs of the score evaluation circuit 40, and the initialization of the frame synchronization counter 10 is performed. By setting it to a value, it becomes synchronous mode. Therefore, according to the configuration shown in FIG. 2, it takes only one frame from entering the out-of-synchronization mode to recovering synchronization. In reality, the time from when it goes out of sync until it enters out-of-sync mode,
That is, several frames are required until the evaluation score of the bit considered as a synchronization bit falls below a certain value, but this time is the same in the conventional configuration, that is, in FIG. Additionally, it is possible to raise the lower limit of evaluation points in order to shorten the time from when synchronization is lost until entering synchronization-out mode, but if a code error occurs in the synchronization bit, even though synchronization has not been lost, Since accidents such as entering the out-of-synchronization mode are likely to occur, resulting in instability, the lower limit of the evaluation score is determined in consideration of the bit error rate. In FIG. 2, the frame synchronization counter 0 and the initial value generation circuit 50 realize a counter circuit that can instantaneously change to any phase. The update circuit 11' can be easily realized by the configuration shown in FIG.

The output of the synchronization bit determination circuit 30' is led from a terminal 140 to control the constant switch 12 to select either a positive constant 14 or a negative constant 15, and sends it to one input of an adder 13.
The output of the additional storage circuit 21, that is, the evaluation score, is applied to the other input of the adder 13 from a terminal 150 and updated. The updated output is sent from the terminal 151 to the additional storage circuit 21 and the score evaluation circuit 40. In FIG. 2, it is assumed that the synchronization bit is one bit, but in other cases, that is, when multiple bits are used (for example, a synchronization character), the synchronization bit determination circuit 30' is configured as shown in FIG. This can be achieved by doing this.

In FIG. 4, the terminal Z160 is connected to the data input terminal 100, and the signal is transmitted to the serial input-parallel output shift register 3.
2 and shifted to the right at every bit synchronization. The data at each stage of the shift register output is led to an exclusive sum circuit and judged bit by bit against the output Z of the synchronization character generation circuit 33. The output of each exclusive OR circuit is led to a detection circuit 31, which detects whether all bits match the synchronization character. Since the detection circuit 31 only needs to detect that all inputs are zero, it can be easily realized with a NOR circuit. The output of the 2-detection circuit 31 is sent from a terminal 140 to the update circuit 11' every bit synchronization.

Since the memory circuit 20' sequentially stores and writes data into a memory of a predetermined length, it is not necessarily a random access memory (RAM) but can be realized by a shift register.

Furthermore, the evaluation score given by the update circuit 11' can be achieved by adding, for example, 10Q when it seems to be a synchronous bit, and -8 when it is not, but in this case Q and 8 do not necessarily have to be integers, so the update circuit Reference numeral 11' may be an analog integrator, the additional storage circuit 21 may be an analog register, and the score evaluation circuit 40 may be an analog comparator. In order to know whether the synchronization bit conditions have been satisfied over the past several frames, an additional storage circuit for storing evaluation points is also configured to have one frame's worth of bits, so that synchronization can be recovered in the event of loss of synchronization.

Compared to the example of the conventional frame synchronization circuit described above, the frame synchronization circuit according to the present invention requires only one frame to recover synchronization, so the speed can be increased by twice the number of frame configuration bits, that is, eight times faster than before. .

[Brief explanation of drawings]

FIG. 1 shows an example of a conventional frame synchronization circuit, FIG. 2 shows an embodiment of the present invention, FIG. 3 shows an example of the update circuit 11' in FIG. 2, and FIG. An example of the configuration of a synchronous bit determination circuit when using a synchronous bit (synchronous character) is shown. Loo... ...Data input terminal, 200...
・Clock input terminal, 300... Synchronization output terminal, 10... Frame synchronization counter, 20... Memory circuit, 21... Additional memory circuit, 30, 30'
...Synchronization bit determination circuit, 11...Reversible counter, 11'...Update circuit, 40...
・Score evaluation circuit, 50...Initial value generation circuit. Inferior figure 1 figure 2 younger brother figure 3 lineage 4 figure

Claims (1)

[Claims] 1. A first storage circuit capable of storing all bits constituting one frame, a synchronization bit determination circuit, a phase-variable frame synchronization counter, and an update circuit that increases or decreases the evaluation score based on the output of the synchronization bit determination circuit. , a second memory circuit having a capacity to store evaluation scores for all frame constituent bits, and the synchronization bit determination circuit distinguishes received data from one frame previous data supplied from the first memory circuit. is determined for each bit, and based on the determination result, the evaluation score for each bit stored in the additional storage circuit is updated in the update circuit, and the phase of the frame synchronization counter is controlled by the output of the update circuit. A frame synchronization circuit characterized by: