JPH0614640B2 - Frame synchronization circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a frame synchronization circuit, and more particularly to a frame synchronization circuit capable of preventing pseudo frame synchronization on the receiving station side of a digital wireless transmission line.

(Prior Art) Conventionally, in a frame synchronizing circuit provided on the receiving side of a digital radio transmission line, as an example, as shown in the main part of FIG. 1, data input from terminals 51 and 52, respectively. Corresponding to the signal (1) 101 and the data signal (2) 102, a frame pattern comparison circuit 3 composed of exclusive OR circuits 1 and 2 is provided, which is input from the frame pattern timing signal generation circuit 6. The frame synchronization pattern (1) 105 and the frame synchronization pattern (2) 106 are compared and collated,
In the state where the frame is synchronized, for example, the data signal (1 ′) 103 and the data signal (2 ′) output from the exclusive OR circuits 1 and 2 and input to the frame / pattern matching / mismatch detecting circuit 4. In the frame 104, the time slot corresponding to each frame synchronization bit becomes the “L” level, and a predetermined timing pulse corresponding to the frame synchronization sent from the frame pattern timing signal generation circuit 6 The pattern match / mismatch detection circuit 4 outputs a level signal 110 of “H” level. This “H” level signal 110 is sent to the prohibiting circuit 5, and the clock signal 107 input through the terminal 53 passes through the prohibiting circuit 5 and becomes a clock pattern 108 as a frame pattern.
It is sent to the timing signal generation circuit 6. Of course, in the frame asynchronous state, the level signal 110 becomes "L" level, the clock signal 107 is cut off by the prohibiting circuit 5, and is not sent to the frame pattern timing signal generating circuit 6. In the frame synchronization state, the frame pattern timing signal generating circuit 6 outputs the frame synchronization pattern (1) 105 and the frame synchronization pattern (2) 106 from the frame pattern timing signal generation circuit 6 through the clock signal 108 described above. Data signal
(1) 101 and data signal (2) 102 are output in a form corresponding to and input to the frame / pattern comparison circuit 3.
Frame pattern comparison circuit 3 during frame synchronization
The data signal output of is as described above.

In this conventional frame synchronization circuit, for example, the data signal (1) 101 and the data signal (2) 102 are shown in FIG.
When represented by a time-series signal as shown in (a), when the normal frame synchronization is established, it is clearly shown in FIG.
Corresponding to the data signal (1) and data signal (2) of (a),
Data signal (1) and data signal shown in FIG. 3 (b)
It is synchronized in the state of (2). However, in the conventional frame synchronization circuit, as shown in FIG. 3 (c), the data signal (1) and the data signal of FIG. 3 (a) are
When the pseudo pull-in occurs in the state of bit delay with respect to (2), it is difficult to leave the pseudo pull-in, which is a great obstacle to establishment of normal frame synchronization. As a countermeasure against this, it is necessary to set a frame synchronization pattern configuration such that the frame synchronization patterns do not match each other at any frame synchronization interval, but it is difficult to select such a frame synchronization pattern. In particular, when the line route is identified based on the difference in the frame synchronization patterns, a number of types of frame synchronization patterns are inevitably necessary. Choosing a sync pattern configuration is an even more difficult situation. That is, the conventional frame synchronization circuit has a drawback that the establishment of normal frame synchronization is significantly hindered by the pseudo pull-in.

(Object of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks, determine a pseudo pull-in state by using a parity bit included in a data signal sequence, and establish frame synchronization through a re-frame search. The purpose of the present invention is to provide a frame synchronization circuit that eliminates a frame synchronization failure due to pseudo pull-in.

(Structure of the Invention) The frame synchronization circuit of the present invention is a frame synchronization circuit provided on the receiving station side of a digital radio transmission line. Circuit, a data signal sequence corresponding to the phase comparison result output from the frame pattern comparison circuit, and a predetermined timing pulse are input, and the frame synchronization pattern and the reception side frame synchronization pattern in the input data signal sequence are input. A frame / pattern match / mismatch detection circuit that detects a phase match / mismatch between the input data signal sequence and a phase level match / mismatch detection circuit that outputs a first level signal indicating the match or mismatch. When the specified parity bits included in the column are compared and collated and they do not match, The parity alarm is generated with reference to the generated parity alarm and the first level signal, when the first level signal indicates a mismatch, and also when the first level signal indicates a match. A parity match / mismatch detection circuit that forcibly determines that the frame is out of synchronization and outputs a second level signal indicating frame synchronization or non-synchronization according to the result of the determination, When the first level signal, the second level signal, and a predetermined clock signal are input, the first level signal indicates coincidence, and the second level signal indicates frame synchronization. Is sent from the clock inhibit circuit, which outputs the clock signal, and inhibits the output of the clock signal otherwise. In response to a clock signal input, a frame generating and outputting the reception side frame synchronization pattern and the timing pulse
And a pattern timing signal generation circuit.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing the main part of one embodiment of the present invention. As shown in the figure, in the present embodiment, a frame pattern comparison circuit 9 including exclusive OR circuits 7 and 8, a parity counting circuit 10, a frame pattern matching / mismatch detecting circuit 11, and a parity matching / circuit. A discrepancy detection circuit 12, a parity bit selection circuit 13, a clock inhibition circuit 17 including an inhibition control circuit 14 and an inhibition circuit 15, and a frame pattern timing signal generation circuit 16 are provided.

In FIG. 2, two series of data signal (1) 111 and data signal (2) 1 input via terminals 54 and 55 are shown.
The frame pattern comparison circuit 9 compares the phase of the data 12 with the frame synchronization pattern (1) 115 and the frame synchronization pattern (2) 116 sent from the frame pattern timing signal generation circuit 16 in a corresponding manner. The operation contents output as the data signal (1 ′) 113 and the data signal (2 ′) 114 are the same as those in the above-mentioned conventional example. For the data signal (1) 111 and the data signal (2) 112 shown in FIG. 4 (a),
Frame synchronization pattern (1) 1 as shown in FIG. 4 (b)
15 and the frame synchronization pattern (2) 116 correspond to each other in time phase, and when there is no error in the frame pulse in the wireless line section, the frame pattern is transmitted through the operation of the exclusive OR circuits 7 and 8. The frame synchronization bit (FIG. 4 (a)) of the data signal (1 ') 113 and the data signal (2') 114 output from the comparison circuit 9
, Designated as F ₁ and F ₂ , respectively)
Both the time slots corresponding to "1" are at the "L" level. Such a state corresponds to a state in which frame synchronization is established. In the frame pattern matching / non-matching circuit 11, via the timing pulse 119 sent from the frame pattern timing signal generating circuit 16 and corresponding to the frame sync bit as shown in FIG. 4 (c). , The number of time slots corresponding to the synchronization bits F ₁ and F ₂ of the data signal (1) 111 and the data signal (2) 112 are counted. In the case of the data signal (1) 111 and the data signal (2) 112 shown in FIG. 4 (a), the time slot corresponding to the frame synchronization bit is detected every 202 bits and corresponds to the frame synchronization bit. When the count value of the matching pulse of the time slot reaches a predetermined value set in advance, it is determined that the frame synchronization is established, and the level signal 122 output from the frame pattern matching / mismatch detecting circuit 11 is It is sent to the parity match / mismatch detection circuit 12 and the inhibition control circuit 14 in the state of “H” level. Needless to say, in the state where the frame synchronization is not established, the level signal 122 is output in the "L" level state and sent to each of the circuits described above.

In the parity counting circuit 10, the data signal (1 ′) 113 sent from the frame pattern comparison circuit 9
And the parity counting operation is performed in response to the input of the data signal (2 ′) 114, and the parity counting value 121 is output. The parity count value 121 is sent to the parity match / mismatch detection circuit 12. For the parity match / mismatch detection circuit 12, together with the parity count value 121, the parity bit 123 sent from the parity bit selection circuit 13 and the frame pattern match
Level signal 122 sent from the mismatch detection circuit 11
And have been entered. In the parity bit 123, the parity bit obtained through the parity counting operation on the transmission side included in the data signal (1 ′) 113 in the parity bit selection circuit 13 is the frame bit.
Parity bit selection signal sent from the pattern timing signal generation circuit 16 (shown in FIG. 4 (d))
It is extracted in the selected form via 120.

In the parity match / mismatch detection circuit 12, the parity count value 121 sent from the parity count circuit 10 is sent.
And the parity bit 123 sent from the parity bit selection circuit 13 are compared and collated, and mutual matching / mismatching is detected, and a predetermined parity / corresponding to the mismatching is detected.
An alarm is generated. This parity alarm is counted through a parity counting operation using a relatively high bit error rate as a threshold value, and when the count value reaches a predetermined predetermined value in a state where frame synchronization is established, Outputs predetermined information indicating that the frame is out of synchronization. Considering the case where the pseudo pull-in occurs in the frame synchronization circuit, first, from the frame / pattern match / mismatch detection circuit 11, the "H" level signal 1 corresponding to the pseudo frame synchronization caused by the pseudo pull-in is generated.
22 is output, and the parity match / mismatch detection circuit 12 is output.
Entered in. In this state, the parity measurement value 121 and the parity bit 123 are compared and collated as described above, but since they are in the pseudo pull-in state, inconsistency is necessarily detected between them, and the parity・ An alarm is generated. Needless to say, the occurrence of this parity alarm also occurs when frame synchronization is normally established and an error occurs in the frame pulse in the wireless link section, but the occurrence rate is the parity bit error rate. In general, the parity bit error rate at the time of out-of-frame synchronization is maintained at a considerably low value. Therefore, the parity alarm is counted with a predetermined occurrence rate exceeding the parity bit error rate as a threshold, and the already established frame synchronization is determined to be normal frame synchronization depending on the counted value. It is clear that it is possible to determine whether there is or abnormal frame synchronization due to pseudo pull-in.

As described above, when the count value of the parity alarm reaches a predetermined value, the level signal 122 sent to the parity match / mismatch detection circuit 12 is sent.
However, in response to the pseudo pull-in, the level signal 124 from the parity match / mismatch circuit 12 does not match the parity measurement value 121 and the parity bit 123 due to the pseudo pull-in. Therefore, the inhibition control circuit 1 outputs the signal at the “L” level.
4 is sent. On the other hand, the prohibition control circuit 1
4, the level signal 122 output from the frame / pattern match / mismatch detection circuit 11 is also sent. As described above, the level signal 122 corresponds to the pseudo pull-in. It is input in the state of "H" level corresponding to the establishment of synchronization. Needless to say, the fact that the level signal 122 is at "H" level in this state means that the frame synchronization is in an abnormal frame synchronization state due to pseudo pull-in.

The prohibition control circuit 14 described above, when the level signal 122 is input at the “H” level and the level signal 124 is input at the “L” level, corresponds to the abnormal frame synchronization due to the pseudo pull-in. The prohibition control signal 125 is output in the state of “L” level via the logic circuit and is input to the prohibition circuit 15. The prohibition control circuit 14 receives the level signal 122 output from the frame / pattern match / mismatch detection circuit 11 and the level signal 124 output from the parity match / mismatch detection circuit 12, and receives the level signal 122. Is always at the "L" level, the inhibit control signal 125 at the "L" level is always output, and when the level signal 122 is at the "H" level, the level signal 124 is at the "H" level. The "H" level inhibit control signal 125 is output, and when the level signal 124 is "L" level, the "L" level inhibit control signal 125 is output.

In the prohibition circuit 15, the clock signal 117 input through the terminal 56 is output as the clock signal 118 to the frame pattern timing signal generation circuit 16 when the prohibition control signal 125 is at "H" level. However, when the prohibition control signal 125 is at "L" level, the clock signal 117 is cut off in the prohibition circuit 15 and is not output. Therefore, the level signal 122 is at the “H” level and the level signal 1 corresponds to the pseudo synchronization.
When 24 is in the "L" level state and the prohibition control signal 125 output from the prohibition control circuit 14 is in the "L" level state, the clock signal 117 is cut off in the prohibition circuit 15 as described above, and thus the frame ·pattern·
The clock signal sent to the timing signal generation circuit 16 is stopped. As a result, the frame pattern timing signal generation circuit 16 outputs the frame
Frame synchronization pattern 1 sent to the pattern comparison circuit 9
15 and 116, and the timing pulse 119 sent to the frame pattern match / mismatch detection circuit 11 is also stopped, and the pseudo frame synchronization state by the pseudo pull-in is released. That is, the frame synchronization search state is restored again. In this state, two series of data signals (1) 1 input via terminals 54 and 55
The operation at the time of frame synchronization search for No. 11 and data (2) 112 is as described at the beginning of the operation description of this embodiment.

When the normal frame synchronization is established through the above process, the level signal 122 and the level signal 124 are both in the "H" level state, so that the prohibition control signal 125 output from the prohibition circuit 14 is also "H". It is input to the prohibition circuit 15 as a level signal of the level. Prohibition circuit 15
Operates so as to output the clock signal 117 as it is as the clock signal 118 without interrupting it when the prohibition control signal is at the "H" level. Therefore, the clock signal 118 is the frame pattern timing signal. It is sent to the generation circuit 16 and the above normal frame synchronization state is maintained.

(Effect of the Invention) As described in detail above, according to the present invention, the parity bit included in the input data signal sequence is used to determine the abnormal frame synchronization state due to the pseudo pull-in and cancel the abnormal frame synchronization state. By promptly restarting the re-frame synchronization search, the frame synchronization failure due to the pseudo pull-in can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an essential part of an example of a conventional frame synchronization circuit, FIG. 2 is a block diagram showing an essential part of an embodiment of the present invention, and FIGS. 3 (a), 3 (b) and (c) is an explanatory diagram of a frame of the input data signal, and FIGS. 4 (a), (b), (c) and (d).
[Fig. 6] is a signal waveform diagram for explaining operation. In the figure, 1, 2, 7, 8 ... Exclusive OR circuit,
3, 9 ... Frame pattern comparison circuit, 4, 11 ...
Frame / pattern match / mismatch detection circuit, 5, 15 ...
... Inhibition circuit, 6, 16 ... Frame pattern timing signal generation circuit, 10 ... Parity counting circuit, 12 ...
... parity match / mismatch detection circuit, 13 ... parity
Bit detection circuit, 14 ... Inhibition control circuit, 17 ... Clock inhibition circuit.

Claims (1)

[Claims] 1. A frame synchronizing circuit provided on the receiving station side of a digital radio transmission line, comprising: a frame pattern comparing circuit for phase comparison between a predetermined receiving side frame synchronizing pattern and an input data signal sequence; and the frame pattern comparing circuit. A data signal sequence corresponding to the phase comparison result output from the circuit and a predetermined timing pulse are input to match the phase between the frame synchronization pattern and the reception side frame synchronization pattern in the input data signal sequence. A frame pattern match / mismatch detection circuit that detects a mismatch and outputs a first level signal indicating a match or mismatch, a parity count value for the input data signal sequence, and a predetermined parity included in the input data signal sequence. A parity alarm generated when the bits are compared and collated and they do not match With reference to the first level signal, the count value of the parity alarm exceeds a predetermined value even when the first level signal indicates disagreement and also when the first level signal indicates coincidence. In the state, it is forcibly determined to be out of frame synchronization, and a parity match / mismatch detection circuit that outputs a second level signal indicating frame synchronization or asynchronousness according to the determination result; the first level signal; When the second level signal and a predetermined clock signal are input, the first level signal indicates coincidence, and the second level signal indicates frame synchronization, the clock signal is output. , Otherwise, in response to a clock inhibit circuit that inhibits the output of the clock signal and a clock signal input sent from the clock inhibit circuit, A frame synchronization pattern for the receiving side and a frame for generating and outputting the timing pulse
A pattern timing signal generation circuit, and a frame synchronization circuit comprising: