JP2677331B2 - Frame synchronization protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization protection circuit which protects the synchronization of received frames in a device which periodically transmits and receives data.

[0002]

2. Description of the Related Art In a device that periodically transmits and receives data,
The frame word may not be detected due to bit error or other causes, resulting in loss of synchronization. Once out of sync, all burst information during that time will be lost until a frame word is found again and frame sync is established.Therefore, if the frame word cannot be detected, it will not immediately go out of sync. A protection circuit is provided.

FIG. 3 is a block diagram showing a configuration example of a conventional frame synchronization protection circuit. In the figure, a frame word detection circuit 30 composed of a shift register 31 and a comparator 32 compares the received signal with the frame word data to detect a match / mismatch. The match output is O
It is input to the K counter 33 and the number of times of frame word detection is counted. The disagreement output is input to the NG counter 34, and the number of times that the frame word cannot be detected is counted. The OK counter 33 and the NG counter 34 each output a reset signal when the count value reaches a predetermined value, and the OK counter 33 and the N counter 34 pass through the OR gate 35.
Input to the reset terminal of the G counter 34. Therefore, when at least one of the OK counter 33 and the NG counter 34 reaches a predetermined value, both counters are reset. Further, the reset signal of the NG counter 34 is input to the reset terminal R of the flip-flop 36 which sets the synchronous / asynchronous mode.

The carry output FK of the m-ary frame counter 37 is output as a frame signal and is OK.
It is input to the clock terminals of the counter 33 and the NG counter 34 (m is a frame period). Therefore, the OK counter 33 and the NG counter 34 count the number of detected and non-detected frame words at the original frame position. The coincidence output of the comparator 32 and the output of the flip-flop 35 which is inverted via the inverter 38 are input to the AND gate 39, and the logical product output thereof is m.
It is connected to the reset terminal of the advance frame counter 37 and to the set terminal S of the flip-flop 36.

Therefore, when the flip-flop 36 is in the reset state (out of synchronization) and its output is "0", the coincidence output of the comparator 32 is the m-ary frame counter 3
7 is used as a sync reset signal to establish frame synchronization. Further, this reset signal is also used as a synchronous set signal of the flip-flop 36, and thereafter the frame synchronization state is set, and the m-ary frame counter 37 outputs the frame signal synchronized with the frame cycle m until the NG counter 34 outputs the reset signal. Output.

The shift register 31 and the m-ary frame counter 37 operate with a basic clock supplied from the system. With such a configuration, when the count value of the NG counter 34 reaches a predetermined value (the number of synchronization protection stages), it is considered that the synchronization is lost, and the frame word is searched bit by bit at another position. When the frame word is found there, the m-ary frame counter 37 is reset and the flip-flop 36 is set to resynchronize. That is, the conventional frame synchronization protection circuit is
When the frame word disagreement is detected a predetermined number of times at the original position, the frame word search is started at another position.

[0007]

By the way, the basic clock of the system does not follow the phase of the received signal, but
If it is supplied from another system such as a subscriber side station device, it is necessary to re-latch the received signal at the phase of the clock. However, the phase of the received signal changes due to the delay fluctuation (wander) due to the temperature change of the transmission line,
In high-speed signals, bit-wise phase jumps may occur. Such a temperature change occurs in a long cycle of one day or one year, and since the conventional frame synchronization protection circuit far exceeds the number of synchronization protection stages, it is unavoidable that the synchronization is lost.

Further, the transmission line may be switched during communication for maintenance or operation of the transmission line. However, since the delay amount is different due to the difference in the length of the transmission line before and after the switching, the frame phase shifts. . Especially when there is a period in which data is not sent as in the time division directional control transmission method,
When switching the transmission path using this period, the conventional frame synchronization protection circuit loses synchronization each time,
I was supposed to lose a lot of data.

It is an object of the present invention to provide a frame synchronization protection circuit capable of keeping a synchronization state by following changes in the phase of a received frame without increasing the number of synchronization protection stages.

[0010]

SUMMARY OF THE INVENTION The present invention is directed to frame synchronization.
In this state, when the frame word is not detected a predetermined number of times in the frame phase, it is regarded as out of synchronization, the frame word is searched for in another phase, and the phase of the frame signal is matched with the detected phase to establish frame synchronization. When the frame sync protection circuit is in the frame sync state,
± n of frame word (n is
Means for detecting phase shift of 1 or more integers)
And when a phase shift of ± n bits or less is detected,
Change the phase of the frame signal according to the amount of phase shift of
And means for

[0011]

According to the present invention, the detection range of the frame word in the synchronous state is expanded from the original position to the position of ± n bits, and if the frame word is detected within that range, the phase is pulled in to detect the reception frame phase. By performing fine adjustment, the synchronization state can be maintained as it is.
That is, if the phase variation is ± n bits or less, the synchronization loss can be avoided by adapting the received frame phase.

It should be noted that when a frame in which a frame word cannot be detected within ± n bits is received a predetermined number of times, it is regarded as out of synchronization, so that the search for the frame word can be started within a range of ± (n + 1) bits or more. it can.

[0013]

1 is a block diagram showing the configuration of an embodiment of a frame synchronization protection circuit of the present invention.

In the figure, a frame word detection circuit 30, O composed of a shift register 31 and a comparator 32.
K counter 33, NG counter 34, OR gate 35,
The flip-flop 36, the m-ary frame counter 37, the inverter 38, and the AND gate 39 are arranged similarly to the conventional configuration shown in FIG.

The feature of the present invention resides in that in the present embodiment, comparison is performed by outputting "1" when the value of the m-ary frame counter 37 is (m-n-1) or more and (n-1) or less. AND gate 12, which ANDs the output of comparator 11, the output of flip-flop 36, and the coincidence output of comparator 32, and the logical sum of the outputs of AND gates 12 and 39. 37, and an OR gate 13 for inputting to a reset terminal of 37.

Here, when the output of the flip-flop 36 is "0" (out of synchronization), the coincident output of the comparator 32 via the AND gate 39 is the m-ary frame counter 3
7 is used as a synchronous reset signal, and is also used as a synchronous set signal of the flip-flop 36 to establish frame synchronization.

On the other hand, when the output of the flip-flop 36 is "1" (at the time of synchronization), the logical product of the coincidence output of the comparator 32 and the output of the comparator 11 via the AND gate 12 is the m-ary frame counter. It is used as a synchronous reset signal of 37.

In the synchronous state, the output of the flip-flop 36 is "1", and at this time, the m-ary frame counter 37
The values of (mn-1), (mn), ..., (m-1),
When the coincidence output of the comparator 32 becomes "1" during the period of 0, 1, ..., (n-1), the m-ary frame counter 37 is reset at that position. That is, the phase of the frame signal is finely adjusted according to the received frame phase, unlike the conventional configuration, even during synchronization.

Therefore, even if the received frame phase is gradually shifted, if the phase fluctuation is ± n bits or less, the m-ary frame counter 37 is reset so as to match the frame phase with the detection position of the frame word,
Since counting up of the NG counter 34 is prohibited,
The synchronization state can be maintained regardless of the number of synchronization protection stages.

However, if a frame in which a frame word cannot be detected continues within a predetermined number of times within ± n bits, the flip-flop 36 is reset by the output of the NG counter 34. Start the bitwise frame word search at.

The state transition of the circuit of the present invention described above is shown in FIG. In this way, the frame synchronization protection circuit of the present invention can change the frame phase by synchronizing with the received frame phase each time, even if a phase jump within ± n bits occurs in the received signal.

[0022]

As described above, according to the present invention, ± bit
Adjust the phase of the frame signal for the following phase shift,
The synchronization state can be maintained. Therefore, even if there is a phase jump of the received signal due to temperature fluctuations, etc., if the phase shift is ± n bits or less, it can be automatically absorbed and out of synchronization can be avoided, thus minimizing errors. Can be suppressed to In particular, even when there is a data transmission suspension period as in the time division directional control transmission method, it becomes possible to maintain the synchronization state regardless of the number of synchronization protection stages, and the effect is extremely large.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a frame synchronization protection circuit of the present invention.

FIG. 2 is a diagram showing a state transition state of the circuit of the present invention.

FIG. 3 is a block diagram showing a configuration example of a conventional frame synchronization protection circuit.

[Explanation of symbols]

 11 comparator 12 AND gate 13 OR gate 30 frame word detection circuit 31 shift register 32 comparator 33 OK counter 34 NG counter 35 OR gate 36 flip-flop 37 m-ary frame counter 38 inverter 39 AND gate

Claims (1)

(57) [Claims] 1. When a frame word is not detected a predetermined number of times in a predetermined frame phase in the frame synchronization state, it is considered to be out of synchronization, a frame word is searched for in another phase, and a frame signal is detected in the detected phase. In the frame synchronization protection circuit that synchronizes the phases of the frames to synchronize the predetermined frame
± n of the frame word with respect to the phase (n is 1 or more)
(Integer) bits or less means for detecting a phase shift, and when a phase shift of ± n bits or less is detected,
The phase of the frame signal according to the amount of phase shift of
Frame synchronization protection circuit is characterized in that a means for further.