KR100370948B1 - Framing Processing Unit in Synchronous Digital Threshold Transmission - Google Patents

Abstract

The framing processing apparatus of the synchronous transmission device of the present invention includes a frame detector which outputs the presence or absence of the detection of the frame word value in the frame data having the STM-N structure, and if the frame word value detection time coincides with the one frame count completion time, An in-frame detection unit for declaring that the frame is not detected and the frame word value is not detected for several frames in the in-frame declaration state, the out-of-frame is declared, the in-frame declaration is released, and the 1 frame count is restarted at another position of the frame. An out-of-frame detection unit for finding a frameword value and a loss-of-frame if the out-of-frame state persists for several tens of frames, and a loss-of-frame declaration if the in-frame state persists for the tens of frames in the loss-of-frame declaration state. It consists of a loss-of-frame detection unit for releasing. The present invention is used in a synchronous transmission device.

Description

Framing processing device in synchronous digital controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous digital hierarchy (hereinafter referred to as " SDH ") transmission apparatus, and more particularly, to an apparatus for framing processing.

In general, synchronous transmission is used for PCM (Pulse Code Modulation) transmission and refers to a form in which information transmission is performed while keeping clocks synchronized between transmitting and receiving stations regardless of transmission information. If the transceiver uses an independent clock, the accuracy of the clock source is limited within a certain range to ensure transmission quality. This type of information may be used regardless of the type of circuit and is usually used to transmit information using a frame or a cell in a periodic or aperiodic period. Types of synchronization used for synchronous transmission can be divided into frame synchronization and digit synchronization. The frame synchronization is a synchronization method in which a channel is connected to a transmission line and moves to the next operation to match the start and end of one frame. The digit synchronous is a synchronization method for synchronizing the clock generator, which is a control pulse source of, for example, 1.544 MHz, necessary for one transmitter and receiver encoders, at the transmitter and receiver.

The SDH transmitter having a STM-N (Synchronous Transport Module level N) frame structure has a frame synchronization scheme. Therefore, for frame synchronization, a frame alignment word (abbreviated as "frame word") must be found. In order to process the frameword in the existing STM-N frame, a large number of logics are used. In addition, it is desirable to implement a device with a small number of logics and improved efficiency.

Accordingly, an object of the present invention is to provide an apparatus for finding an efficient and effective frameword in an SDH transmission apparatus having an STM-N frame structure.

Another object of the present invention is to provide an apparatus for accurately grasping the current frame state in the SDH transmission apparatus having the STM-N frame structure and providing the result information.

In accordance with the above object, the present invention provides a synchronous transmission apparatus, comprising: a frame detector for outputting a frameword value detected in frame data having an STM-N structure, and the frameword value detection time is one frame count completion time; If it is equal to the in-frame detection unit for declaring the in-frame, and if the frame word value is not detected for several frames in the in-frame declaration state, the out-of-frame is declared and the in-frame declaration is released, and the frame count is restarted by the first frame count. An out-of-frame detection unit for finding a frameword value at another position of the frame, and if an out-of-frame state persists for several tens of frames, a loss-of-frame is declared. A loss-of-frame detection unit that releases the loss-of-frame declaration Characterized in that.

1 is an exemplary configuration diagram of a framing processing apparatus according to an embodiment of the present invention;

FIG. 2 is a block diagram illustrating a concrete block of the loss-of-frame detecting unit 34 of FIG. 1;

3 is a structural diagram of an STM-4 frame applied as an embodiment of the present invention;

4 is an operation waveform diagram illustrating a case in which the framing processing apparatus of FIG. 1 declares an in-frame;

5 is an operation waveform diagram illustrating a case in which the frame processing apparatus of FIG. 1 declares an out of frame;

6 is a view illustrating a process of declaring an in-frame state, an out-of-frame state, a loss-of-frame state, and a process of deviating from the loss-of-frame state according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same elements in the figures are denoted by the same numerals wherever possible. In addition, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

In the embodiment of the present invention to be described below, an example of the STM-N frame structure will be described as STM-4.

The framing processing apparatus of the STM-4 frame structure according to the embodiment of the present invention is shown in FIG. 1, DT and CLK are input signals. The DT is data having an STM-4 frame structure, and the CLK is a system clock. The output signals include an in frame signal INF, an out of frame signal 00F, and a loss of frame signal LOF. The in-frame signal INF is a signal indicating whether or not input frame data is synchronized. In-frame signal INF indicates a logical "high" state value. The out-of-frame signal 00F is declared an out-of-frame when a frame is missed a predetermined number of times, for example, four times in an in-frame state. The out of frame signal 00F at the time of out of frame is a logic "high" state. The loss-of-frame signal LOF has a logic state that declares a loss-of-frame when the out-of-frame state is repeated up to 24 times, for example, and has a logic state that is out of the loss of frame when the in-frame state is repeated up to 24 times, for example. When declared as a loss-of-frame, the logic state of the loss-of-frame signal LOF is logic "high", and when out of the loss-of-frame state, the logic state of the loss-of-frame signal LOF is logic "low". In the initial state, the inframe signal INF maintains a logic "low" state, and the out of frame signal 00F and the loss of frame signal LOF maintain a logic "high" state.

1, the framing processing unit according to the embodiment of the present invention includes a frame detector 2, a set / reset circuit 4, 14, 32, a ternary counter 12, a 9720 binary counter 26, a loss-of-frame detection unit 34, and a plurality of Logic gates 6,8,10,16,18,20,22,24,28. According to the structure of the framing processing unit, five blocks (frame detector 2, set / reset circuit 4, 14, 32, ternary counter 12, 9720 binary counter 26, loss-of-frame presence detector 34) and simple logic associated with the block are shown. It can be seen that it is composed of gates (logical gates 6, 8, 10, 16, 18, 20, 22, 24, 28).

FIG. 2 is a detailed block diagram of the loss-of-frame detection unit 34 of FIG. 1 and includes a plurality of logic gates 36, 37, 38, 39, 41, a binary counter 40, 42, and a set / reset circuit 44. do. The input source of the AND gate 36 is a carry signal CARR output from the out of frame signal 00F and the 9720 binary counter 26. The output of the AND gate 36 is provided to the enable end of the binary counter 40. An input source of the exclusive NOR gate 38 is the frame detection signal FEN output from the carry signal CARR and the frame detection unit 2. FIG. The output of the exclusive noar gate 38 is provided to an enable end of the binary counter 42. The out-of-frame signal 00F is applied to one input terminal of the AND gate 39 via the inverter 37, and the output of the exclusive no gate 38 is applied to the type force terminal of the AND gate 39. The output of the AND gate 39 is provided to the load end ld of the binary clock 42. The outputs of the binary counters 40 and 42 are provided to the set input terminal S and the reset input terminal R of the set / reset circuit 44, respectively. In addition, the output of the binary counter 42 is provided to the load end ld of the binary clock 40 through the inverter 41. 40 out of the 24 binary counters 40 and 42 is used for declaring a loss of frame, and 42 is used for declaring a loss of frame.

3 is an STM-4 frame structure diagram applied as an example of an embodiment of the present invention. The STM-4 frame has 9720 parallel data (1080 columns x 9 rows) in one frame. As an example, in the STM-4 frame, the signals of one row are composed of 12 parallel data, and the D _n signal is composed of 1044 parallel data. Unlike the other signals (A, B, etc.), the D _n signal may contain various data.

4 illustrates an operation waveform when the framing processing apparatus of FIG. 1 declares an in-frame.

First, an operation when a framing processing apparatus declares an inframe will be described with reference to FIGS. 1 and 4. In FIG. 1, when the frame data DT having the STM-4 structure as shown in FIG. 3 is received, the frame detector 2 searches for a frame word. Specifically, when the frame data DT having the STM-4 structure and the clock signal CLK are applied to the frame detector 2 of FIG. 1, the frame detector 2 has the signals A1 and A2 at the start position of the frame data DT, respectively, F6 (H). ), 28 (H) is checked. The A1 and A2 signals are defined as F6 (H) and 28 (H) in the ITU-T (International Telecommunications Union-Telecommunications standardization sector) recommendation, respectively, and correspond to framewords. When the signals A1 and A2 are set to F6 (H) and 28 (H), respectively, the frame detector 2 “high” pulses the frame enable signal FEN in the X-th frame as shown in FIG. 4. The pulse width is 77.76 MHz, which is one period of the clock signal CLK. The set / reset circuit 4 is set by the "high" pulse of the frame enable signal FEN to output a logic "high" state. In addition, the "high" pulse of the frame enable signal FEN is put into the logic "low" state by the inverter 22 and is applied to the oragate 24. The oragate 24 outputs a logic " high " state to the load terminal ld of the counter 26 by arranging a logic " low " state that is an output of the inverter 22 and a logic " high " state that is an output of the set / reset circuit 4. . The 9720 binary counter 26 performs the count up to 9720 in response to the clock signal CLK in the logic " high " state. When the count is completed, the carry signal CARR of the "high" pulse is output.

Since the 9720 binary counter 26 counts one frame section, the "high" pulse of the generated carry signal CARR is the "high" pulse of the frame enable signal FEN generated in the X + 1th frame and the timing of the generation thereof. Will be like this. The " high " pulse of the X + 1th frame enable signal FEN and the " high " pulse of the carry signal CARR are AND gated at the AND gate 28 so that the set stage S of the set / reset circuit 32 and the set / reset circuit 14 Is applied to the reset stage R of. In response to this, the set / reset circuit 32 transitions and outputs the in-frame signal INF in the "low" state, which was initially held, to the in-frame signal INF in the "high" state. The in-frame signal INF in the "high" state declares that it is in-frame. The set / reset circuit 14 is also reset by the logic " high " pulse applied to the reset stage R, and therefore outputs the out-of-frame signal 00F in the logic " low " state.

Therefore, it can be seen that the in-frame declaration according to the embodiment of the present invention is made when the frame words A1 and A2 are detected twice in the same position as shown in FIG. 4.

On the other hand, in the embodiment of the present invention, if the frame word is not detected four or more times consecutively at the same position, the out-of-frame declares and finds the frame words A1 and A2 at different positions.

Hereinafter, an operation of declaring an out of frame will be described in detail with reference to FIGS. 1 and 5. When the frame detection unit 2 of FIG. 1 fails to detect the frame words A1 and A2, the frame enable signal FEN is applied to the AND gate 8 in a logic " low " state and input to one input terminal of the OR gate 10. A logic " high " is applied to the 10 type force stage by a carry signal CARR of " high " Therefore, the output of oragate 10, which is applied to the enable end en of the quadrature counter 12 at the rear end, is a logic "high" state.

The quaternary counter 12 is initially in a logic "high" state indicating an out of frame, and transitions to a logic "low" state when a frameword is received at the same location for two frames. If no 4 consecutive framewords are found in the in-frame state, a logic "high" state is output. The operation of the quaternary counter 12 is further described as follows. The ternary counter 12 is enabled whenever a logic "high" state is applied from OA gate 10 (applied every frame), and then the frame enable signal FEN applied to the input terminal di is in a logic "low" state. Each time a count up is performed. Thus, counting up to four times outputs a logic " high " pulse as shown in FIG. The logic "high" pulse output of the quaternary counter 12 is applied to the set stage S of the set / reset circuit 14, so that the set / reset circuit 14 is out of logic "high" state as shown in FIG. Since frame signal 00F is generated, out-of-frame is declared. In the embodiment of the present invention, when the out-of-frame is declared, the frame words A1 and A2 are found at other positions.

When the out-of-frame signal 00F is in a logic "high" state, the output of the oragate 20 also becomes a logic "high" state and is applied to one input terminal of the AND gate 16. Since the output of the 9720 binary counter 26 is a logic "high" and the frame enable signal FEN is a logic "low" state, the output of the exclusive logic sum gate 18 is a logic "high", so the type force terminal of the AND gate 16 has a logic "high" state. Is approved. Therefore, the output of the AND gate 16 is in a logic "high" state, and the logic "high" state is applied to the reset terminal R of the set / reset circuit 4. As a result, the set / reset circuit 4 outputs a logic " low " state. The output of the ORA gate 24 becomes a logic "low" by the logic "low" state of the set / reset circuit 4 and the logic "low" state of the frame enable signal FEN. The 9720 binary counter 26 is cleared by the logic " low " state output of the oragate 24, and then continues counting by the clock signal CLK. In this case, the frame word detected by the frame detector 2 is not the values F6 (H) and 28 (H) in the A1 and A2 signals, but F6 (H) and 28 (H) in the other signals. That is, it means that the current frameword position is not where the framewords A1 and A2 are actually located. In this case, out-of-frames continue to occur, which causes the 5720 binary counter 26 to count after clearing the current count again. This operation finds the framewords A1 and A2 at different locations in the frame.

The loss-of-frame detection unit 34 logic the loss-of-frame signal LOF when the out-of-frame state, i.e., the out-of-frame signal 00F is maintained for 24 frames [3 msec = 1 frame (l25 µs) x 24] is maintained. Declares the loss of frame state by outputting it in "high" state. If the in-frame state is maintained for 24 frames (3 msec) in the loss-of-frame state, the frame is out of the loss-of-frame state.

The operation of the loss of frame detection unit 34 will be described in more detail with reference to FIG. 2. First, the operation in the case of declaring a loss of frame state will be described.

The 24-bit counter 42 outputs a "high" state every frame as the in-frame state persists, and the 24-degree county 40 is cleared by a "low" state signal that is then applied to the load end ld. The AND gate 36 outputs a "high" signal to the enable end of the binary counter 40 when an out-of-frame signal 00F of the "high" state is applied to the carry signal CARR of the "high" pulse from the 9720 binary counter 26. . The 24-bit counter 40 increments the count value by one in response to the clock signal CLK in the "high" signal state applied to the enable end en. Thus, counting up to 24 applies a logic " high " pulse to the set stage S of the set / reset circuit 44. Accordingly, the loss-of-frame signal LOF, which is the output of the set / reset circuit 44, outputs a logic "high" state.

Next, the operation in the case of moving out of the loss of frame state will be described.

Exclusive Noagate 38 sends the signal of the "high" state when the carry signal CARR of the "high" pulse and the frame enable signal FEN of the "high" state are applied from the 9720 binary counter 26. en) and the output of the type gate of the AND gate 39. Correspondingly, the binary counter 42 is enabled.

If the in-frame state continues, the out-of-frame signal 00F is maintained at the logic "low" state, so that the signal applied to the one input terminal of the AND gate 39 through the inverter 37 becomes the logic "high" state, so that the AND gate 39 is The signal of the "high" state is applied to the rod end ld. When the "high" state is applied to the rod end ld, the binary clock 42 is not cleared. However, if it goes out of frame and 00F is applied to a logic "high" state, the binary counter 42 is cleared. The 24-bit counter 40 increments the count value by one in response to the clock signal CLK in the "high" signal state applied to the enable end en. Thus counting up to 24 applies a logic " high " pulse to the reset stage R of the set / reset circuit 44. Accordingly, the loss of frame signal LOF, which is the output of the set / reset circuit 44, outputs a logic " low " state.

6 is a view briefly illustrating a process of declaring an in-frame state, an out-of-frame state, a loss-of-frame state, and a process of deviating from the loss-of-frame state according to an embodiment of the present invention.

In the above description of the present invention, the framing processing apparatus of the STM-4 structure has been described, but it should be understood that any STM-N structure frame processing apparatus can be applied by changing only the counters. Accordingly, the present invention can be practiced with various modifications and changes without departing from the spirit of the invention. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be defined by the equivalent of claims and claims.

As described above, the present invention has an effect of efficiently framing using a small number of logics to extract a frame alignment word from data having an STM-N form. The apparatus of the present invention can be importantly used in the SDH transmission apparatus.

Claims (1)

In a synchronous transmitter: A frame detector for outputting a frame enable signal upon detection of a frame word value in frame data having an STM-N structure; A first counter unit which is cleared at the time of outputting the frame enable signal or at the time of declaring an out-of-frame, and outputs a first count completion signal by counting one frame section based on a predetermined clock; A first set / reset circuit unit which is set when the frame enable signal and the first count completion signal are generated at the same time and declare an in-frame; A second counter that is enabled when the frame enable signal is not applied in the in-frame declaration state, counts when the frame enable signal is not applied every frame, and outputs a second count completion signal when the count value reaches a predetermined value Wealth; A second set / reset circuit unit which is set when the second count completion signal is output and declares an out of frame; A third set / reset circuit section set when the frame enable signal is applied and reset when the out-of-frame declaration is made to clear the first counter section so that the first counter section performs the count operation again; A loss-of-frame detection unit for declaring a loss-of-frame if the out-of-frame state persists for several tens of frames, and releasing a loss-of-frame declaration if the in-frame state persists for the tens of frames in the loss-of-frame declaration state; The loss of frame detection unit; A logic gate providing logic state values according to out-of-frame state and in-frame state, A counter for performing a predetermined number of frame counts based on the logic state values corresponding to the out-of-frame state, and outputting a second count completion signal when the count is completed; A counter that performs a preset number of frame counts based on the logic state value corresponding to the in-frame state and outputs a fourth count completion signal when the count is completed; And a fourth set / reset circuit unit which is set when the third count completion signal is applied to declare a loss of frame and releases the lost of frame that is reset when the fourth count complete signal is applied. .