KR19990075325A - Synchronous Digital Stepping Frame Counter - Google Patents

Abstract

It relates to the structure of the counter, to provide a structure of the SDH frame counter to identify the SDH frame location in order to easily extract / or insert the overhead bytes in the SDH frame. The SDH frame counter is reset by the initialization signal and an initialization signal generator for generating an initialization signal in response to the input of the frame offset, in order to count the position of the SDH frame having a predetermined size on the column side and the low side. And a row counter for counting a system clock and outputting the magnitude value of the column, and a row counter enabled for input of the generated initialization signal and counting a system clock to output the row magnitude value. .

Description

Synchronous Digital Stepping Frame Counter

The present invention relates to a frame counter of Synchronous Digital Hierarchy (hereinafter referred to as " SDH "), in particular to an SDH frame for easy extraction / or insertion of overhead bytes in an SDH frame. It relates to the structure of the SDH frame counter to identify the location.

In general, SDH is a kind of digital transmission method based on synchronous digital hierarchy, and is being rapidly developed by multiplexing / demultiplexing in synchronous transfer mode (STM-n). The general structure of the frame of the SDH as described above is as shown in FIG.

1 shows a synchronous digital hierarchy frame structure, in particular the structure of STM-1. In the figure, the row side has a size of 9 bytes and the column side has a total size of 270 bytes. That is, the SDH frame occupies a space having a size of "9 bytes x n x 270 bytes" during 125 ms of a frame offset (FO) of one frame used as a reference in the SDH multiplexed transmission system. Therefore, it has a bit rate of n x 155.520 Mbps (= 9 x n x 270 x 8 x 8 Kbps) (where n is a natural number such as 0, 1, 2, 3, etc., which is a constant attached to 9 bytes on the row side). . In the SDH frame having the configuration as shown in FIG. 1, "9 bytes x n x 9 bytes" is a section overhead (hereinafter referred to as "SOH") and an AU (Administration Unit) point space. The section of "9 bytes x n x 261 bytes" is a payload space.

Focusing on the STM-1 frame structure, the SOH includes a Regenerator Section Overhead (RSOH) having a size of 3 × 9 bytes and a Multiplexer Section Overhead (MSOH) having a size of 5 × 9 bytes. It consists of two spaces, and the AU pointer consists of a space of 1x9 bytes.

In order to generate various timing signals used in the SDH multiplexing system or to extract or insert overhead bytes in the SDH frame as shown in FIG. 1, it is necessary to specify the position of the SDH frame. That is, in order to extract or insert a specific byte of RSOH or MOSH in the SDH frame having the structure as shown in FIG. 1, it is necessary to designate the position of the SDH frame.

Accordingly, an object of the present invention is to provide an SDH frame counter that counts SDH frames so that a specific position of the SDH frame can be easily designated.

Another object of the present invention is to provide a frame counter that can specify a desired position within a frame by counting the SDH frame based on a frame offset used as a reference signal in the SDH multiplexing system.

Another object of the present invention is to provide a frame counter for generating a timing signal that can easily specify a specific position within the payload section of the SDH frame.

According to an aspect of the present invention, there is provided an apparatus for counting an SDH frame having a predetermined size on a column side and a row side, comprising: an initialization signal generator for generating an initialization signal in response to an input of a frame offset; Reset by the counter, the column counter counting the input system clock to output the magnitude value of the column, and the row counter enabled by the input of the generated initialization signal and counting the system clock to output the row size value It is characterized by the configuration.

1 illustrates a synchronous digital hierarchy frame structure.

2 is a block diagram of a synchronous digital frame frame counter in accordance with an embodiment of the present invention;

3 is an operation timing diagram for explaining the operation of FIG. 2;

4 is an enlargement of a portion of FIG. 3, which illustrates in more detail the timing diagram of operation of the ROW counter shown in FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to obscure the subject matter of the present invention.

2 is a diagram illustrating a configuration of a synchronous digital frame frame counter according to an embodiment of the present invention. In the drawing, reference numeral 12 is an initialization signal generator, 14 is a column counter, and 16 is a low counter.

In FIG. 2, the initialization signal generator 12 outputs a logic " high " signal in response to the binary data corresponding to the column value " 270 ₁₀ " of the above-described SDH frame. And AND 20, which inverts the output of AND gate 18 and outputs AND AND 22, which generates an initialization signal by logically multiplying the output of inverter 20 and the frame offset signal SYS_FO, which is input at a logic " low " It is configured to include.

Here, reference numerals 24 to 32 which are not described invert the logic states of the bits of IN8, IN5, IN4, IN3, and IN2 among the data bits IN9 to IN0 (where IN9 is the most significant bit) input to the AND gate 18. The inverters are configured to enable the output of the AND gate 18 to be logic "high" when the value of the data input to the AND gate 18 is "269 ₁₀ ", and the inverters 24 to 32 and the AND gate 18 are inputted. Decoder outputs logical "high" when "101100001" in binary.

In the column counter 14, 4-bit binary counters 36, 38, and 40 are cascaded to form a 12-bit modulo-12 counter. In this case, the slave connection of the counters 36, 38, and 40 is carried out by the carry out cout of the counter of the lower bit and is connected to the enable terminal CIN of the counter of the next stage, and the system clock CLK-19C (19 MHz) is respectively provided. This is a synchronous counter supplied to the clock terminals CLK of the counters 36, 38, and 40. The outputs of the outputs CLO0 to CLO8 of the column counter 14 are fed back to the input terminal of the initialization signal generator 12 described above.

The row counter 16 is a 4-bit binary counter that is enabled during the input period of the initialization signal output from the AND gate 22 to count the system clock CLK_19C. Here, reference numeral 34, which is not described, is an inverter for inverting the output of the AND gate 22 and supplying it to the enable terminal CIN of the low counter 16.

FIG. 3 is a diagram illustrating an operation timing diagram for describing the operation of FIG. 2, and FIG. 4 is an enlargement of a portion of FIG. 3, which illustrates the operation timing diagram of the ROW counter shown in FIG. 2 in more detail. Figure is shown. 3 and 4, SYS_FO is a frame offset signal that is output as a pulse having a logic " low " for 52 ms per cycle of 125 ms. CLK_19C is a pulse signal having a frequency of 19 MHz as the system clock, ROW [3: 0] is a 4-bit data value as the output of the low counter 16, and COL [8: 0] is the output of the column counter 14. 9-bit data value.

Hereinafter, the operation of the SDH frame counter configured as shown in FIG. 2 according to an embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 and 4, when the frame offset signal SYS_FO having a logic " low " every 125 ms is input to the initialization signal generator 12 and the low counter 16, the output ROW [3: 0 of the low counter 16 is received. ] Is initialized to "0 ₁₀ ". At this time, the AND gate 22 in the initialization signal generator 12 initializes all the counters 36, 38, and 40 in the column counter 14 shown in FIG. 2 in response to the "low" signal.

Each of the counters 36, 38, and 40 initialized by the output of the AND gate 22 counts the CLK_19C inputted to the clock terminal CLK from the initial value "0 ₁₀ " as shown in FIGS. 0]. In this case, timing diagrams of data counted and output by the column counter 14 are as shown in FIGS. 3 and 4.

As described above, the column value COL [8: 0] counting and outputting the system clock CLK_19C from the initial value (0 ₁₀ ) as shown in FIG. 1 indicates that the column value COL [8: 0] is "269 ₁₀ "(" 100001101 ") to complete the counting of one column direction, all signals input to the AND gate 18 are input to the logic" high "by the inverting operation of the inverters 24 to 32 shown in FIG.

Thus, if column counter 14 counts one column and its value COL [8: 0] is " 269 _{10 &} quot ;, then the output of AND gate 18 transitions to a logic " high ". At this time, the output " high " of the AND gate 18 is inverted to a logic " low " by the inverter 20 connected to the output terminal, so that the AND gate 22 outputs a logic " low " signal to all the counters 36, 38 and 40 in the column counter 14. Initialize them.

On the other hand, the inverter 34 having an input connected to the output of the AND gate 22 in the initialization signal generator 12 inverts the logic "low" initialization signal to the logic "high" state and supplies it to the enable terminal CIN of the low counter 16. At this time, the row counter 16 is enabled and counts the system clock CLK_19C input to the clock terminal CLK. That is, the row counter 16 operates to count the row side only once when the column counter 14 counts the column side up to "269 ₁₀ " so that it counts the number from 0 to 269 9 times (from 0 to -8). . The row counter 16 operated in this manner is reset and initialized by the system frame offset signal SYS_FO generated every 125 ms.

Therefore, the column counter 14 in the frame counter as shown in FIG. 2 described above repeatedly counts the columns 0 to 269 of the SDH frame, and the row counter 16 outputs the values 0 to 8 to 269. It counts each time and outputs the position value of the frame.

Such a configuration can be implemented using a general-purpose logic gate, and can be manufactured in one chip using a field programmable gate array, which is composed of a plurality of logics and can be programmed.

As described above, the frame counter according to an embodiment of the present invention is used for designing an SDH system by easily designating a position in a frame by using a system clock used in the system and a system frame offset signal indicating a frame period of the SDH. There is an advantage that the internal timing signal generated and the overhead in the frame can be efficiently processed (insertion / extraction of data at a specific position).

Claims (4)

In the device for counting the SDH frame having a predetermined size on the column side and row side, An initialization signal generator for generating an initialization signal in response to the input of the frame offset; A column counter reset by the initialization signal and counting an input system clock to output a size value of the column; And a low counter enabled by the input of the generated initialization signal and counting a system clock to output a magnitude value of the row. The synchronous digital frame frame counter according to claim 1, wherein the row counter is initialized every cycle (125 ms) of the synchronous digital frame by inputting a system frame offset signal. The decoder of claim 1 or 2, wherein the initialization signal generator generates an initial call signal in response to a value of a column counting and outputting from the column counter being a value of "270" of one column of a synchronous digital hierarchy frame. A synchronous digital frame frame counter further comprising. 4. The synchronous digital frame frame counter as claimed in claim 3, wherein the column counter is a synchronous counter cascaded with three 4-bit binary counters.