JP3487701B2 - Frame counter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame counter for specifying each position on a multiframe composed of a plurality of frames.

The present invention is also based on SDH (Synchronous
Digital Hierarchy) and SONET (Synchronous Opti
cal NETwork), like a frame counter for specifying each position on the frame represented by a matrix.

[0003]

2. Description of the Related Art Conventionally, frame counters of this type have been disclosed in JP-A-3-18446 and JP-A-5-2521.
The counter described in Japanese Patent No. 27 is known.

This frame counter divides the frame counter into a plurality of synchronous counters according to the structure of a multi-frame (frames in the case of SDH and SONET), and cascade-connects these through a carry signal. ing. In order to decode the value of the frame counter and process multi-frame data at high speed, it is general to make the decoder circuit and the frame processing circuit synchronous.

[0005]

As the transmission speed increases, one multiframe (SDH,
In the case of SONET, the amount of data transmitted in frames) increases. As a result, the number of bits of the frame counter increases, and the number of flip-flop circuits of each synchronous counter increases. As a result, the carry signal increases the load on the synchronous counter used in the synchronous counter at the next stage, and the operating speed of this synchronous counter becomes slow.

Further, as the number of flip-flop circuits of the synchronous counter increases, the load on the circuit that generates a reset signal for synchronizing the counter with the phase of multi-frame (frame in the case of SDH or SONET) increases. The operating speed of the reset signal generating circuit becomes slow.

[0007]

In order to solve the above problems, the first invention requires synchronization with a clock signal in order to specify the position on each frame of a multiframe. Focusing on the fact that it is not necessary to synchronize with the clock signal to specify each frame position on the multi-frame, the frame counter is divided into a synchronous counter and an asynchronous counter.

Here, the synchronous counter is reset by a reset signal synchronized with the phase of the multi-frame,
Each position on the frame is specified by counting the clock signals synchronized with the phase of the multi-frame. The asynchronous counter is reset by the reset signal and counts the carry signal of the synchronous counter to identify each frame position on the multi-frame.

A second invention is SDH or SONET.
In order to specify each column position of the frame of, it is necessary to synchronize with the clock signal, whereas to specify each row position of the frame, it is not necessary to synchronize with the clock signal. The counter is divided into a synchronous counter and an asynchronous counter.

Here, the synchronous counter is reset by a reset signal synchronized with the phase of the frame and counts clock signals synchronized with the phase of the frame to identify each column position. The asynchronous counter is reset by the reset signal and counts the carry signal of the synchronous counter to identify each frame position on the frame.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

[First Embodiment] [Structure] FIG. 1 is a block diagram showing the structure of a first embodiment of the present invention. Note that FIG. 1 shows an overhead processing device provided with the frame counter of the present invention.

This overhead processing apparatus comprises an overhead detection circuit 100 and an overhead processing circuit 200.
Have. The overhead detection circuit 100 has the frame counter 110 and the decoder 120 of the present invention.

In the overhead processing device, the overhead detection circuit 100 includes a data signal input terminal 300.
The overhead OH included in the first frame of the multi-frame is detected from the data signal D supplied to, and the position display signal S1 indicating the overhead position is output.

Further, the overhead processing circuit 200 processes the data inserted in the overhead OH of each frame on the multi-frame based on the detection output of the overhead detection circuit 100.

In the overhead detection circuit 100,
The frame counter 110 of the present invention identifies each position on the multi-frame. The decoder 120 generates the position display signal S1 based on the count outputs S2 and S3 of the frame counter 110.

The above is the configuration of the overhead detector. Next, the frame counter 1 which is a feature of the present invention
The configuration of 10 will be described.

In this embodiment, the clock signal CK is used to specify the position on each frame of the multi-frame.
The frame counter 110 needs to be synchronized with the clock signal CK in order to specify each frame position on the multi-frame.
Is divided into a synchronous counter 111 and an asynchronous counter 112.

Here, the synchronous counter 111 is reset by the reset signal R supplied to the reset signal input terminal 400, and counts the clock signal CK supplied to the clock signal input terminal 500, so that the bits on the frame are It has the function of specifying the position.

Here, the synchronous counter 111 is composed of an n-ary counter. n indicates the number of bits included in one frame. The reset signal R is a signal that is synchronized with the phase of the multiframe and has the same period as the multiframe period. The clock signal CK is a signal that is synchronized with the phase of the multiframe and has the same period as the bit period.

Further, the asynchronous counter 112 is reset by the reset signal R and counts the carry signal S4 of the synchronous counter 111 to specify each frame position on the multi-frame.

[Operation] The operation of the above configuration will be described with reference to the timing chart of FIG.

First, the operation of the overhead processing device will be described. The data signal D supplied to the data signal input terminal 300 is supplied to the overhead processing circuit 200. This data signal D is multi-framed. Figure 2
Shows a case where the number of frames m included in each multi-frame is 9. Each frame has an overhead OH and a payload PL, as shown in FIG.

The reset signal R supplied to the reset signal input terminal 400 is supplied to the overhead detection circuit 100. The clock signal CK supplied to the clock signal input terminal 500 is supplied to the overhead detection circuit 100,
It is supplied to the overhead processing circuit 200.

The overhead detecting circuit 100 detects the overhead OH included in the first frame of the multi-frame in synchronization with the reset signal R and outputs a position display signal S1 indicating the position thereof. This position display detection signal S
1 is supplied to the overhead processing circuit 200.

The overhead processing circuit 200 detects the overhead OH included in each frame of the multi-frame based on the position display signal S1 and performs a predetermined process on the data of the overhead OH. This processing is performed using the clock signal CK as a reference signal.

The above is the operation of the overhead processing device. Next, the operation of the overhead detection circuit 100 will be described.

After being reset by the reset signal R, the frame counter 110 counts the clock signal CK. Thereby, each bit position on the multi-frame is specified.

The count outputs S2 and S3 are supplied to the decoder 120. The decoder 120 decodes the count outputs S2 and S3 to generate the position display signal S1. This processing is performed using the clock signal CK as a reference signal.

The above is the operation of the overhead detection circuit 100. Next, the operation of the frame counter 110, which is a feature of the present invention, will be described.

The synchronous counter 111 has a reset signal R
After being reset by, the clock signal CK is counted. As a result, the count value (count output S2) of the counter 111 sequentially increases by 1 from 1 in synchronization with the clock signal CK, as shown in FIG. After that, when the count value becomes n, the counter 111 starts counting from 1 again. By the above counting operation, each bit position on the frame is repeatedly specified at the frame cycle.

The asynchronous counter 112 counts the carry signal S4 output from the synchronous counter 111 after being reset by the reset signal R. As a result, the count value of the counter 112 is the carry signal S4.
In synchronism with the above, the number is sequentially increased from 1 by 1. After that, when the count value reaches 9, the counter 112 is reset by the reset signal R and restarts counting from 1. By the above counting operation, each frame position on the multi-frame is repeatedly specified in the multi-frame cycle.

Counter output S of the counters 111 and 112
2, S3 are supplied to the decoder 120 as signals indicating each bit position on the multiframe.

[Effect] According to this embodiment described in detail above, the following effects can be obtained.

(1) First, according to this embodiment, the frame counter 110 is reset by the reset signal R and counts the clock signal CK,
Synchronous counter 111 for identifying each position on the frame
Then, by resetting the reset signal R and counting the carry signal S4 of the synchronous counter 111, the synchronous counter 111 is divided into the asynchronous counters 112 that specify each frame position on the multi-frame. The load can be reduced.

(2) Further, according to such a configuration, since the reset of the asynchronous counter 112 is asynchronous,
A buffer can be inserted in the reset signal input section of the counter 112. As a result, the reset signal R
It is possible to reduce the load on the reset signal generating circuit that generates

(3) According to this embodiment, since the frame counter 110 is separated into the synchronous counter 111 and the asynchronous counter 112, the synchronous counter 11
1 can be miniaturized and speeded up.

(4) Further, according to this embodiment, the asynchronous counter 112 for counting the carry signal S4.
Since the operation speed of 1 can be slow, the circuit can be easily arranged.

[Second Embodiment] In the above embodiment, the case where the synchronous counter 111 is composed of one counter has been described.

On the other hand, in this embodiment, the synchronous counter is divided into two, and the carry signal is used to cascade-connect the two counters.

[Structure] FIG. 3 is a block diagram showing the structure of the synchronous counter of this embodiment.

The illustrated synchronous counter has a first synchronous counter 1A, a second synchronous counter 2A, and a latch circuit 3A.

Here, the first synchronous counter 1A is reset by the reset signal R, and counts the clock signal CK to specify the bit position of each division part obtained by dividing one frame into m. To do. The counter 1A is composed of a (n / m) -adic counter. Here, m is set so that n / m is an integer.

The second synchronous counter 2A specifies each divided portion on the frame by counting the carry signal S5 of the first synchronous counter 1A. The counter 2A is composed of an m-ary counter.

The latch circuit 3A latches the reset signal R and outputs the latch output as the reset signal R1 of the second synchronous counter 2A.

[Operation] The operation of the above configuration will be described with reference to the timing chart of FIG.

When the reset signal R is input while the frame counter 110 is in an indefinite state, the first synchronous counter 1A at the preceding stage is reset at the falling timing T0 of the reset signal R. As a result, the count value of the synchronous counter 1A is set to 1.

Thereafter, the synchronous counter 1A counts the clock signal CK. As a result, the count value of the synchronous counter 1A is sequentially updated by 1. When this count value reaches n / m, the synchronous counter 1A
Automatically starts counting again from 1. As a result, the bit position of each division obtained by dividing one frame into m is repeatedly specified in the repetition cycle of the division.

The reset signal R is temporarily held in the latch circuit 3A and then output as a reset signal R1 at a predetermined timing. This reset signal R1 is
It is supplied to the second synchronous counter 2A in the subsequent stage. As a result, the synchronous counter 2A is reset at the falling timing T1 of the reset signal R1. as a result,
The count value of the synchronous counter 2A is set to 1.

After that, the synchronous counter 2A counts the carry signal S5. As a result, the count value of the synchronous counter 2A is sequentially updated by 1. When the count value reaches m, the synchronous counter 2A automatically starts counting from 1 again. As a result, the position of each divided portion of each frame is repeatedly specified at the frame cycle.

The second synchronous counter 2A may be reset between the reset of the first synchronous counter 1A and the output of the first carry signal S5.
In the example of FIG. 4, the falling timing T of the reset signal R is
0 to the first fall timing T of the carry signal S5
It suffices to be reset before 2 has elapsed. FIG. 4 shows a case where the reset is performed at the timing T1 when one cycle of the clock signal CK has elapsed from the falling timing T0 of the reset signal R.

As described above, the first synchronous counter 1A in the preceding stage counts the clock signal CK and counts from 1 to n / m, and runs by itself. As described above, the first synchronous counter 2A in the subsequent stage counts the carry signal S5 to count from 1 to m and self-runs. Therefore, the count values of the counters 1A and 2A do not change even if the reset signal R is not input at the timing T3 when one frame period has elapsed from T0.

[Effect] According to this embodiment described in detail above, the same effects as those of the previous embodiment can be obtained, and further the following effects can be obtained.

That is, according to this embodiment, the synchronous counter includes the first synchronous counter 1A for counting the clock signal CK and the second synchronous counter 2A for counting the carry signal S5 of the counter 1A. Since the reset signal R of the first synchronous counter 1A is supplied to the second synchronous counter 2A via the latch circuit 3A, the load on the circuit that generates the reset signal R can be reduced. it can. As a result, the delay of the reset signal R can be reduced, so that the peripheral circuits of the frame counter can operate at high speed.

[Other Embodiments] The two embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments.

(1) For example, in the above first and second embodiments, the present invention is applied to a frame counter for specifying each position on a multi-frame composed of a plurality of frames. explained. However, this invention
It can also be applied to a frame counter for specifying each position on a frame represented by a matrix, such as an SDH or SONET frame.

In this case, the frame counter is reset by the reset signal whose phase is synchronized with the frame, and the synchronous counter which specifies each column position by counting the clock signal whose phase is synchronized with the frame, and the reset signal. By resetting and counting the carry signal of the synchronous counter, it is divided into asynchronous counters that specify each row position.

(2) Further, in the second embodiment,
The case where the synchronous counter of the frame counter is divided into two synchronous counters 1A and 2A has been described. However, the present invention may be divided into three or more synchronous counters. In this case, all the latch circuits may not be inserted between the two counters connected in cascade, but a necessary number may be inserted according to the load.

That is, the synchronous counter of the present invention is
The first stage counts the clock signal CK, and the second and subsequent stages latch multiple synchronous counters cascaded to count the carry signal of the previous stage and the reset signal supplied to the synchronous counter of the previous stage. In order to supply the latch output to the subsequent synchronous counter as a reset signal, a latch circuit appropriately inserted between adjacent synchronous counters may be provided.

(3) In addition to this, it is needless to say that the present invention can be variously modified without departing from the scope of the invention.

[0061]

As described above in detail, according to the first invention, in order to specify the position on each frame of the multiframe, it is necessary to synchronize with the clock signal.
Focusing on the point that it is not necessary to synchronize with the clock signal in order to specify each frame position on the multiframe, the frame counter is reset by the reset signal synchronized with the phase of the multiframe and synchronized with the phase of the multiframe. A synchronous counter that identifies each position on the frame by counting the clock signal, and a carry signal that is reset by the reset signal and is counted by the synchronous counter, and identifies each frame position on the multi-frame Since it is divided into asynchronous counters, the load on the synchronous counter can be reduced.

Further, according to such a configuration, since the reset of the asynchronous counter is asynchronous, a buffer can be inserted in the reset signal input section of this counter. This can reduce the load on the circuit that generates the reset signal.

Similarly, according to the second invention, SDH and S
Like an ONET frame, it is necessary to synchronize with a clock signal to specify each column position of a frame represented by a matrix, whereas it is necessary to synchronize with a clock signal to specify each row position. Paying attention to the point that there is no such, there is a synchronous counter for resetting the frame counter by a reset signal synchronized with the phase of the frame, and counting the clock signal synchronized with the phase of the frame, and specifying the column position; Reset by
Since the asynchronous counter for specifying the row position is configured by counting the carry signal of the synchronous counter, the load of the synchronous counter can be reduced.

Further, according to such a configuration, since the reset of the asynchronous counter is asynchronous, a buffer can be inserted in the reset signal input section of this counter. This can reduce the load on the circuit that generates the reset signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the second embodiment of the present invention.

[Explanation of symbols]

100 ... Overhead detection circuit 200 ... Overhead processing circuit 300 ... Data signal input terminal 400 ... Reset signal input terminal 500 ... Data signal input terminal 110 ... Frame counter 120 ... Decoder 111 ... Synchronous counter 112 ... Asynchronous counter 1A ... 1st synchronous counter 2A ... second synchronous counter 3A ... Latch circuit

Claims (3)

(57) [Claims] 1. A frame counter for identifying each position on a multi-frame composed of a plurality of frames, wherein a clock reset by a reset signal synchronized with the phase of the multi-frame and synchronized with the phase of the multi-frame A synchronous counter that identifies each position on the frame by counting signals, and a carry signal that is reset by the reset signal and counts the carry signal of the synchronous counter to identify each frame position on the multiframe. A frame counter having an asynchronous counter for specifying. 2. A frame counter for identifying each position on a frame represented by a matrix, counting a clock signal which is reset by a reset signal synchronized with the phase of the frame and is synchronized with the phase of the frame. A synchronous counter that specifies each column position, and an asynchronous counter that specifies each frame position on the frame by counting the carry signal of the synchronous counter that is reset by the reset signal. A frame counter that is characterized. 3. The synchronous counter comprises: a plurality of synchronous counters cascade-connected to count the clock signal in the first stage and count carry signals in the previous stages in the second and subsequent stages; And a latch circuit appropriately inserted between adjacent synchronous counters in order to latch a reset signal supplied to the synchronous counter and to supply the latch output to the synchronous counter in the subsequent stage as a reset signal. The frame counter according to claim 1 or 2.