JP2950784B2 - Asynchronous signal synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous signal synchronizing circuit for synchronizing a transmitted signal with a clock on a receiving side in digital transmission.

[0002]

2. Description of the Related Art FIG.
FIG. 1 shows a configuration of a conventional asynchronous signal synchronization circuit disclosed in Japanese Unexamined Patent Application Publication No. HEI 9-125, and FIG. 6 shows a time chart thereof.

In FIG. 6, an input signal S11 is asynchronous with a clock signal CK11. This input signal S1
1 (FIG. 6 (b)) is taken into the first flip-flop 11 at the rising edge of the clock signal CK11 (FIG. 6 (a)), and the input signal S11 is also supplied to the second flip-flop 12 by the clock signal CK11. Is taken in at the falling edge of.

The output signal S12 (FIG. 6 (c)) of the first flip-flop 11 and the output signal S13 (FIG. 6 (d)) of the second flip-flop 12 are selected by a switching control circuit 14 to be switched. It is input to the circuit 13. Here, the switching control circuit 14 compares the asynchronous input signal S11 with the output signal S14 of the selection circuit 13 (FIG. 6 (f)) according to the following criteria, and outputs the resulting switching signal CNT (FIG. 6 (e)). ) Controls the selection circuit 13.

That is, in a state where the selection circuit 13 first selects the flip-flop 11 side, that is, inputs the signal S12, after the state of the input signal S11 changes (in FIG. 6, the data D1 changes to D2). When a state occurs in which the output signal S14 of the selection circuit 13 becomes the same (D2) within the predetermined time t ₀ , the switching control circuit 14 causes the switching signal CNT so that the selection circuit 13 selects the flip-flop 12 side. Change the state of. As a result, the output signal S14 of the selection circuit 13 maintains the same state as the previous state (the state of outputting the data D1 in FIG. 6), and the state of the input signal S11 changes (in the case of D1, the state changes from D1 to D2). Change), the input to the third flip-flop 15 does not change.

As a result, a signal synchronized with the clock signal CK11 is obtained from the flip-flop 15. In the case of FIG. 6, the selection circuit 13 is selecting the flip-flop 12 side and the predetermined time t after the state of the input signal S11 changes (D2 → D3).
_The state when the output state of the selection circuit 13 becomes the same (D3) within ₀ is shown.

[0007]

In recent years, the scale of LSI has been steadily increasing, and logic synthesis and testability design have become essential as design techniques.

However, in the above-described conventional configuration, since the flip-flop 12 is in a falling operation and the switching control circuit 14 needs to be adjusted for a predetermined time length, logic synthesis cannot be performed in circuit design, and manufacturing is not possible. There is a problem that the testing of the manufactured product is also difficult.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide an asynchronous signal synchronizing circuit having a minimum configuration using only flip-flops that all operate at rising edges.

[0010]

In order to achieve this object, the present invention employs the following means. That is, for example, as shown in FIG. 1, a first flip-flop 1 that takes in an input data strobe signal at the rising edge of a clock signal, and a second flip-flop that takes in the output of the first flip-flop 1 at the rising edge of the clock signal 2, a gate 3 for outputting the logical product of the output of the first flip-flop 1 and the inverted output of the second flip-flop 2, and an input when the output of the gate is true and the clock signal rises Third to capture data signal
The flip-flop 4 is provided.

As a result, a signal which becomes true ("H") when the data signal is true can be obtained from the gate, and the output of the third flip-flop 4 becomes a data signal synchronized with the clock signal. .

Generally, in a digital circuit, a plurality of (n) bits are processed in parallel, so that the above-mentioned circuit also needs to process a plurality of bits simultaneously. Therefore, as shown in FIG. 3, an external input signal is taken in at the rise of the external clock signal.
A bit shift register, and n-
Bit number detecting means for detecting that one piece of data has been input; and a fourth flip-flop 8 for taking in the output of the bit number detecting means at the rise of the external clock signal. The output of the fourth flip-flop 8 is used as an input data strobe signal.

Thus, a data strobe signal in which the input to the n-bit shift register becomes true (“H”) every n bits can be obtained from the fourth flip-flop.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. (Embodiment 1) FIG. 1 shows a configuration diagram of an asynchronous signal synchronization circuit according to a first embodiment of the present invention.
FIG. 2 is a time chart thereof. Hereinafter, the configuration of the present embodiment will be described together with the operation.

The data strobe signal S1 shown in FIG.
Is formed in synchronization with the clock signal S2 (in the illustrated case, the cycle of the data strobe signal S1 is twice the cycle of the clock signal CK2).
1 and the clock signal CK1 are asynchronous.
The data signal S2 shown in (d) is the data strobe signal S1.
Is true when is true.

The data strobe signal S1 is fetched by the flip-flop 1 at the rise of the clock signal CK1. Incidentally, at this time, the data strobe signal S1 is asynchronous with respect to the clock signal CK1, so that the flip-flop 1
As shown in FIG. 2 (e), even if the clock signal CK1 rises, the "H" state of the data strobe signal S1 cannot be completely captured, that is, a metastable state, and the output of the Q terminal of the flip-flop 1 As shown in FIG. 2, the signal S3 has a period in which the signal S3 becomes “H” or “L” and is indefinite.

The output of the flip-flop 1 is further taken into the second flip-flop 2 at the rise of the clock signal CK1, and the inverted Q terminal of the first flip-flop 1 as shown in FIG. The signal 4 which becomes "L" one clock later than the signal S3 which is the output of the signal 4 is output.

Since the AND gate 3 calculates the logical product of the signal 2 and the signal 3, the signal S5 which becomes "H" during the time when the data signal S2 is true as shown in FIG. Output. The flip-flop 4 outputs the data signal S2 when the signal S5 is true and the clock signal CK1 rises.
And the clock signal CK as shown in FIG.
Thus, a signal S6 synchronized with 1 is output.

As is clear from the above description, in the asynchronous signal synchronization circuit according to the present embodiment, all the flip-flops operate at the rising edge, so that theoretical synthesis can be performed at the time of designing a large-scale LSI. Thus, an excellent effect can be obtained. Furthermore, since there is no uncertain time element, it is easy to determine the quality of the product based on the test pattern.
In the above example, the frequency of the clock signal CK1 needs to be at least twice the frequency of the clock signal CK2.

(Embodiment 2) FIG. 3 shows the first embodiment of the present invention.
FIG. 4 is a circuit diagram showing an embodiment until a data strobe signal is obtained according to the embodiment, and FIG. 4 is a time chart thereof.

In FIG. 3, the input data signal S7 is sequentially taken into the shift register 5 at the rise of the external clock signal CK2 (FIG. 4 (b)).
The data is output as bit parallel data S8 (FIG. 4 (c)).

The clock signal CK2 is also input to the 3-bit counter 6, and the 3-bit counter 6 counts up by one each time the clock signal CK2 rises (FIG. 4 (d)). The output of the 3-bit counter 6 is input to a decoder 7, which outputs a signal to the D input of the flip-flop 8 every time the count value of the 3-bit counter 6 becomes 7 (decimal 111). The signal S9 that becomes “H” (FIG. 4
(e)).

Since the flip-flop 8 captures the value of the D input at the rising edge of the clock signal CK2, the flip-flop 8 receives the input data S7.
Outputs a data strobe signal S1 (FIG. 4 (f)) which becomes "H" every 8 bits.

This data strobe signal S1 is used for the synchronization circuit shown in the first embodiment,
The following configuration and operation are the same as those of the first embodiment. However, since 8 bits are handled here, the output of the 8-bit shift register 5 is set at the last stage so that the signal S5 is true and the clock signal Capture at the rising edge of CK1 8
A flip-flop 9 capable of processing bits is provided.

As described above, the asynchronous signal synchronizing circuit according to the present embodiment includes an n-bit shift register, and a bit number detecting means 10 which is true when the number taken into the shift register is n-1. With the configuration including a flip-flop that takes in the output of the bit number detection means 10 at the rising edge of the clock, synchronization can be achieved even when the input signal is continuously transmitted.

It should be noted that the counter 6 constituting the bit number detecting means 10 in this embodiment is an up-counter with an initial value of 0, and the decoder 7 is a combination which becomes true when the output of the counter 6 is 7, It goes without saying that the same combination can be realized by any means indicating that seven data are taken into the shift register.

[0027]

As described above, in the asynchronous signal synchronizing circuit according to the present invention, the first flip-flop for taking in the data strobe signal at the rise of the clock signal and the first flip-flop are used.
A second flip-flop that takes in the output of the flip-flop at the rising edge of the clock signal; a gate that outputs a logical product of the output of the first flip-flop and the inverted output of the second flip-flop; By providing the third flip-flop which takes in the input data signal when the output is true and the clock signal rises, the logic synthesis can be performed at the time of design, so that the design cost can be reduced and the test pattern becomes uncertain. Since no time element is included, it is possible to reliably determine the quality of the product.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart of the circuit shown in FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a time chart of the circuit shown in FIG. 3;

FIG. 5 is a circuit diagram of a conventional asynchronous signal synchronization circuit.

FIG. 6 is a time chart of the circuit shown in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st flip-flop 2 2nd flip-flop 3 AND gate 4 3rd flip-flop 8 4th flip-flop

Claims (2)

(57) [Claims] A first flip-flop for receiving an input data strobe signal at a rising edge of a clock signal; a second flip-flop for capturing an output of the first flip-flop at a rising edge of the clock signal; A gate for outputting the logical product of the output of the flip-flop and the inverted output of the second flip-flop; and a third flip-flop which takes an input data signal when the output of the gate is true and the clock signal rises. Asynchronous signal synchronization circuit comprising a loop. 2. An n-bit shift register for taking in an external input signal at the rising edge of an external clock signal (n is an integer).
A number-of-bits detecting means for detecting that n-1 pieces of data have been input to the shift register; and a fourth flip-flop for taking in the output of the number-of-bits detecting means at the rising edge of the external clock signal.
2. The asynchronous signal synchronizing circuit according to claim 1, wherein an output of said shift register is an input data signal, and an output of said fourth flip-flop is an input data strobe signal.