JP2001245176A - Field decision circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field decision circuit for stably discriminating odd and even fields from a composite video signal by a circuit which has simple composition, small scale and no need of extra adjustment. SOLUTION: The field decision circuit comprises a synchronizing separation circuit 1 for separating a composite synchronous signal b from an input composite video signal a, a delay circuit 2 for outputting a shift clock signal c and being connected to the output side of the separation circuit 1, a shift resister circuit 3 holding and bit-shifting the pattern of an equivalent pulse and a vertical synchronous period, by using a clock signal generated at the composite synchronizing signal b, and a decision circuit 4 for obtaining a field discriminating signal e by the decision of the odd and the even fields of the composite video signal according to the decision of the bit pattern provided from the shift resister circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field judgment circuit, and more particularly to a field judgment circuit for judging odd / even fields to which a composite video signal can be inputted.

[0002]

2. Description of the Related Art In a typical television (hereinafter, referred to as a TV) receiver, an image is displayed by a plurality of fields (for example, two fields of an odd number and an even number) in order to reduce flickering of the image. are doing.

FIGS. 9 and 11 are block diagrams showing the configuration of a conventional field determination circuit. FIG.
Is a "field determination method" disclosed in Japanese Patent Application Laid-Open No. 5-37809. This prior art includes an extraction circuit 100 receiving a video signal input, a phase difference detection circuit 101, a current detection result holding circuit 102, and a previous detection result holding circuit 10
3. It is composed of a field determination means 104 and a previous determination result holding circuit 105, and obtains a determination result output from the field determination means. First, an input video signal is input to the extraction circuit 100 to obtain a vertical synchronization signal. The phase difference between the two synchronization signals is detected by the phase difference detection circuit 101 to which the extracted synchronization signals are input. Further, a holding circuit 102 for holding the current phase difference detection result and a holding circuit 105 for holding the previous field determination result are provided. The current phase difference detection result held in the current detection result holding circuit 102, the previous phase difference detection result held in the previous detection result holding circuit 103, and the previous determination result holding circuit 1
The state transition is determined by the field determination unit 104 based on the previous field determination result held in
Final field judgment is performed.

FIG. 10 is a flowchart showing a field determination procedure of the field determination circuit shown in FIG. First, in step S1, it is determined whether one field is completed. When one field ends (step S1: YES)
In step S2, the process proceeds to step S2, where the previous determination result holding circuit 10
It is determined whether or not the output c of No. 5 is an odd number. On the other hand, if it is not the end of one field (step S1: NO), the process returns to step S1 and waits for the end of one field. Step S
If c = odd in Step 2 (Step S2: YES), the process proceeds to Step S3, and it is determined whether the output e of the current detection result holding circuit 102 is odd and the output b of the previous detection result holding circuit 103 is b = even. . If a = odd number and b = even number (step S3: YES), the process proceeds to step S4, and a determination output that the output from the field determination unit 104 is d = odd is obtained. On the other hand, if c = not an odd number (step S
2: NO), the process proceeds to step S5, where a = even number and b
= Judge whether it is an odd number or not. If a = even and b = odd (step S5: YES), the process proceeds to step S6,
It is determined that d = even number described above. Step S3: NO
And step S5: If NO, step S5
6 and step S4, where it is determined that d = even number and d = odd number.

Next, FIG.
FIG. 1 is a block diagram of a “field discriminating circuit” disclosed in Japanese Unexamined Patent Application Publication No. H11-157, FIG. The field determination circuit includes a shift register 200, a selection circuit (selector) 201, a latch 202,
It comprises a decoder 203 and a state machine 204. The shift register 200 receives a video signal input and a clock, and outputs Va to Vf to the selection circuit 20.
Sent to 1. A vertical synchronization output is obtained from the selection circuit 201. The vertical synchronization output and the horizontal scanning period division signal are input to the latch circuit 202, and a field output is obtained from the decoder 203. The output of the decoder 203 is input to a selection circuit 201 via a state machine 204, and controls the selection circuit 201. Thus, the odd / even field is determined by determining the phase in the scanning line period where the rising edge of the vertical synchronization signal is located, using the vertical synchronization signal held and shifted in the shift register 200.

[0006]

The former technique requires a circuit for separating a vertical synchronizing signal and a horizontal synchronizing signal from a composite video signal. In addition, the phase difference detection used for field determination requires a state machine that detects and controls state transitions with reference to past determination results for the phase relationship between the vertical synchronization signal and the horizontal synchronization signal, and verifies complex conditions. , A complicated logic circuit is required. Further, the field determination process is complicated as shown in FIG. 10, and is generally configured by a CPU.
It is realized by a complicated procedure. Therefore, the field determination according to the conventional technique has a problem that a complicated configuration and a complicated determination procedure are required.

On the other hand, in the latter case of the above-mentioned prior art, it is necessary to divide one horizontal scanning line period into at least six parts in order to reliably determine a field. Further, it is necessary to define a state corresponding to the phase and to control the state transition, and therefore, a signal for determining the phase in the horizontal scanning period is required. In addition, a state machine corresponding to the divided phases is required, and the configuration becomes complicated. Reducing the number of scan line divisions and the number of state transitions for simplification makes the field determination operation unstable as described in this publication. Therefore, there has been a problem that the circuit configuration is complicated or the circuit scale is easily increased, and the determination procedure is complicated.

[0008]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to stably distinguish odd and even fields from a composite video signal by a circuit having a relatively simple configuration and a small circuit size, and requiring no special adjustment. An object of the present invention is to provide a field determination circuit that can output an identification signal.

[0009]

According to the present invention, there is provided a field determination circuit comprising: a sync separation circuit for separating a composite sync signal from an input composite video signal; and a falling edge of the composite sync signal separated by the sync separation circuit. A delay circuit for generating a shift clock signal having a rising edge delayed by a predetermined time from a multivibrator circuit for generating a holding clock signal having a pulse width of 0.5 times or more the horizontal scanning period from the falling edge of the composite synchronization signal; A shift register that captures and shifts the composite synchronizing signal at each rising edge of the shift clock signal from the delay circuit to obtain a shift register output, and outputs the shift register output obtained by the shift register using a holding clock signal from the multivibrator circuit. Holds the odd and even fields of the composite video signal It determines field and a judging circuit for outputting a field identification signal.

According to a preferred embodiment of the present invention, the above-described determination circuit is based on a pair of comparison circuits for detecting different bit patterns from the input shift register output and a comparison result by the pair of comparison circuits. A set / reset circuit for performing a set / reset operation, and determines an odd field and an even field of the composite video signal, and outputs a field identification signal. Further, the determination circuit is configured to transmit a high-level determination result output in an odd-numbered field, and to transmit a low-level determination result output in an even-numbered field.

The above-described delay circuit includes a differentiating circuit for differentiating the input composite synchronizing signal into a pulse for one cycle of the clock signal, a reset circuit reset by the differential pulse from the differentiating circuit, counting by the clock signal, and A counter circuit for generating a shift clock signal having a rising edge delayed by a predetermined time from the falling edge of the synchronization signal. The above-described multivibrator circuit generates a holding clock signal having a high pulse width of at least a half horizontal scanning period or more by using the falling edge of the input composite synchronization signal as a trigger while the holding clock signal is at a low level. I do. Further, the delay time from the falling edge of the composite synchronization signal to the rising edge of the shift clock signal is set to be longer than the low-level period of the horizontal synchronization pulse and shorter than the low-level period of the vertical synchronization pulse of the composite synchronization signal. .

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of a preferred embodiment of a field judgment circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a preferred embodiment of a field determination circuit according to the present invention. FIG.
FIG. 2 is a block diagram showing a detailed configuration of a delay circuit in FIG. FIG. 3 is a block diagram showing a detailed configuration of the determination circuit 4 in FIG. 4 is a timing chart when an odd field is input in the field determination circuit of FIG. 1, FIG. 5 is a timing chart when an even field is input in the field determination circuit of FIG. 1, and FIG. 6 is a differentiation circuit in the field determination circuit of FIG. 7 is a timing chart of the delay circuit in the field decision circuit of FIG. 1, and FIG. 8 is a timing chart of the monostable multivibrator circuit in the field decision circuit of FIG.

First, the field determination circuit shown in FIG. 1 includes a sync separation circuit 1, a delay circuit 2, a shift register circuit 3, a determination circuit 4, and a monostable multivibrator (MSMV) circuit 5.
And a clock generation circuit 6. The synchronization separation circuit 1 separates a composite synchronization signal b from an input composite video signal a. Composite sync signal b separated by sync separation circuit 1
Is input to the delay circuit 2, shift register circuit 3, and monostable multivibrator circuit 5. Delay circuit 2
Receives a clock signal g from the clock generation circuit 6 and inputs a shift clock signal c, which is an output thereof, to a clock (CLK) terminal of the shift register 3. From the shift register 3, shift register outputs d0 to d7 are input to the decision circuit 4, and the field identification signal e is obtained from the decision circuit 4. The MSMV circuit 5 receives the composite synchronizing signal b and outputs the held clock signal f,
Clock (CLK) terminal.

Next, as shown in FIG. 2, the delay circuit 2 includes a differentiating circuit 21 and a counter circuit 22.
The input composite synchronizing signal b is differentiated by the differentiating circuit 21 into a pulse for one cycle of the clock signal g input from the clock generating circuit 6, and is input to the counter circuit 22 as a differential pulse i. This counter circuit 22 is reset by the differential pulse i and counts by the clock signal g. Then, a shift clock signal c having a rise delayed by a predetermined time from the fall of the composite synchronization signal b is generated. As shown in FIG. 7, the delay time from the fall of the composite synchronization signal b to the rise of the shift clock signal c is longer than the low-level period of the horizontal synchronization pulse of the composite synchronization signal b and the low-level period of the vertical synchronization pulse. (About 5 μsec or more to about 27 μsec or less). In the field determination circuit shown in FIG. 1, the composite synchronizing signal b is fetched and bit-shifted every time the shift clock signal c rises in the shift register circuit 3 to obtain a shift register output d (ie, d0 to d7).

At this time, at the rise of the shift clock signal c, the high level portion of the horizontal synchronizing period and the equivalent pulse period of the composite synchronizing signal b and the low level portion of the vertical synchronizing period are captured. The shift register output d of the shift register circuit 3 is input to the determination circuit 4.

MSM in the field determination circuit of FIG.
The V circuit 5 outputs a holding clock signal f having a high-level period longer than a half horizontal scanning period and shorter than one horizontal scanning period, triggered by a fall of the composite synchronization signal b (about 40 μsec or more). ~ About 60 μs). At this time, as shown in FIG. 8, if the composite synchronizing signal b falls while the holding clock signal f is at a high level, the falling is ignored. The holding clock signal f output from the MSMV circuit 5 is input to the clock terminal of the determination circuit 4.

Next, as shown in FIG.
A pair of comparison circuits 41 and 42 and a pair of flip-flops (F
F) Circuits 43 and 44 and Set Reset (SR) Circuit 45
It consists of. The input shift register output d from the shift register 3 is applied to a pair of comparison circuits 41 and 42. “00000011” by one of the comparison circuits 41
And the other comparison circuit 42 detects the bit pattern of “10000001”. Comparison result j by comparison circuit 41 and comparison circuit 42
Is retimed by the FF circuits 43 and 44, respectively, and then given to the SR circuit 45 as a set signal ι and a reset signal m, respectively, to set and reset the SR circuit 45. The SR circuit 45 is set when the comparison result j is at a high level, and is reset when the comparison result k is at a high level. As a result, the SR circuit 45
Is high when an odd field is input, and is low when an even field is input. Therefore, it is possible to accurately determine the odd and even fields of the composite synchronization signal.

As described above, according to the preferred embodiment of the field determination circuit of the present invention, when determining the odd / even field, the phase relationship between the horizontal synchronization and the vertical synchronization is detected, and the state transition is performed by any method. Instead of detecting the difference, the difference between the pattern of the equivalent pulse and the pattern of the vertical synchronization period in the composite synchronization signal is detected. In this case, since it is not necessary to detect the phase in the horizontal scanning period, the configuration of the sync separation circuit may be a minimum necessary circuit configuration. Further, since a state machine that determines transition conditions from the past state and the current state is not required, the circuit configuration and the processing procedure can be simplified. Therefore, a field determination circuit having a simple configuration, a small circuit scale, and a simple processing procedure can be realized. The delay circuit, MSMV circuit, shift register circuit, and the like necessary for the preferred embodiment described above can be realized at low cost by using small-scale counters and registers.

It should be noted, however, that the preferred embodiments are merely illustrative of the invention and do not limit the invention in any way. It will be readily apparent to those skilled in the art that various modifications can be made in accordance with the particular application without departing from the spirit of the invention.

[0021]

As will be understood from the above description, according to the field determination circuit of the present invention, the circuit configuration is relatively simple, the circuit size is small, and the odd / even field is reliably determined by simple processing. Is practically remarkable.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a preferred embodiment of a field determination circuit according to the present invention.

FIG. 2 is a detailed configuration diagram of a specific example of the delay circuit shown in FIG.

FIG. 3 is a detailed configuration diagram of a determination circuit in FIG. 1;

FIG. 4 is a timing chart of an odd field for explaining the operation of the field determination circuit shown in FIG. 1;

FIG. 5 is a timing chart of an even field for explaining the operation of the field determination circuit shown in FIG. 1;

FIG. 6 is a timing chart illustrating the operation of the differentiating circuit shown in FIG. 2;

FIG. 7 is a timing chart illustrating an operation of a delay circuit used in the field determination circuit shown in FIG.

8 is a timing chart illustrating an operation of the monostable multivibrator used in the field determination circuit shown in FIG.

FIG. 9 is a block diagram showing a configuration of a conventional technique of a field determination circuit.

10 is a flowchart illustrating the operation of the conventional field determination circuit shown in FIG.

FIG. 11 is a configuration diagram of another conventional example of a field determination circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Synchronization separation circuit 2 Delay circuit 3 Shift register circuit 4 Judgment circuit 5 Multivibrator (MSMV) circuit 6 Clock generation circuit 21 Differentiation circuit 22 Counter circuit 41, 42 Comparison circuit 43, 44 Flip-flop (FF) circuit 45 Set reset (SR) ) Circuit a Composite video signal b Composite sync signal c Shift clock signal d Shift register output e Field identification signal f Holding clock signal g Clock signal i Differential pulse j, k Comparison result ι Set signal m Reset signal

Claims (6)

[Claims] 1. A synchronizing separation circuit for separating a composite synchronizing signal from an input composite video signal, and a shift clock signal having a rising edge delayed by a predetermined time from a falling edge of the composite synchronizing signal separated by the synchronizing separating circuit. A delay circuit that generates a multi-vibrator circuit that generates a holding clock signal having a pulse width of 0.5 times or more the horizontal scanning period from a falling edge of the composite synchronization signal; A shift register that captures and shifts each time the shift clock signal rises to obtain a shift register output, and holds the shift register output obtained by the shift register with a holding clock signal from the multivibrator circuit to generate the composite video signal. To determine the odd and even fields of Field determination circuit; and a judging circuit for outputting an identification signal. A pair of comparison circuits for detecting different bit patterns from the output of the shift register; and a set / reset circuit for performing a set / reset operation based on a comparison result by the pair of comparison circuits. 2. The field determination circuit according to claim 1, further comprising: determining an odd field and an even field of the composite video signal and outputting a field identification signal. 3. The judgment circuit according to claim 2, wherein said judgment circuit outputs a high-level judgment result output in an odd-numbered field and outputs a low-level judgment-result output in an even-numbered field. Field judgment circuit. 4. A delay circuit for differentiating an input composite synchronizing signal into a pulse for one cycle of a clock signal, wherein the delay circuit is reset by a differential pulse from the differential circuit.
2. The field determination circuit according to claim 1, further comprising: a counter circuit that counts with the clock signal and generates a shift clock signal having a rising edge delayed by a predetermined time from a falling edge of the composite synchronization signal. 5. The monostable multivibrator circuit according to claim 1, wherein a falling edge of said composite synchronizing signal input during a period when said holding clock signal is at a low level triggers a high pulse width of at least a half horizontal scanning period or more. 2. The field determination circuit according to claim 1, wherein a holding clock signal having the following is generated. 6. The delay time from the falling edge of the composite synchronization signal to the rising edge of the shift clock signal is as follows:
The field determination circuit according to claim 1, wherein the length of the field determination circuit is set to be longer than a low-level period of a horizontal synchronization pulse and shorter than a low-level period of a vertical synchronization pulse of the composite synchronization signal.