CN113138019B - Avalanche photodiode array-based reading circuit and photoelectric detector - Google Patents
Avalanche photodiode array-based reading circuit and photoelectric detector Download PDFInfo
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- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
- G01J1/44—Electric circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
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Abstract
The invention provides a reading circuit based on an avalanche photodiode array and a photoelectric detector, and relates to the technical field of photoelectric detection. The circuit comprises: the high-voltage isolation unit receives current generated by the avalanche photodiode and outputs the current to the quenching reset unit; the quenching reset unit receives the current output to the voltage comparison unit; the voltage comparison unit generates a first signal, the latch unit obtains a second signal, the logic unit performs logic operation to obtain a third signal and a fourth signal, and the quenching reset unit receives the third signal for quenching; receiving a fourth signal to reset the photon voltage value; the counter combines the third signal and the frame frequency signal in the other input signals of the logic unit to obtain the counting result. The reading circuit reduces the power consumption of the reading circuit and further shortens the quenching time, and has higher practical value.
Description
Technical Field
The invention relates to the technical field of photoelectric detection, in particular to a reading circuit based on an avalanche photodiode array and a photoelectric detector.
Background
At present, a reading circuit in a photoelectric detector based on an Avalanche photodiode (abbreviated as APD) structure mainly comprises a photoelectric signal receiving module, a quenching circuit, a time digital converter module (TDC), a data storage and output module and the like, when the Avalanche photodiode receives photons, Avalanche current is generated, the current triggers the quenching circuit and is transmitted to the time digital converter for timing, and after the counting of each pixel is completed, the Avalanche photodiode is controlled by an external time sequence to be uniformly output through the storage module. The quenching circuit needs to rapidly take the avalanche photodiode out of the avalanche state each time after the readout circuit completes the reception of a primary photon and induces an avalanche current, so as not to damage the avalanche photodiode due to a large current for a long time.
Quenching circuits are mainly divided into active quenching and passive quenching. The form of passive quenching is usually longer, and therefore the form of active quenching is more used at present. The active quenching circuit is connected to a fixed quenching level at the cathode of the avalanche photodiode through another independent quenching branch, and controls to turn on the switch through an independent signal, the independent signal can be an additional synchronous signal, and can also be fed back to the quenching branch through a loop after being generated by a circuit internal voltage detection module, so that the rapid quenching of the avalanche photodiode can be realized, the quenching time is mainly external delay time or loop delay time, and the speed is greatly improved compared with the passive quenching speed.
Circuits that quench with externally supplied control signals can be relatively difficult to synchronize their timing and are not suitable for use with multiple pixels or arrays, so quenching is currently mostly achieved by modular circuits that add feedback loops inside the pixels. In this way, the quenching time is mainly the delay of the feedback loop, but the current feedback loop is formed based on a large number of transistors, and the further reduction of the quenching time is very difficult while the circuit structure is more complicated. In addition, the large size of the transistor increases the area and power consumption of the whole readout circuit. Therefore, how to further reduce the quenching time while reducing the power consumption of the readout circuit is a problem to be solved.
Disclosure of Invention
The invention provides a readout circuit based on an avalanche photodiode array and a photodetector, and provides a readout circuit technical scheme with low power consumption and further shortened quenching time.
A first aspect of embodiments of the present invention provides a readout circuit based on an avalanche photodiode array, where the readout circuit includes: the high-voltage isolation circuit comprises a high-voltage isolation unit, a quenching reset unit, a voltage comparison unit, a latch unit and a logic unit, wherein the logic unit comprises a plurality of paths of input signals;
the high-voltage isolation unit receives current generated by an avalanche photodiode in the avalanche photodiode array and outputs the current to the quenching reset unit;
the quenching reset unit receives the current and outputs the current to the voltage comparison unit;
the voltage comparison unit converts the current into a corresponding photon voltage value and compares the magnitude relation between the photon voltage value and a reference voltage value to generate a first signal, wherein the first signal is used as an input signal of the latch unit;
the latch unit changes and latches the first signal to obtain a second signal, and the second signal is used as one path of input signal of the logic unit;
the logic unit performs logic operation on the second signal and other input signals to obtain a third signal and a fourth signal, the third signal is output to the quenching reset unit and the counter, and the fourth signal is output to the quenching reset unit;
wherein the quenching reset unit receives the third signal and quenches the avalanche photodiode;
the quenching reset unit receives the fourth signal and resets the photon voltage value;
and the counter is combined with the third signal and the frame frequency signal in other input signals of the logic unit to obtain a counting result.
Optionally, the high voltage isolation unit comprises: a high pressure resistant tube; the quenching reset unit includes: the PMOS tube, the first NMOS tube and the second NMOS tube;
one end of the high-voltage resistant tube is connected with the cathode of the avalanche photodiode, and the other end of the high-voltage resistant tube is respectively connected with the drain electrode of the PMOS tube and the drain electrode of the first NMOS tube;
the source electrode of the PMOS tube receives quenching voltage;
the grid electrode of the PMOS tube is connected with the grid electrode of the first NMOS tube and the logic unit respectively;
the grid electrode of the first NMOS tube is connected with the logic unit;
the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and the voltage comparison unit respectively;
the grid electrode of the second NMSO tube is connected with the logic unit;
and the source electrode of the second NMSO tube is grounded.
Optionally, the voltage comparing unit includes: an adjustable resistor, a comparator;
one end of the adjustable resistor is connected with the source electrode of the first NMOS tube, the drain electrode of the second NMOS tube and the first input end of the comparator respectively;
the other end of the adjustable resistor is grounded;
a second input terminal of the comparator receives the reference voltage value;
the output end of the comparator is connected with the latch unit, and the output end of the comparator outputs the first signal.
Optionally, the latch unit includes: the digital-to-analog converter comprises a D flip-flop, a first NOR gate, a second NOR gate and a NOT gate;
a first input end of the D flip-flop is respectively connected with an output end of the comparator and a first input end of the first NOR gate;
a second input end of the D trigger receives a power-on detection signal;
the output end of the D flip-flop is connected with the second input end of the first NOR gate;
a third input terminal of the first nor gate is connected with an output terminal of the second nor gate;
the output end of the first nor gate is respectively connected with the first input end of the second nor gate and the logic unit, and the output end of the first nor gate outputs the second signal;
a second input end of the second NOR gate is connected with an output end of the NOR gate;
and the input end of the NOT gate is connected with the logic unit.
Optionally, the logic unit includes: the first AND gate, the second AND gate, the OR gate and the third NOR gate;
a first input end of the first AND gate receives the frame frequency signal, and a rising edge of the frame frequency signal represents the emission time of photons;
the second input end of the first AND gate is respectively connected with the output end of the first NOR gate, the first input end of the second NOR gate and the first input end of the second AND gate;
the output end of the first AND gate is connected with the first input end of the OR gate;
the second input end of the second AND gate is connected with the input end of the NOT gate, and the second input end of the second AND gate receives the delay signal;
the output end of the second AND gate is connected with the second input end of the third NOR gate;
a first input end of the third NOR gate and a second output end of the OR gate receive a detection switch control signal;
the output end of the OR gate outputs the third signal;
an output of the third nor gate outputs the fourth signal.
Optionally, the delay signal is a signal generated by delaying the frame frequency signal by one clock;
the power-on detection signal is a signal generated by reversely delaying a clock by a reset signal of the D trigger, and the reset signal is generated and sent by a control circuit and is used for resetting the working state of the D trigger;
the detection switch control signal is a signal generated by delaying the reset signal by two clocks.
Optionally, the third signal is used as a cutoff signal of the counter;
and the counter counts the time from the rising edge of the frame frequency signal to the falling edge of the third signal to obtain a counting result, and the counting result represents the flight time length of the photons from the emission to the reception of the photons by the avalanche photodiode.
Optionally, the high pressure resistant tube comprises: a high voltage transistor;
the high-voltage transistor isolates the high voltage generated by the cathode of the avalanche photodiode;
the high-voltage transistor is simultaneously controlled by a signal output by the output end of the D trigger and a control signal sent by the control circuit.
Optionally, when the readout circuit is initially powered up, the D flip-flop automatically checks to mark whether each avalanche photodiode in the avalanche photodiode array is damaged or not at the rising edge of the power-up detection signal, and the D flip-flop outputs a high level signal to indicate that the avalanche photodiode is damaged, and a low level signal to indicate that the avalanche photodiode is not damaged.
A second aspect of embodiments of the present invention provides a photodetector, including: an avalanche photodiode and a readout circuit as claimed in any one of the first aspect.
According to the reading circuit based on the avalanche photodiode array, the high-voltage isolation unit receives current generated by the avalanche photodiodes in the avalanche photodiode array and outputs the current to the quenching reset unit, and the quenching reset unit receives the current and outputs the current to the voltage comparison unit; the voltage comparison unit converts the current into a corresponding photon voltage value and compares the magnitude relation between the photon voltage value and a reference voltage value to generate a first signal; the latch unit changes and latches the first signal to obtain a second signal; and the logic unit performs logic operation on the second signal and other input signals to obtain a third signal and a fourth signal. The quenching reset unit receives the third signal and quenches the avalanche photodiode; the quenching reset unit receives the fourth signal and resets the photon voltage value to ensure the normal work of the reading circuit.
Because the generation of the third signal is inside the readout circuit, the influence of an external control signal on the quenching circuit is avoided, and the third signal is generated by using only the logic unit to realize quenching, the quenching time depends on the operation of the logic circuit and the response time of the voltage comparison unit, and compared with the current modularly designed circuit, the delay between the signals is also shorter, so that the quenching time is further reduced. And the structure of the logic circuit is simple, and the area and the power consumption of components are smaller than those of transistors, so that the area and the power consumption of the whole reading circuit are reduced. The reading circuit based on the avalanche photodiode array further shortens the quenching time while reducing the power consumption of the reading circuit, and has higher practical value.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a modular schematic diagram of a readout circuit based on an avalanche photodiode array in accordance with an embodiment of the present invention;
FIG. 2 is a schematic diagram of a preferred readout circuit based on an avalanche photodiode array in an embodiment of the present invention;
FIG. 3 is a timing diagram illustrating power-up detection of the readout circuit according to an embodiment of the present invention;
fig. 4 is a timing diagram illustrating normal operation of the readout circuit according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, there is shown a modular schematic diagram of a readout circuit based on an avalanche photodiode array, the readout circuit including: the high-voltage isolation circuit comprises a high-voltage isolation unit, a quenching reset unit, a voltage comparison unit, a latch unit and a logic unit, wherein the logic unit comprises a 1-path and a 2-path … of multi-path input signals; when the avalanche photodiode in the avalanche photodiode array receives photons, the avalanche photodiode can generate large current, the high-voltage isolation unit can receive the large current generated by the avalanche photodiode in the avalanche photodiode array, and the large current flows to the quenching reset unit; after receiving the large current, the quenching reset unit flows to the voltage comparison unit; the voltage comparison unit converts the large current into a photon voltage value corresponding to the large current, and compares the magnitude relation between the photon voltage value and a reference voltage value to generate a first signal which is used as an input signal of the latch unit; the latch unit changes and latches the first signal to obtain a second signal, and the second signal is used as one path of input signal of the logic unit; and the logic unit performs logic operation on the second signal and other input signals to obtain a third signal and a fourth signal, wherein the third signal is output to the quenching reset unit and the counter, and the fourth signal is output to the quenching reset unit.
After the quenching reset unit receives the third signal, the avalanche photodiode can be quenched; meanwhile, the quenching reset unit also receives a fourth signal, so that the photon voltage value can be reset; and the counter combines the third signal and the frame frequency signal in other input signals of the logic unit to obtain a counting result, and the counting result represents the flight time length of the photons from the emission to the receiving of the avalanche photodiode. Each avalanche photodiode and its corresponding readout circuit are processed until the readout circuit finishes counting all pixels.
Referring to fig. 2, a schematic diagram of a preferred readout circuit based on an avalanche photodiode array in an embodiment of the present invention is shown, where fig. 2 includes: high-voltage transistor MHPMOS transistor MQA first NMOS transistor MCA second NMOS transistor MRAdjustable resistance RSComparator UA, D trigger DFA first NOR gate NOR1, a second NOR gate NOR2, a NOT gate NOT, a first AND gate AND1, a second AND gate AND2, an OR gate OR, a third NOR gate NOR3, AND a Counter.
The high pressure resistant pipe in the embodiment of the invention may include: high-voltage transistor MH. High-voltage transistor MHThe high voltage generated at the cathode of the avalanche photodiode APD can be isolated so that a high voltage avalanche photodiode can be used, for example, a 60V avalanche photodiode. The higher voltage can enable the reading circuit to have higher precision, and the avalanche photodiodes adopted at present are basically low-voltage diodes, so that the reading circuit of the embodiment of the invention has higher precision compared with the current reading circuit.
High-voltage transistor MHIs controlled by the signal Q output by the output of the D flip-flop D and by a control signal sent by a control circuit (not shown in fig. 2). I.e. the signal VH is simultaneously controlled by the signal Q and a control signal sent by a control circuit (not shown in fig. 2). High-voltage transistor M at high level of signal VHHOn, high voltage transistor M at low level of signal VHHAnd (6) turning off.
The quenching reset unit in the embodiment of the invention may include: PMOS tube MQA first NMOS transistor MCA second NMOS transistor MR(ii) a High-voltage transistor MHOne end of the high-voltage transistor M is connected with the cathode of the avalanche photodiode APDHAnother end of the PMOS transistor MQDrain electrode of (1), first NMOS tube MCThe drain electrodes of the first and second electrodes are respectively connected; PMOS tube MQReceives the quench voltage Vqch; PMOS tube MQGrid and first NMOS transistor MCThe grid of the logic unit and the output end of the OR gate OR in the logic unit are respectively connected; first NMOS transistor MCIs also connected to the output of the OR gate OR in the logic cell; first NMOS transistor MCSource electrode of and the second NMOS transistor MRAdjustable resistor R in the drain and voltage comparison unitSIs connected to the first input terminal of the comparator UA; second NMSO tube MRIs connected to the output of a third NOR gate NOR3 in the logic cell; second NMSO tube MRIs connected to ground GND. The operation principle of the quenching reset unit is explained below, and is not described in detail.
The voltage comparison unit in the embodiment of the present invention may include: adjustable resistor RSA comparator UA; adjustable resistor RSOne end of (D) and the first NMOS tube MCSource electrode of the first NMOS transistor MRThe drain of the comparator UA and the first input end of the comparator UA are respectively connected; adjustable resistor RSThe other end of the first and second electrodes is grounded GND; a second input end of the comparator UA receives a reference voltage value Vref; output end of comparator UA and D trigger D in latch unitFIs connected to the first input of the comparator UA, and the output of the comparator UA outputs the first signal. The working principle of the voltage comparison unit is described below, and is not described in detail.
The latch unit in the embodiment of the present invention may include: d flip-flop DFA first NOR gate NOR1, a second NOR gate NOR2, a NOT gate NOT; a first input end of the D flip-flop D is connected to an output end of the comparator UA and a first input end of the first NOR gate NOR1, respectively; i.e. the first signals are transmitted to the D flip-flops D simultaneouslyFAnd a first NOR gate NOR 1. D flip-flop DFReceives the power-on detection signal CHdN; d flip-flop DFIs connected to a second input of the first NOR gate NOR 1; d flip-flop DFIt is also necessary to receive a reset signal CH for resetting the D flip-flop DF。
A third input terminal of the first NOR gate NOR1 is connected to an output terminal of the second NOR gate NOR 2; the output terminal of the first NOR gate NOR1 is connected to the first input terminal of the second NOR gate NOR2 AND the second input terminal of the first AND gate AND1 in the logic unit, respectively, AND the output terminal of the first NOR gate NOR1 outputs the second signal X; the output end of a second input end NAND gate NOT of the second NOR gate NOR2 is connected; the input of the NOT-gate NOT is connected to a second input of a second AND-gate AND2 in the logic unit. The working principle of the latch unit is described below and will not be described in detail.
The logic unit in the embodiment of the present invention may include: a first AND gate AND1, a second AND gate AND2, an OR gate OR, AND a third NOR gate NOR 3; a first input terminal of the first AND gate AND1 receives a frame frequency signal FI, a rising edge of which represents a photon emission time; which is input from the outside. A second input terminal of the first AND gate AND1 is connected to an output terminal of the first NOR gate NOR1, a first input terminal of the second NOR gate NOR2, AND a first input terminal of the second AND gate AND2, respectively; the second input of the first AND-gate AND1 AND the first input of the second AND-gate AND2 each receive the second signal X.
The output terminal of the first AND gate AND1 is connected to a first input terminal of the OR gate OR; a second input terminal of the nand gate NOT of the second AND gate AND2 is connected, AND a second input terminal of the second AND gate AND2 receives the delay signal FId; the output terminal of the second AND gate AND2 is connected to the second input terminal of the third NOR gate NOR 3; a first input terminal of the third NOR gate NOR3 and a second output terminal of the OR gate OR each receive the detection switch control signal CHdd; the output of the OR gate OR outputs a third signal S1; an output terminal of the third NOR gate NOR3 outputs a fourth signal S2. The working principle of the logic unit is described below, and is not described in detail.
In the embodiment of the present invention, the latch unit is designed to change and latch the first signal output by the comparator UA; another aspect is to enable detection at initial power up of the readout circuit to detect whether each avalanche photodiode in the array of avalanche photodiodes is damaged. Specifically, the method comprises the following steps: when the readout circuit is initially powered on, the avalanche photodiode array does not perform any counting operation on the pixels to be counted, and the D flip-flop DFAn automatic check is performed with the output of comparator UA as D flip-flop DFInput, marking each APD in the APD array as damaged or not at the rising edge of the detection signal CHdN, and marking with D trigger DFBased on the high and low levels of the output signal Q, the signal Q is taken as a high level signal to represent that the corresponding APD is damaged, and the signal Q is taken as a low level signal to represent that the corresponding APD is not damaged. Because an APD is damaged, the readout circuit corresponding to the APD cannot normally operate naturally, and therefore, whether the APD is damaged is equivalent to whether the readout circuit corresponding to the APD can normally operate. Generally, when the readout circuit is initially powered up, that is, when the readout circuit is in an initial state and is operating normally, the signal Q is 0 (low level), and the signal Q is 1 (high level) to indicate that a certain APD is damaged, and the corresponding readout circuit cannot operate normally.
Referring to FIG. 3, a timing diagram of power-up detection of the readout circuit in the embodiment of the invention is shown when D flip-flop D is turned onFWhen automatic check is carried out, firstly, the external control circuit sends a reset signal CH to the D trigger DFResetting is carried out, and simultaneously the external control circuit sends a signal with VH equal to 1 high level to turn on the high-voltage transistor MH. The power-on detection signal CHdN is a reset signal CH and reversely delays one clock to generate, because the APD does not receive photons and only weak dark current flows through the APD if the APD is not damaged, the adjustable resistor RSThe voltage value generated above is very small, certainly not larger than the reference voltage value Vref, the comparator UA cannot be overturned, the first signal output by the comparator UA is 0, and then the D trigger is triggeredDFThe output signal Q is 0, the second signal X is 1 after the latch structure formed by the first NOR gate NOR1, the second NOR gate NOR2 and the NOT gate NOT is changed, FI is 0 and FId is 0 because of the absence of the frame frequency signal FI and the delay signal FId, and the detection switch signal control signal CHdd is a signal generated by delaying the reset signal CH by two clocks, and after the logic operation of the logic unit, the third signal S1 is 1 and the fourth signal S2 is 0, the whole readout circuit operates normally.
In another case: when D triggers DFWhen automatic check is carried out, firstly, the external control circuit sends a reset signal CH to the D trigger DFResetting is carried out, and simultaneously the external control circuit sends a signal with VH equal to 1 high level to turn on the high-voltage transistor MH. The power-on detection signal CHdN is generated by delaying a reset signal CH by one clock in a reverse direction, and because the APD does not receive photons and if the APD is damaged, a large current directly flows through the APD, the adjustable resistor RSThe voltage value generated in the D flip-flop D is very large and is larger than the reference voltage value Vref, the comparator UA is overturned, the first signal output by the comparator UA is 1FThe output signal Q is 1, the signal Q is changed into a second signal X is 0 through a latch structure formed by the first NOR gate NOR1, the second NOR gate NOR2 and the NOT gate NOT, and the signal Q is 1, which controls VH to 0, so that the high-voltage transistor M is enabled to be 1HOff, high voltage transistor MHAnd when the circuit is turned off, the whole reading circuit cannot work normally naturally.
By the power-up detection method, which APDs in the APD array are damaged and which APDs are normally not damaged can be determined. When detecting whether the APD is damaged, the normal undamaged APD and the corresponding reading circuit can still work normally.
In the embodiment of the present invention, after the power-on detection of the readout circuit is completed, the working state of counting the pixels can be entered, and with reference to the normal working timing diagram shown in fig. 4, the working process of the readout circuit is as follows:
when the readout circuit in the normal operation state starts to operate, the external control circuit first sends VH equal to 1 so that the high-voltage transistor M is turned onHConducting, opening a detection path, after a clock delay, the S1 is equal to 1, the S2 is equal to 0, entering a state to be detected, and at the moment, the PMOS transistor MQTurn off, the first NMOS transistor MCConducting the second NMOS transistor MRIs turned on in the delay from S2 ═ 1 to S2 ═ 0, which is mainly to drain the first NMOS transistor MCWhen the NMOS transistor is turned on, the drain terminal of the NMOS transistor accumulates charges, so that the voltage value of the first input terminal VX of the comparator UA passes through the second NMOS transistor MRThe reset state is maintained, i.e. the voltage value of the first input VX of the comparator UA is made 0, to avoid causing a premature inversion of the comparator UA resulting in miscounting. While the Counter is reset during this delay time and starts counting. When S1 is equal to 1 and S2 is equal to 0, the PMOS transistor MQTurn off, the first NMOS transistor MCConducting the second NMOS transistor MRAnd (4) turning off, wherein the VX voltage value is 0.
When the APD receives a photon, it generates a large current, which passes through the first NMOS transistor M that is turned onCAt an adjustable resistance RSWhen the VX voltage rises to exceed the reference voltage Vref, the comparator UA flips, the comparator outputs a first signal 1, which passes through the latch unit to become a second signal X, whose value is 0, i.e., X equals 0.
Since the frame frequency signal FI is 1 when the frame frequency signal FI is present, and the delay signal FId is a signal generated by delaying the frame frequency signal FI by one clock, FI is 1, FId is 1, and the detection switch signal control signal CHdd is 0 (CHdd is 0 because the power-on detection is completed at this time), the third signal S1 is 0, and the fourth signal S2 is 1 when the logic operation of the logic unit is performed. When S1 is equal to 0 and S2 is equal to 1, the S1 signal is simultaneously transmitted to the PMOS transistor MQA first NMOS transistor MCAnd the Counter, S2 signal is transmitted to the second NMOS transistor MRThus, PMOS transistor MQConducting the first NMOS transistor MCTurn off, second NMOS transistor MRAnd conducting.
PMOS tube MQThe voltage of an ADP cathode is equal to a quenching voltage Vqch when the transistor is switched on, APD active quenching is realized, and the second NMOS transistor MRIs conducted to enable the voltage value of VXResetting to 0 corresponds to the comparator UA being reset. And S1 is used as a cutoff signal of the Counter, so that the Counter ends counting and stores the result in the Counter, and the Counter counts the time from the rising edge of the frame frequency signal FI to the falling edge of the third signal S1 to obtain a counting result, which represents the time length of the flight of the photons from the emission to the reception by the APD. After the counting is stopped, the Counter data is kept unchanged, and the writing into the memory of each pixel is controlled by the Write signal after the falling edge of the frame frequency signal FI. Wherein the Write signal is generated from the frame rate signal FI. Each undamaged APD works according to the working process based on the corresponding reading circuit, and therefore counting of all pixels can be achieved.
In summary, the readout circuit according to the embodiment of the present invention only needs the external control circuit to provide the frame frequency signal FI and the reset signal CH, and the remaining signal timings are implemented inside the readout circuit, for example, delaying one clock or delaying two clocks. And the frame frequency signal FI and the reset signal CH are respectively sent when the reading circuit starts counting and is electrified for detection, so that the frame frequency signal FI and the reset signal CH are not interfered with each other, and the time sequences of the frame frequency signal FI and the reset signal CH do not need to be synchronously controlled, thereby greatly reducing the difficulty of external signal synchronous control. And the generation of the third signal S1 and the fourth signal S2 depends on the logic unit inside the readout circuit, the influence of the external control signal on the quenching circuit is avoided, the quenching is realized by the third signal, the reset is realized by the fourth signal, the quenching time of the quenching circuit mainly depends on the delay of the comparator and the operation of the logic circuit, the avalanche signal is responded by the high-speed comparator, the detection threshold is lower compared with the detection method using a simple inverter or other detection methods, the response to the avalanche signal is faster, and therefore the quenching time can be further shortened. In addition, only three transistors are used in the readout circuit and are independently designed, compared with a circuit formed by current modularized units, the area and power consumption of components are smaller, the delay between signals is also shorter, and the main power consumption is used for a comparator to improve the quenching speed, so that the quenching time is further shortened. And the structure of the logic circuit is simple, the area and the power consumption of components are small compared with the circuit with a modular design, and the structure of the whole reading circuit is more concise compared with the reading circuits of other feedback loops, so that the area and the power consumption of the whole reading circuit are reduced. The reading circuit based on the avalanche photodiode array further shortens the quenching time while reducing the power consumption of the reading circuit, and has higher practical value.
Based on the readout circuit, an embodiment of the present invention further provides a photodetector, where the photodetector includes: an avalanche photodiode and a readout circuit as described in any of the above.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (7)
1. A readout circuit based on an avalanche photodiode array, the readout circuit comprising: the high-voltage power supply comprises a high-voltage isolation unit, a quenching reset unit, a voltage comparison unit, a latch unit and a logic unit, wherein the logic unit comprises a plurality of paths of input signals;
the high-voltage isolation unit receives current generated by an avalanche photodiode in the avalanche photodiode array and outputs the current to the quenching reset unit;
the quenching reset unit receives the current and outputs the current to the voltage comparison unit;
the voltage comparison unit converts the current into a corresponding photon voltage value and compares the magnitude relation between the photon voltage value and a reference voltage value to generate a first signal, wherein the first signal is used as an input signal of the latch unit;
the latch unit changes and latches the first signal to obtain a second signal, and the second signal is used as one path of input signal of the logic unit;
the logic unit performs logic operation on the second signal and other input signals to obtain a third signal and a fourth signal, the third signal is output to the quenching reset unit and the counter, and the fourth signal is output to the quenching reset unit;
wherein the quenching reset unit receives the third signal and quenches the avalanche photodiode;
the quenching reset unit receives the fourth signal and resets the photon voltage value;
the counter is combined with the third signal and frame frequency signals in other input signals of the logic unit to obtain a counting result;
the quenching reset unit includes: the PMOS transistor, the first NMOS transistor and the second NMOS transistor;
the drain electrode of the PMOS tube and the drain electrode of the first NMOS tube are respectively connected with the high-voltage isolation unit;
the source electrode of the PMOS tube receives quenching voltage;
the grid electrode of the PMOS tube is connected with the grid electrode of the first NMOS tube and the logic unit respectively;
the grid electrode of the first NMOS tube is connected with the logic unit;
the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and the voltage comparison unit respectively;
the grid electrode of the second NMSO tube is connected with the logic unit;
the source electrode of the second NMSO tube is grounded;
the voltage comparison unit includes: an adjustable resistor and a comparator;
one end of the adjustable resistor is connected with the source electrode of the first NMOS tube, the drain electrode of the second NMOS tube and the first input end of the comparator respectively;
the other end of the adjustable resistor is grounded;
a second input terminal of the comparator receives the reference voltage value;
the output end of the comparator is connected with the latch unit, and the output end of the comparator outputs the first signal;
the latch unit includes: the digital-to-analog converter comprises a D flip-flop, a first NOR gate, a second NOR gate and a NOR gate;
a first input end of the D flip-flop is respectively connected with an output end of the comparator and a first input end of the first NOR gate;
a second input end of the D trigger receives a power-on detection signal;
the output end of the D flip-flop is connected with the second input end of the first NOR gate;
a third input terminal of the first nor gate is connected with an output terminal of the second nor gate;
the output end of the first nor gate is respectively connected with the first input end of the second nor gate and the logic unit, and the output end of the first nor gate outputs the second signal;
a second input end of the second NOR gate is connected with an output end of the NOR gate;
the input end of the NOT gate is connected with the logic unit;
the logic unit includes: the first AND gate, the second AND gate, the OR gate and the third NOR gate;
a first input end of the first AND gate receives the frame frequency signal, and a rising edge of the frame frequency signal represents the emission time of photons;
the second input end of the first AND gate is respectively connected with the output end of the first NOR gate, the first input end of the second NOR gate and the first input end of the second AND gate;
the output end of the first AND gate is connected with the first input end of the OR gate;
the second input end of the second AND gate is connected with the input end of the NOT gate, and the second input end of the second AND gate receives the delay signal;
the output end of the second AND gate is connected with the second input end of the third NOR gate;
a first input end of the third NOR gate and a second output end of the OR gate receive a detection switch control signal;
the output end of the OR gate outputs the third signal;
an output of the third nor gate outputs the fourth signal.
2. The sensing circuit of claim 1, wherein the high voltage isolation unit comprises: a high pressure resistant tube; one end of the high-voltage resistant tube is connected with the cathode of the avalanche photodiode, and the other end of the high-voltage resistant tube is connected with the drain electrode of the PMOS tube and the drain electrode of the first NMOS tube respectively.
3. The readout circuit of claim 1, wherein the delay signal delays the frame rate signal by a clock generated signal;
the power-on detection signal is a signal generated by reversely delaying a clock by a reset signal of the D trigger, and the reset signal is generated and sent by a control circuit and is used for resetting the working state of the D trigger;
the detection switch control signal is a signal generated by delaying the reset signal by two clocks.
4. The readout circuit of claim 1, wherein the third signal is a cutoff signal of the counter;
and the counter counts the time from the rising edge of the frame frequency signal to the falling edge of the third signal to obtain a counting result, and the counting result represents the flight time length of the photons from the emission to the reception of the photons by the avalanche photodiode.
5. The sensing circuit of claim 2, wherein the high voltage tolerant transistor comprises: a high voltage transistor;
the high-voltage transistor isolates the high voltage generated by the cathode of the avalanche photodiode;
the high-voltage transistor is simultaneously controlled by a signal output by the output end of the D trigger and a control signal sent by the control circuit.
6. The readout circuit of claim 1, wherein upon initial power-up of said readout circuit, said D flip-flop automatically checks to flag each avalanche photodiode in said array of avalanche photodiodes as being defective at a rising edge of said power-up detection signal, wherein a high signal output by said D flip-flop indicates that said avalanche photodiode is defective, and a low signal output by said D flip-flop indicates that said avalanche photodiode is not defective.
7. A photodetector, characterized in that the photodetector comprises: an avalanche photodiode and a readout circuit as claimed in any one of claims 1 to 6.
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| US5194727A (en) * | 1989-07-03 | 1993-03-16 | The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland | Avalanche photodiode quenching circuit wtih resetting means having a second amplifier |
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| CN110785932A (en) * | 2017-06-23 | 2020-02-11 | ams有限公司 | Avalanche diode arrangement and method for controlling an avalanche diode arrangement |
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| US5194727A (en) * | 1989-07-03 | 1993-03-16 | The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland | Avalanche photodiode quenching circuit wtih resetting means having a second amplifier |
| CN202092781U (en) * | 2011-05-16 | 2011-12-28 | 华东师范大学 | Balanced type active suppression circuit suitable for multi-pixel photon counter |
| CN107091687A (en) * | 2017-05-05 | 2017-08-25 | 重庆理工大学 | A kind of APD single-photon detectors circuit and avalanche signal discriminating method |
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