KR100429266B1 - Logic circuit for signal process of synchronous transfer module reframed data - Google Patents

Abstract

The present invention relates to signal processing of a leaf reamer, which is one of the blocks in the ASIC included in the synchronous transmission modules (STM-1 and STM-4), among the dependent signals of the 2.5G synchronous digital layer (SDH) system.

The present invention detects the last A1 byte and the first A2 byte instead of detecting the entire frame byte in each frame of the STM-1 / 4 signal or the last A1 byte of the frame byte and the first A2 byte of the frame byte. After that, it configures the logic circuit which detects the last A2 byte again and makes re-ramming, so that the ASIC is more reliable and accurate signal processing function through simpler logic circuits in error-prone or random signal transmission environment. Provided are a signal processing logic circuit and a method of a synchronous transfer module leaf reamer that can be used in both STM-1 / 4 units.

Description

SIGNAL CIRCUIT PROCESSING CIRCUIT OF SYNCHRONIC TRANSFER MODULE REFRAMER {LOGIC CIRCUIT FOR SIGNAL PROCESS OF SYNCHRONOUS TRANSFER MODULE REFRAMED DATA}

The present invention is an on-demand type included in a synchronous transfer module (STM) and a STM-4 (STM-4) unit among dependent signals of a 2.5G (Giga) Synchronous Digital Hierachy (SDH) system. TECHNICAL FIELD The present invention relates to signal processing of a reframer, one of blocks in an application specific integrated circuit (ASIC), and more reliable and accurate signals using simpler logic circuits, especially in an error or random signal transmission environment. It is a signal processing logic circuit of the leaf reamer of a synchronous transmission module that allows the ASIC to be used in both STM-1 and STM-4 units through processing functions. As a standard technology for transmission, it is internationally equivalent to SONET (Synchronous Optical Network). Both technologies are faster and less expensive to access networks than traditional PDH (Plesiochronous Digital Hierarchy) devices. Also in digital phone transmission, 'synchronous' means that the bits belonging to one call all move in one transmission frame. 'Plesiochronous' means a call that is nearly synchronous or that one call must be extracted from one or more transmission frames. SDH uses the following STM-n series and speed. That is, STM-1 at 155 Mbps, STM-4 at 622 Mbps, STM-16 at 2.488 Gbps, and STM-64 at 10 Gbps, and the data transmission has an STM-n frame structure. This is done when the signal is transmitted serially from the first bit in the upper left to the last bit in the lower right. When such a signal is repeatedly transmitted through an optical cable, the repetition of such a frame is defined as transmission of an STM-n level signal. This frame data structure has a payload carrying data every frame and a value suitable for each function. It consists of overhead. Here, the frame pattern bytes indicated by A1 and A2 in the overhead have a fixed value. The values are binary numbers A1 and A2, respectively, where A1 is '11110110 (F6, the first four digits F, the last four digits 6, hexadecimal)', and A2 is 00101000 (28). The A1 and A2 values, which are the frame bytes, have a fixed value every frame, and thus serve as a criterion for finding a frame. Therefore, in the STM-1 / 4 class, 'A1' is used to transmit and receive data in a normal manner. ',' A2 'to have the values of' 11110110 'and' 00101000 'at each corresponding position. Then, the criteria for aligning each frame by finding the position corresponding to A1 and A2 in the receiving part, that is, frame synchronization By using the bytes for, we find the location of each overhead. At this time, it finds the overhead for each function and performs the function required for transmission / reception. In order to find the A1 and A2 values, all the input signals must be searched sequentially, and the A1 and A2 positions must be found first to smoothly perform the transmission and reception functions at overhead. The reamer of the STM-1 / 4 signal in the transmission mode receiving apparatus has a structure that detects A1A2 bytes indicating the start position of each frame.

The reamer of this synchronous transfer mode is as shown in Fig. 1. Referring to Fig. 1, the comparator 1 compares input data with a reference FAS byte (Frame Alignment Signal). After detecting the FAS byte A1A2 among the input data, a frame pulse (FP) is generated to find a frame start position of the corresponding signal.

In this case, the frame reordering unit (Re-Aligner) 2 when the frame pulse (FP) for finding the start position of the frame from the comparator 1 is inputted, the frame realignment unit (2) rearranges the frames of the input data using the input frame pulse. (reframed data) will be displayed.

Since such re-framer there is detected the A1A2 bytes indicating the start position of each frame, in the case of the STM-1 signal in the case of each frame begins with a "A1A1A1A2A2A2", and STM-4 has to begin with a "A1A1A1A1A1A1A1A1A1A1A1A1A2A2A2A2A2A2A2A2A2A2A2A2", The relayer searches the received signal to detect each A1A2 byte and then finds the start position of the frame. However, in the prior art, there may be various structures and algorithms for finding A1A2. However, the most common structure would be to find all the A1A2 bytes in its entirety. In case of finding all the A1A2 bytes, as shown in FIG. In-frame state is declared when frame "A1A1A1A2A2A2" byte can be searched for two consecutive frames at the position, and the frame pulse (FP) is generated to inform the frame realignment unit 2 of the start position of the frame. . That is, when the value to be retrieved appears in succession (for example, 250us) at one frame interval, this is called an in-frame state. If the values of '11110110' and '00101000' are not continuously searched within a predetermined time (for example, 3 ms) at intervals of one frame, this is called an out of frame.

And, in case of STM-4, comparator 1 detects 24 bytes of "A1A1A1 A1A1A1 A1A1A1 A1A1A1A2A2A2 A2A2A2 A2A2A2 A2A2A2" and retrieves two consecutive frames at the same position "A1A1A1 A1A1 A1A2A2A2A2A2A2A2A2A2A2A2A2 The frame pulse FP is generated while declaring the clinical condition to inform the frame realignment unit 2 of the starting position of the frame. In this way, the comparator of the leaf reamer is frame-by-frame to find the position of A1 and A2 in the received signal. Since it is not a divided signal, all incoming signals must be searched sequentially. The A1 and A2 bytes of the retrieved total bytes are used as a criterion indicating the start of each frame.

However, in the above case, when the received data is in an error environment, the performance of reframing is not only deteriorated. In addition, as shown in FIG. Accordingly, in order to solve the above problem, conventionally, a structure as shown in FIG. 3 that finds the last A1 byte (last A1) and the first A2 byte (first A2) among the entire frame bytes is provided to find the starting point of each frame. To find the last A1 byte and the first A2 byte.

However, the above structure has the advantage of improving performance and reducing the number of logic gates in the reframing of received data in an error environment. It has the disadvantage of poor accuracy.

Accordingly, an object of the present invention is to detect the entire frame byte in each frame of an STM-1 / 4 signal or to detect the last A1 byte and the first A2 byte. By configuring the logic circuit that detects the last A1 byte and the first A2 byte and then detects the last A2 byte again to perform reframing, simpler logic circuits are used in an error-prone or random signal transmission environment. The aim is to provide a signal processing logic circuit for the synchronous transfer module leaf-raiser that allows the ASIC to be used in both STM-1 / 4 units with more reliable and accurate signal processing.

1 is a signal processing logic circuit diagram of a synchronous transfer module leaf reamer applied in the related art.

2 is a first embodiment of a frame byte detection structure through signal processing logic in a conventional relayer;

3 is a second embodiment of a frame byte detection structure through signal processing logic in a conventional relayer;

4 is a signal processing logic circuit diagram of a synchronous transmission module leaf reamer according to one embodiment of the present invention;

5 is a structural structure of frame byte detection through the signal processing logic circuit of the present invention.

The signal processing logic circuit of the synchronous transmission module leaf reamer according to the present invention for achieving the above object, in the relay of the synchronous transmission mode receiver for transmitting and receiving a signal with the transmitter, alignment of the reference frame in the random data received and input A first comparator for generating a first frame pulse for indicating a frame start position of a corresponding signal when the last A1 byte and the first A2 byte of the whole framing bytes are detected after comparing with the byte; A position adjusting unit which generates a second frame pulse after shifting the data position of the first frame pulse generated from the first comparator to the last A2 byte position of the framing byte; A second comparator for searching the input data at the second frame pulse position generated by the position adjusting unit, comparing the input data with a reference A2 byte signal, and generating a third frame pulse when the last A2 byte signal of the framing byte is detected; And a frame rearranging unit which finds a starting position of the received and input data based on the third frame pulse generated from the second comparator and rearranges the input data.

Preferably, the second comparator detects the last A2 byte from the data input at the second frame pulse position shifted by the position adjusting unit, searches for the presence or absence of an error of the last A2 byte compared to the reference A2 byte, and there is no error. In this case, the third frame pulse is generated and transmitted to the frame reordering unit.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 4 is a signal processing logic circuit diagram of a synchronous transmission module leaframer according to an embodiment of the present invention, and FIG. 5 is a structure of frame byte detection through the signal processing logic circuit of the present invention.

As shown in FIGS. 4 and 5, the first comparator 10 generating a first frame pulse FP1 for detecting a frame start position of a corresponding signal after detecting a FAS byte among received input data. )Wow; A position adjusting unit 20 for shifting and adjusting the position of the first frame pulse FP1 generated from the first comparator 10 to the last A2 byte and generating the second frame pulse FP2 at the adjusted position; ; A second comparator (30) for generating a second frame pulse (FP3) after retrieving the last A2 byte from the input data at the position of the second frame pulse (FP2) generated by the position adjusting unit (20); The frame realignment unit 40 rearranges the received input data based on the position of the third frame pulse FP3 generated from the second comparator 30.

That is, the present invention does not detect the entire frame byte (A1A2) or detect the last A1 byte and the first A2 byte in each frame of the STM-1 / 4 signal through the simple logic circuit as described above. After detecting the A2 byte, the last A2 byte is detected again so that reramming is performed.

Referring to Figures 4 and 5 attached to the operation of an embodiment of the present invention configured as described above are as follows.

First, as shown in FIG. 5, when the structure of the improved frame of STM-1 / 4 is input to the leaf reamer, the first comparator 10 of the leaf reamer receives the input data (Input data) as a reference frame. After detecting the frame alignment signal FAS byte in comparison with the alignment signal (Reference FAS, F628) byte, the first frame pulse FP1 for generating the frame start position of the corresponding signal is generated.

That is, the first comparator 10 indicates the frame start position of the detection information when the last A1 byte and the first A2 byte are consecutively detected among the framing bytes in comparison to the reference FAS byte in each frame of the STM-1 / 4 signal. To output the first frame pulse FP1 to the position adjusting unit 20.

At this time, the position adjusting unit 20 shifts the position of the first frame pulse FP1 of the start position display as shown in FIG. 5 according to the input first frame pulse FP1 to adjust to the last A2 byte of the framing byte. The second frame pulse FP2 at the adjusted position is generated and then output to the second comparator 30.

Then, the second comparator 30 searches for input data through the frame pulse FP2 generated from the position adjusting unit 20, compares the retrieved frame byte with the frame byte that is originally located, and then compares the result. When there is no error of the frame byte, the final third frame pulse FP3 is output to the frame realignment unit 40.

The frame reordering unit 40 rearranges the leaf rayer data based on the received input data based on the third frame pulse FP3 generated from the second comparator 30.

That is, the second comparator 30 compares the "28" signal, which is the last A2 byte, from the framing byte at the position of the frame pulse FP2 of the position adjusting unit 20, detects the last A2 byte from the input data, and then performs a third frame. By generating the pulses, it is possible to realign the data by finding the starting position of the received data based on the third frame pulse. Thus, the last A1 byte and the first to find the starting position of each frame among the whole framing bytes. By comparing the first A2 byte and the last A2 byte together, the data is rearranged based on the last frame pulse, so that the leaframer can perform more reliable and accurate signal processing.

As described above, the present invention detects the last A1 byte and the first A2 byte in each frame of the STM-1 / 4 signal, and then detects the last A2 byte again so that reframing is performed. In a signal transmission environment, simpler logic circuits provide more reliable and accurate signal processing, providing the effect that the ASIC can be used for both the STM-1 / 4 and other signals in the SDH family.

The present invention is not limited to the above-described specific preferred embodiments, and various modifications can be made by any person having ordinary skill in the art without departing from the gist of the present invention claimed in the claims. Of course, such changes will fall within the scope of the claims.

Claims (2)

In a leaf reamer of a synchronous transmission mode receiver for transmitting and receiving a signal with a transmitter, A first frame pulse for generating a first frame pulse to indicate a frame start position of a corresponding signal when the last A1 byte and the first A2 byte are detected among the whole framing bytes after comparison with the reference frame alignment byte in the received and input random data; 1 comparator; A position adjusting unit which generates a second frame pulse after shifting the data position of the first frame pulse generated from the first comparator to the last A2 byte position of the framing byte; A second comparator for searching the input data at the second frame pulse position generated by the position adjusting unit, comparing the input data with a reference A2 byte signal, and generating a third frame pulse when the last A2 byte signal of the framing byte is detected; And a frame realignment unit which finds a starting position of the received and input data based on the third frame pulse generated from the second comparator, and rearranges the input data. Logic circuit. The method of claim 1, wherein the second comparator detects the last A2 byte from the data input at the second frame pulse position shifted by the position adjusting unit, and compares the last A2 byte with the reference A2 byte to determine whether there is an error. And generating a third frame pulse and transmitting the third frame pulse to the frame reordering unit if there is no error .