JP5230367B2 - Parallel optical transmission apparatus and method - Google Patents

Description

  The present invention relates to a parallel optical transmission apparatus and method, and more particularly to a parallel optical transmission apparatus and method for adjusting skew between lanes that transmit optical signals in parallel.

  The progress of optical communication technology in recent years is remarkable, and products using 40 Gbit / s transmission / reception technology are currently commercialized in the field of serial transmission. However, the current communication demand surpasses the progress of technology, and there is a growing demand for transmitting 40 Gbit / s bulk data using a technology or product that is cheaper than the currently developed 40 Gbit / s serial optical transceiver module. Yes. Furthermore, the demand for communication capacity is not limited to 40 Gbit / s, and in one example, standardization of 100 GE Ethernet (registered trademark) has already been started by the Institute of Electrical and Electronics Engineers (IEEE).

  Parallel transmission technology is a technology that can configure a system at a lower cost than serial transmission technology. Although history has proven that serial transmission is cost-effective as technology matures in the future, at this stage, the cost of 40G serial transmission optical modules has been sufficiently reduced to meet the rapid increase in traffic demand. Not. The parallel optical transmission technology is realized by, for example, paralleling 40 Gbit / s bulk data to four lanes with 10 Gbit / s transmission technology, so 10 Gbitnet (registered trademark) standardization has dramatically reduced 10 Gbit. / S technology and its products can be used. However, when transmitting bulk data in parallel, how to guarantee bit sequence integrity (BSI), in other words, how to adjust the delay difference (skew) between parallel lanes The question of whether to do it arises.

  At present, there is a growing desire in the world for clients with various protocols to connect to a network and transmit data over long distances. Of various protocols, attention should be paid to Ethernet (registered trademark), SONET (Synchronous Optical Network) / SDH (Synchronous Digital Hierarchy), and OTN (Optical Transport Network). These three are the most popular protocols in the world.

  FIG. 1 shows a conceptual diagram of a deskew method by multi-lane distribution (MLD). MLD is a deskew technique discussed in IEEE and is known from Non-Patent Document 1 (http://www.ieee802.org/3/ba/public/jan08/gustlin — 01 — 0108.pdf). This technology belongs to a sublayer above the physical layer and directly below the MAC layer. First, in the TX MLD on the transmission side, a single bulk data is divided into 64-bit blocks, and 64 / 66B encoding is performed on each block. The encoded 66-bit blocks 1-8 are distributed between lanes and transmitted. Here, a specially encoded 66-bit skew adjustment block A is inserted in the gap between the blocks of each lane and transmitted. The receiving side RX MLD adjusts the delay amount of the receiving side buffer memory based on the phase (delay) of the skew adjusting block A to compensate for the skew between the lanes. As can be seen from the fact that the MLD technology belongs to a sub-layer immediately below the MAC layer, it is a technology specialized for Ethernet (registered trademark), and cannot support various clients having systems conforming to various protocols.

  FIG. 2 shows a deskew method according to SFI-5 (Serdes Framer Interface Level 5). SFI-5 is a deskew method independent of service or client type. This technology has been standardized by the standardization organization OIF (Optical Internetworking Forum) and is described in Non-Patent Document 2 (http://www.oiforum.com/public/documents/OFI-SFI5-01.0.0.pdf). Are known. In SFI-5, it is defined as a 16 parallel electrical interface between a framer IC and a SerDes (Serializer-Deserializer) IC that performs parallel-serial. The SFI-5 deskew algorithm can also be applied to optical parallel transmission. The deskew method is as follows. In addition to 16 lanes for transmitting parallel signals, another lane is provided as a deskew lane. On the transmission side shown in the upper half of FIG. 2, the signals of 16 parallel lanes are copied in order for each block, and the copied signals are written in the deskew lane in order. The first lane 1 signal is copied, the lane 2 signal is copied next, the 16th lane signal is copied in this order, and then the lane 1 copy is resumed. On the receiving side shown in the lower half of FIG. 2, the deskew lane signal and the lane 1 signal are compared, and the buffer memory for the lane 1 signal is adjusted until the bit strings are complete. Similarly, the skew from lane 2 to lane 16 is adjusted. When SFI-5 is used, deskewing is possible regardless of the main signal protocol, but it is necessary to add one lane. In particular, in the case of parallel optical transmission, it is necessary to add a set of optical transmission / reception circuits, which generally increases the circuit scale.

  Although not shown, OIF defines a short-range SONET / SDH interface called VSR5 (Very Short Reach Interface Level 5). VSR5 is known from Non-Patent Document 3 (http://www.oiforum.com/public/documents/OFI-VSR5-01.0.pdf). The parallel electrical interface defined by VSR5 is also applicable to a parallel optical transmission system. In this interface, 64 / 66B encoding is performed on an arbitrary parallel bit string on the transmission side. That is, the bit rate increases by 1.03125 times. On the receiving side, deskewing of each lane is performed based on the 64 / 66B header written in each lane. Although this method does not depend on the main signal protocol, an increase in external circuits due to an increase in the bit rate, particularly a PLL (phase locked loop) circuit, becomes complicated. Furthermore, there is an unavoidable concern that jitter will increase due to multiple frequency conversions.

As a technology applied to Ethernet (registered trademark), SONET / SDH, and OTN, which are globally popular protocols among the above three technologies, the increase in cost is suppressed and the jitter does not increase due to the increase in bit rate. MLD is most desirable, but is only applicable to Ethernet.
"100GE and 40GE PCS (MLD) Proposal", IEEE (Institute of Electrical and Electronics Engineers) 802.3ba, Munich, 2008 “Serdes Framer Interface Level 5 (SFI-5): Implementation Agreement for 40 Gb / s Interface for Physical Layer Devices”, OIF (Optical Internetworking Forum), January 29, 2002 “Very Short Reach Interface Level 5 (VSR-5): SONET / SDH OC-768 interface for Very Short Reach (VSR) application”, OIF (Optical Internetworking Forum), September 2002 "ITU-T G.707 / Y.1322 Network node interface for the synchronous digital hierarchy (SDH)", ITU-T, January 2007 "ITU-T G.709 / Y.1331 Interfaces for the Optical Transport Network (OTN)", ITU-T, March 2003

  Accordingly, an object of the present invention is to provide an inexpensive deskew method and apparatus applicable to all of Ethernet (registered trademark), SONET / SDH, and OTN.

  A predetermined bit string having a specific length is inserted as frame synchronization information in a frame such as OTN or SDH. When a frame having this bit string is transmitted in parallel, the receiving side needs to identify a lane (one signal string input to a parallel transmission port), establish frame synchronization, and a deskew function of a plurality of ports.

  A further object of the present invention is that maintenance frames (ODUk-AIS, ODUk-OCI, ODUk-LCK, MS-AIS, MSF-AIS, etc.) in OTN and SDH are included in a bit string other than the frame synchronization information in the frame. It is an object of the present invention to provide a deskew method and apparatus applicable even when a bit string that matches a matching pattern is generated every frame period.

  A further object of the present invention is that g-AIS (generic AIS, OTUk-AIS) defined in OTN is only output from the PN-11 scrambler, has no frame structure, and does not include a frame synchronization signal. Therefore, an object of the present invention is to provide a deskew method and apparatus applicable even when synchronization detection is impossible.

  According to the present invention, a method for performing deskew between lanes on the receiving side of a parallel optical transmission system is provided. The method includes: detecting a loss of frame synchronization based on frame synchronization information of a transmission frame for each lane; determining a delay amount to be added to one or a plurality of lanes in which the loss of frame synchronization is detected; and the delay Reading received signals from the received signal buffers of the one or more lanes according to quantity.

  The present invention further provides an apparatus for performing deskew between lanes on the receiving side of a parallel optical transmission system. The apparatus includes means for detecting out of frame synchronization based on frame synchronization information of a transmission frame for each lane, means for determining a delay amount to be added to one or a plurality of lanes in which out of frame synchronization is detected, and the delay Means for reading a received signal from the received signal buffer of the one or more lanes according to the quantity.

  According to the present invention, there is further provided a method of performing deskew between lanes on the receiving side of a parallel optical transmission system. The method includes detecting a pattern matching based on a specific bit string for each lane, determining a delay amount to be added to one or a plurality of lanes in which the pattern matching is detected, and according to the delay amount, Or reading a received signal from a received signal buffer of a plurality of lanes.

  The present invention further provides an apparatus for performing deskew between lanes on the receiving side of a parallel optical transmission system. The apparatus includes: means for detecting pattern matching based on a specific bit string for each lane; means for determining a delay amount to be added to one or a plurality of lanes in which the pattern matching is detected; and according to the delay amount, Or means for reading received signals from the received signal buffers of a plurality of lanes.

  Since the present invention realizes deskew using only information transmitted by the main signal, it is not necessary to provide an additional device or transmission path for deskew, and a large-capacity parallel transmission system can be constructed at low cost. In addition, the present invention suppresses the continuation of the same code for each lane, which may occur when long frame synchronization information is parallelized, and improves the transmission quality of a large-capacity parallel transmission system.

  The present invention is based on the fact that only the frame synchronization information appears periodically when most of the received frames differ from each other as in the normal state. By determining it as information, deskew is enabled.

  The present invention further provides maintenance frame type determination, maintenance frame type determination, frame synchronization, identification of lanes for parallel transmission, even when pattern matching other than frame synchronization information is repeatedly detected apart by the frame length, and Enable deskew.

[Example 1]
FIG. 3 is a configuration diagram of the parallel optical transmission system 300 according to the first embodiment of the present invention. The parallel optical transmission system 300 of FIG. 3 includes a transmission side framer 311, a transmission side converter 312, a parallel optical transmission module 313 on the transmission side, a reception side framer 331, a reception side converter 332, a parallel optical reception module 333, an FPGA or The CPU 334 has an optical transmission path between the transmission side and the reception side, and a 40 Gbit / s signal is sent to four 10 Gbit / s transmission paths 321, for example, four CWDM (Coarse-WDM (Wavelength Division Multiplexing): low Performs parallel transmission on a density wavelength division multiplexing transmission line.

  The transmission side framer 311 forms a SONET / SDH or OTN frame, and transmits the frame to the transmission side converter 312 via 16 lanes and 1 deskew lane according to the SFI-5 standard. The transmission-side converter 312 adjusts the skew generated by the electrical wiring between itself and the framer 311 by adjusting the reading of the signal from the transmission buffer in accordance with the SFI-5 standard, and further 16: 4 in 1-bit units for the signal. By performing interleaving, the data is allocated to four lanes and transmitted to the parallel optical transmission module 313. Here, the skew adjustment and the interleaving order may be reversed. The parallel optical transmission module 313 converts the received electrical signal into an optical signal and transmits it to the transmission path 321.

  The parallel optical receiving module 333 converts the optical signal from the transmission path 321 into an electric signal and transmits it to the receiving side converter 332. The receiving-side converter 332 expands the signal into 16 lanes by performing 4:16 interleaving in 1-bit units, and signals to the receiving-side framer 331 via 16 lanes and one deskew lane according to the SFI-5 standard. Send. The reception side framer 331 adjusts the skew generated by the electrical wiring between itself and the reception side converter 332 by adjusting the reading of the signal from the reception buffer according to the SFI-5 standard.

  FIG. 4 is a detailed block diagram of the receiving side of the parallel optical transmission system according to the first embodiment of the present invention. The frame synchronization information extraction unit 411 of the reception side framer 331 extracts frame synchronization information such as A1 byte and A2 byte included in the SONET / SDH frame, and transmits the frame synchronization information to the FPGA or the CPU 334. The OOF (Out-Of-Frame) / LOS (Loss-Of-Signal) detection unit 441 of the FPGA or CPU 334 determines whether or not the main signal is correctly received based on the frame synchronization information. . For example, when the BSI is corrupted due to skew, the frame synchronization information corresponding to each lane from the receiving framer 331 is skewed, so it is determined that OOF has occurred. In response to the occurrence of OOF, the delay amount determination unit 442 determines a delay amount to be added for each lane. The FPGA or CPU 334 transmits the delay amount to be added determined by the delay amount determination unit 442 to the converter 332 as a deskew instruction for each lane. The reception-side converter 332 adjusts the skew between the lanes by adding the delay amount notified from the FPGA or the CPU 334 to the signal read from the buffer 421 for each lane.

  When the OOF / LOS detection unit 441 detects LOS (signal loss), the FPGA or the CPU 334 may stop transmitting the deskew instruction in order to save power. Also, the skew instruction is not transmitted while the LOS is detected so that the signal can be received immediately after the restoration of the signal loss.

  3 and 4, the FPGA or the CPU 334 is shown as a separate component from the framer 331 and the converter 332, but may alternatively be incorporated in the converter 332.

  Such determination of the delay amount may be performed for all possible combinations of one or a plurality of lanes among one or a plurality of lanes.

[Example 2]
A method of determining the delay amount by the delay amount determination unit 442 of the FPGA or the CPU 334 according to the second embodiment of the present invention will be described below. The delay amount determination unit 442 calculates a skew from the input transmission path condition, and generates a deskew instruction centered on the calculated skew. For example, the delay difference of the optical portion can be calculated from the set of wavelengths used for the four lanes, the dispersion of the optical fiber, the distance, and the like. FIG. 5 shows a calculation example of skew between lanes according to the second embodiment of the present invention. For example, the set of wavelengths to be used is 1270 nm, 1290 nm, 1310 nm, and 1330 nm. G. In the case of SMF of 652 standard fiber, the zero dispersion wavelength is around 1300 nm (here, assumed to be 1300 nm), and the dispersion slope is about 0.093 ps / nm ² / km. From the above, the optical delay is calculated as 428.4 ps for lane 1, 46.8 ps for lane 2, 46.1 ps for lane 3, and 409.1 ps for lane 4. Since the baud rate is 10.3125 Gbit / s, the skews are 4.41 UI, 0.48 UI, 0.46 UI, and 4.22 UI, respectively.

  In addition to the optical delay described above, it is also possible to measure in advance the delay difference due to the electrical wiring of the transmission and reception side devices. Furthermore, it is also possible to estimate the skew from the estimation of the temperature gradient during operation of the transmission and reception side devices.

  In the second embodiment of the present invention, by starting the deskew using the skew value calculated as described above as an initial value, the time required to determine an appropriate delay amount can be shortened.

[Example 3]
FIG. 6 is a configuration diagram of a parallel optical transmission system having a pattern matching circuit 601 according to the third embodiment of the present invention. As a difference from FIG. 3, a signal line for transmitting a pattern matching pulse signal for each lane from the converter 332 to the FPGA or the CPU 334 is provided. The pattern matching method will be described below using FIG. In the pattern transmitted from the framer 331, in STM1, every A1 byte (F6 in hexadecimal notation, 11110110 in binary notation) called frame synchronization information is 125 bytes every 3 μs, followed by A2 byte (28 in hexadecimal notation, 28, 00101000 in binary notation) always appears 3 bytes (6 bytes = 48 bits in total). Although the case of STM1 will be described below, the present embodiment is also applicable to STM4, 16, 64, 256, OTU3, etc. in which A1 and A2 bytes appear periodically continuously.

  As an alternative, pattern matching may be performed using any periodic specific bit string for each lane instead of the frame synchronization information. An example of such a periodic specific bit string is a specific bit string included in a maintenance frame or the like.

  As an alternative, pattern matching may be performed using any specific bit string for each lane instead of the frame synchronization information. For example, the present embodiment can be applied to a variable-length frame such as Ethernet (registered trademark).

  Instead of the pattern matching pulse of FIG. 6, an arbitrary pattern matching signal that is generated when pattern matching is detected with respect to the input signal and indicates that the pattern is matched may be used.

Interleaving will be described below with reference to FIG. FIG. 7 illustrates how frame synchronization information is interleaved in units of four lanes according to the third embodiment. The electrical interface between the framer 311 and the converter 312 is provided with 16 parallel + deskew channels in addition to the SFI-5 interface. For example, when these signals are transmitted in parallel in four lanes, the converter 312 converts 16 parallel signals into four parallel signals. Here, it is assumed that 16: 4 interleaving is performed in bit units (hereinafter expressed as n = 1 where n is the number of bits to be interleaved). The 48-bit signal is interleaved in the four parallel lanes I-IV as follows.
Lane I: 101010010101
Lane II: 111111,000,000
Lane III: 111111101010
Lane IV: 101010000000
Therefore, a different 12-bit pattern is obtained for each lane, and the lane can be identified on the receiving side. The converter 332 transmits a pattern matching pulse to the FPGA or the CPU 334 when the pattern matching circuit 601 provided for each lane detects the pattern every 125 μs (or every 3 μs in OTU3). Alternatively, the converter 332 may immediately transmit a pattern matching pulse upon detecting pattern matching, and notify the FPGA or CPU 334 of detection of pattern matching every 125 μs (every 3 μs). The FPGA or CPU 334 determines a delay amount to be added to each lane based on the arrival time of the pattern matching pulse, and transmits the delay amount to the converter 332. The converter 332 realizes deskew by controlling the read time from the reception buffer 421 according to the delay amount. As described above, the deskew process is further speeded up by providing the pattern matching circuit 601. Since the pattern matching circuit 601 is provided for each lane, a pattern matching pulse signal is generated for each lane, and frame synchronization is realized for each lane.

  Note that the distance from the pattern patching circuit 601 of each lane of the converter 332 to the FPGA or the CPU 334 is slightly different between lanes, or may be changed by a temperature gradient or the like. In order to adjust the skew due to these differences, the deskew may be performed by combining the first and second embodiments of the present invention. Specifically, the FPGA or the CPU 334 determines an initial value of the delay amount to be added for each lane around the skew calculated from the transmission path condition and / or the device condition, and performs an approximate deskew based on the pattern matching pulse. While performing, finally, the skew state is searched by the trial and error method so that the OOF is not detected in the vicinity of the calculated skew.

  In FIG. 6, the FPGA or CPU 334 is shown as a separate component from the framer 331 and the converter 332, but may alternatively be incorporated in the converter 332.

  In the third embodiment of the present invention shown in FIG. 6, since interleaving is performed in bit units (ie, n = 1), the interleaving units of the converters 312 and 332 on the transmitting side and the receiving side (the receiving side is shown in FIG. 4). 423) (shown as 423) can be shared with the SFI-5.2 interface that serializes the conventional SFI-5 to serial 4 parallel. This is because the SFI-5.2 interface is configured with 4 parallel + 1 deskew channels, and therefore, when converting from the conventional SFI-5 interface of 16 parallel + 1 deskew channels, 16: 4 interleaving in bit units is used. Because.

[Example 4]
In the fourth embodiment of the present invention, the pattern matching timing is transmitted by the pattern matching pulse width. The fourth embodiment of the present invention is a particularly effective means when there are restrictions on the pulse output conditions in the third embodiment, particularly when there is a restriction on high speed. Specifically, in general, in a CMOS circuit or the like, the output terminal for the pattern matching pulse described in the third embodiment is often assigned to a control terminal, and the control terminal has a restriction on the operation speed. There are many. In general, the rise time of the pulse at the control terminal of the CMOS circuit is often suppressed to about several hundred nanoseconds, and the timing information described in the third embodiment may be buried in the error of the rise time of the pulse. . The fourth embodiment of the present invention solves this problem by transmitting pattern matching timing information to an external FPGA or CPU 334 according to the width of the pattern matching pulse.

FIG. 8 is an explanatory diagram of a fourth embodiment in which the pattern matching timing is transmitted by the pattern matching pulse width. In FIG. 8, the matching pattern is assumed as follows.
Lane I: 110011110011
Lane II: 100110100110
Lane III: 10010001100
Lane IV: 110011100110
Since pattern matching processing is difficult to perform at high speed, it is usually performed after parallel development. In the following description, as shown in FIG. 8, 16 parallel development will be described. However, more or less than 16 parallel lanes may be used. In the following, only lane I and lane II will be described with reference to FIG.

  The received signals of Lane I and Lane II are 16-bit parallel expanded. Here, the bit parallel (DMX) circuit needs to be synchronized in all lanes. Depending on the delay difference of each lane, which bit of the parallel development starts with the desired pattern differs. For example, in the lane I shown in FIG. 8, since the pattern starts from the third bit, there is a relative delay of 3 bits. In Lane II, since the pattern starts from the 6th bit, it can be seen that there is a 6-bit relative delay. Each pattern matching circuit can set the pulse width of the pattern matching pulse to a multiple of the minimum pulse width based on the information of the start bit. That is, in Lane I, the width is three times the minimum pulse, and in Lane II, the width is six times the minimum pulse.

  The FPGA or CPU 334 can recognize the relative delay of each lane based on the reached pulse width, and can transmit an appropriate command, that is, a deskew instruction that indicates an appropriate delay amount.

  This embodiment is applied to skew adjustment of less than 16 UI when the number of parallel lanes is 16 parallel, for example, and the maximum pulse width is shorter than the minimum frame period (3 μs for OTU, 125 μs for STM). To do.

[Example 5]
In the third embodiment described above, interleaving in bit units (ie, n = 1) has been described as shown in FIG. 7. However, with the configuration shown in FIG. 11, for example, four lanes in 3 bit units (ie, n = 3). It may be divided into In this case, the 48-bit signal in each of the 4 parallel lanes is as follows.
Lane I: 1111101001100
Lane II: 101011010000
Lane III: 101110000101
Lane IV: 1111110010000
Therefore, since the 12-bit pattern differs for each lane, the lane can be identified. The advantage of this embodiment is remarkable when the main signal is STM256. In STM256, every 125 μs, A1 byte is 64 bytes, and then A2 byte is 64 bytes. Therefore, in the third embodiment in which interleaving is performed in bit units (that is, n = 1), in the case of STM256, as shown in FIG. 9, there are lanes in which 1 and 0 continue for 128 bits.

  On the other hand, if interleaving is performed in units of 3 bits (that is, n = 3) as shown in FIG. 11, the continuation of the same code can be suppressed to 5 bits at the maximum. As a result, it is possible to easily extract a clock component from the serial signal, simplify the circuit configuration, or increase the bit identification margin.

  In the fifth embodiment of the present invention shown in FIG. 11, the interleaving in units of 3 bits (that is, n = 3) is exemplified. Can be made. However, in interleaving in units of bits including only 2 in the factor such as 2-bit units (n = 2) and 4-bit units (n = 4), a different pattern cannot be created for every four lanes. Therefore, in the case of 4 lanes, interleaving in units of 3 bits is the simplest, and the STM256 is the optimum configuration that does not cause extreme continuation of the same code.

[Example 6]
FIG. 12 shows Embodiment 6 of the present invention for improving the transmission quality when the frame synchronization information portion is transmitted in parallel. FIG. 12 includes inverters 1201 and 1202 that alternately invert OTU and STM main signals every 8 bits in addition to the configuration of the third embodiment. As a pattern transmitted from the framer 311, in STM1, every A1 byte (F6 in hexadecimal notation and 11110110 in binary notation) called frame synchronization information is 125 bytes every 3 μs, followed by A2 bytes (28, 2 in hexadecimal notation). 3 bytes (a total of 6 bytes = 48 bits) always appear in decimal notation. Although the case of STM1 will be described below, the present embodiment is also applicable to STM4, 16, 64, 256, OTU3, etc. in which A1 and A2 bytes appear periodically continuously.

FIG. 13 illustrates a state in which a part of the frame synchronization information is inverted and interleaved in units of four lanes. The electrical interface between the framer 311 and the converter 312 is provided with 16 parallel + deskew channels in accordance with the SFI-5 interface. For example, when these signals are transmitted in parallel in four parallel lanes, the converter 312 converts 16 parallel signals into 4 parallel signals. Here, 16: 4 interleaving in bit units (ie, n = 1) is assumed. Then, the inverter 312 is provided with alternating inversion means, for example, an inverter 1201, for inverting the input of the first eight signals out of the 16 parallel signals at the input stage of the converter 312 or at the input section of the converter 312. , The number of bits to be inverted is expressed as m = 8). At this time, 48-bit signals appearing in each of the four parallel lanes are as follows. A bit enclosed in parentheses indicates that it has been inverted by the inverter 1201.
Lane I: (01) 10 (01) 01 (10) 01
Lane II: (00) 11 (00) 00 (11) 00
Lane III: (00) 11 (00) 10 (01) 10
Lane IV: (01) 10 (01) 00 (11) 00
Therefore, a different 12-bit pattern is obtained for each lane, and the lane can be identified on the receiving side. The reception-side converter 332 includes the above-described pattern matching circuit 601 for each lane, and transmits a pattern matching pulse to the FPGA or the CPU 334 when the pattern is detected every 125 μs (every 3 μs in OTU3). Alternatively, the converter 332 may immediately transmit a pattern matching pulse upon detecting pattern matching, and notify the FPGA or CPU 334 of detection of pattern matching every 125 μs (every 3 μs). The FPGA or CPU 334 determines a delay amount to be added to each lane based on the arrival time of the pattern matching pulse, and transmits the delay amount to the converter 332. The converter 332 realizes deskew by controlling the read time from the reception buffer 421 according to the delay amount. As described above, since the pattern matching circuit 601 is provided in each lane, a pattern matching pulse signal is generated for each lane, and frame synchronization is realized for each lane. Then, when returning each lane to 16 parallel + deskew channels after deskewing, the main signal may be restored by being inverted by the inverter 1202 every 8 bits (that is, every 2 bits in each lane).

  The advantage of the sixth embodiment is remarkable when the main signal is STM256. In STM256, every 125 μs, A1 byte is 64 bytes, and then A2 byte is 64 bytes. Therefore, in the third embodiment having no previous alternating inversion means, there are lanes in which 1 and 0 continue for 128 bits as shown in FIG. On the other hand, if the alternating inversion means 1201 in units of 8 bits (that is, m = 8) is provided as shown in FIG. 12, the continuation of the same code can be suppressed to a maximum length of 4 bits as shown in FIG. As a result, it is possible to easily extract a clock component from the serial signal, simplify the circuit configuration, or improve the bit identification quality.

  In the sixth embodiment, an example in which alternating inversion is performed in units of 8 bits (that is, m = 8) when interleaving is performed in units of bits (that is, n = 1) and transmission is performed in 4 lanes has been described. 12) or 16-bit units (m = 16). In either case, a different 12-bit pattern is generated for each lane, so that the same code continuity can be suppressed. However, the same code continuation is 6 bits long in 12-bit units and 8 bits long in 16-bit units. On the other hand, since a different 12-bit pattern is not generated for each lane in 4-bit units (that is, m = 4), the lanes cannot be identified. For this reason, when interleaving in bit units (n = 1) and transmitting in 4 lanes, alternating inversion in 8-bit units (m = 8) is optimal.

[Example 7]
FIG. 14 shows the configuration of a seventh embodiment of the present invention that improves the lane identification capability when the inverter application timing is shifted in the sixth embodiment and the frame synchronization information portion is transmitted in parallel. As a pattern transmitted from the framer 311, in STM256, A1 byte (F6 in hexadecimal notation and 11110110 in binary notation) called frame synchronization information every 125 μs is 64 bytes, followed by A2 bytes (28, 2 in hexadecimal notation). 64 bytes (a total of 128 bytes = 1024 bits) always appear in hexadecimal notation. The electrical interface between the framer 311 and the converter 321 is provided with 16 parallel + deskew channels in addition to the SFI-5 interface. For example, when these signals are transmitted in parallel in four parallel lanes, the converter 312 converts 16 parallel signals into 4 parallel signals. Here, 16: 4 interleaving in bit units (ie, n = 1) is assumed. The converter 312 is provided with an alternating inversion means, for example, an inverter 1401, for inverting the central 8 signals among the 16 parallel signals, at the front stage of the converter 312 or at the input portion of the converter 312. ) Alternately. That is, alternating inversion is performed at the point of the 4th bit and the 5th bit which are intermediate between the 1-byte (8-bit) frame synchronization information A1 and A2. At this time, the 48-bit signals in the four parallel lanes are as follows. A bit enclosed in parentheses indicates that it has been inverted by the inverter 1401.
Lane I: 1 (10) 01 (11) 10 (01) 1
Lane II: 1 (00) 11 (01) 00 (11) 0
Lane III: 1 (00) 11 (00) 01 (10) 0
Lane IV: 1 (10) 01 (11) 00 (11) 0
Accordingly, a different 12-bit pattern is obtained for each lane, and the lane identification on the receiving side is possible. The receiving unit of the converter 332 includes the pattern matching circuit 601 for each lane, and transmits a pattern matching pulse to the FPGA or the CPU 334 when the pattern is detected every 125 μs (or every 3 μs in OTU3). Alternatively, the converter 332 may immediately transmit a pattern matching pulse upon detecting pattern matching, and notify the FPGA or CPU 334 of detection of pattern matching every 125 μs (every 3 μs). The FPGA or CPU 334 determines a delay amount to be added to each lane based on the arrival time of the pattern matching pulse, and transmits the delay amount to the converter 332. The converter 332 realizes deskew by controlling the read time from the reception buffer 421 according to the delay amount. As described above, since the pattern matching circuit 601 is provided in each lane, a pattern matching pulse signal is generated for each lane, and frame synchronization is realized for each lane. Then, when returning each lane to 16 parallel + deskew channels after deskewing, the main signal may be restored and inverted by the inverter 1402 every 8 bits (that is, every 2 bits in each lane).

  The advantage of the seventh embodiment is remarkable when the main signal is STM256. In Example 5, since the alternating inversion is simply performed in units of bytes, as shown in FIG. 13, if the lane III is shifted by 1 bit, it matches the 12-bit pattern of the lane IV. In lane identification is not possible. On the other hand, in the seventh embodiment, as shown in FIG. 14, if the phase for performing the alternating inversion in units of 8 bits (that is, m = 8) is shifted by 4 bits and the alternating inversion is performed in the middle of the frame synchronization information, In Lane IV, the same 12-bit pattern is not generated even if the bit position is shifted. This provides an advantage that lanes can be identified only by a bit pattern.

Further, the seventh embodiment has an advantage that the pattern matching can be simplified. Specifically, lane identification and skew adjustment can be performed by using only the 4-bit pattern of each lane surrounded by [] shown below, near the center where the frame synchronization information A1 and A2 are switched. This is because the corresponding 4-bit pattern always appears every 125 μs (every 3 μs in the case of OTN3) in each lane only at the timing when the frame synchronization information is switched. (The bit enclosed in parentheses indicates that it has been inverted by the inverter 1201.)
Lane I: 1 (10) 0 [1 (11) 1] 0 (01) 1
Lane II: 1 (00) 1 [1 (01) 0] 0 (11) 0
Lane III: 1 (00) 1 [1 (00) 0] 1 (10) 0
Lane IV: 1 (10) 0 [1 (11) 0] 0 (11) 0
[Example 8]
FIG. 16 shows the configuration of the eighth embodiment of the present invention in which serialization is performed by interleaving in units of 1 bit in the middle of the parallel transmission means. Differences from FIG. 12 are as follows. The converter 312 parallelizes the signal into four lanes and passes the signal to the serial optical transmission module 1613. Next, the serial conversion light transmission module 1613 interleaves in units of 1 bit, that is, serializes and transmits to the serial conversion light transmission line 1621 with one type of wavelength. The parallel-converted light receiving module deinterleaves the signal received from the serial-converted light transmission path 1621 in units of 1 bit and returns the signal to 4 lanes. Unlike the case of FIG. 12, when the parallel conversion light reception module 1633 returns the signal to 4 lanes, the positions of the 4 lanes on the transmission side and the 4 lanes on the reception side may be shifted depending on the timing of bit distribution. . However, since a different 12-bit pattern is generated for each lane according to the present invention, the lane can be identified on the receiving side. Specifically, for example, each pattern matching circuit 601 checks whether all four patterns match, and pattern matching is detected when the pattern is detected every 125 μs (or every 3 μs in OTU3). The pulse and the detection pattern number are transmitted to the FPGA or the CPU 334. It is possible to output to the reception side framer 331 in the same correct order as the transmission side by recognizing the lane from this pattern number and controlling which reception buffer is read out.

[Example 9]
In general, in parallel transmission, a physical port and a lane may not correspond on the receiving side. In such a case, in order to know the correspondence between the physical port and the lane, a bit string (matching pattern) to be matched may be arbitrarily set for each lane. When a frame is received, if no matching occurs in a certain matching pattern or the amount of skew cannot be calculated, a different matching pattern is set and pattern matching is performed again.

  Furthermore, the setting of the matching pattern may continue to be changed sequentially at a specific time interval or every specific number of bits. Thereby, pattern matching can be performed even when the correspondence between the port and the lane is unknown at the time of signal reception.

  Embodiment 9 will be described with reference to FIG. In the example shown in FIG. 17, the matching pattern applied to the ports 1 to 4 is changed at regular intervals. In particular, when the transmission frame is a fixed-length frame such as OTN or SDH, the matching pattern may be set at a predetermined time interval or a predetermined number of bits corresponding to one frame of the fixed-length frame.

[Example 10]
FIG. 18 shows a configuration example of the tenth embodiment. Upon receiving the pattern matching signal, the counter 1820 resets the counter value to 0 and starts counting. When the counter value reaches a predetermined time or number of bits, or when the next pattern matching signal is received, the counter value is reset again. The register 1810 is set to High when the pattern matching signal is received, and is set to Low when the counter value reaches a predetermined time or the number of bits. The register 1810 is in a high state only for a predetermined time or number of bits from the occurrence of pattern matching. By taking the logical product 1830 of the registers 1810 of all the lanes, an all lane pattern match flag which is a signal for detecting the occurrence of the pattern matching signal in all the lanes within a predetermined time or less than the number of bits is obtained.

  On the other hand, the amount of skew is calculated from the difference in clock or bit number between the counter value at the time when pattern matching occurs in each lane and the all lane pattern match flag that detects the occurrence of pattern matching signals in all lanes. calculate. When OTN and SDH maintenance frames and frame synchronization information are transmitted in parallel, if matching is performed on a bit string received by each lane, matching other than the frame synchronization information occurs at a sufficiently distant position in each lane. FIG. 19 shows, as an example, the position of a bit string where pattern matching occurs when ODUk-OCI is transmitted with the configuration shown in FIG. The numbers in the figure are the positions of the first bits of the bit string where matching occurs, counted from the first bit of FAS (Frame Alignment Signal) which is frame synchronization information. Here, except for the pattern matching of four lanes including matching generated from a bit string that is not at least one frame synchronization information, the pattern matching of the four closest lanes is a portion surrounded by a dotted line in FIG. Lane 2 2050, lane 3 1899, and lane 4 2075, which are 460 bits apart.

  Therefore, if the predetermined time or the number of bits is appropriately set (for example, 200 bits in the above example), the frame synchronization information is received when pattern matching occurs in all the lanes within the set range. Can be considered.

[Example 11]
The eleventh embodiment will be described using an OTN maintenance frame as an example. Since most of the OTN maintenance frames are fixed values (predetermined values that can be known in advance), when matching is performed with an arbitrary matching pattern, the generation interval (generation position) of the pattern matching signal is various maintenance frames. Or it is fixed for each lane. FIG. 20 illustrates the position of a bit string where pattern matching occurs when ODUk-OCI is transmitted in parallel with the configuration shown in FIG. 15 and matching is performed using a matching pattern that can detect frame synchronization information. The number in the figure represents the position of the first bit of the bit string that matches the pattern when the top of the frame is 1.

  Here, the receiving side stores the predetermined pattern matching signal generation interval as described above, and the frame type and lane number corresponding to the predetermined pattern matching signal generation interval. The receiving side performs pattern matching on the signal that is actually received, and compares the actual pattern matching signal generation interval detected from the received signal with the stored predetermined pattern matching signal generation interval. If the pattern matching signal generation intervals match, the receiving side can identify the type and lane number of the received frame.

  Further, the receiving side stores the position of the frame synchronization information together with the pattern matching signal generation interval. When the receiving side detects the pattern matching signal from the received signal at the same interval as the pattern matching signal generation interval stored in advance, the receiving side can identify the pattern matching signal generated by the frame synchronization information based on the position information of the frame synchronization information. Then, the receiving side calculates the skew amount from the difference in detection time of the pattern matching signal generated by the frame synchronization information of each lane.

  In the above example, the case where matching is performed using a matching pattern capable of detecting frame synchronization information has been described. However, the present invention is not limited to the above example, and the matching pattern can be arbitrarily set.

  FIG. 21 shows an example in which the interval between two adjacent pattern matching signals is used as the pattern matching signal generation interval.

  A pattern matching signal interval between two adjacent pattern matching signals is selected from the pattern matching signal generation intervals as shown in FIG. 20 determined in advance by the configuration of the transceiver and the matching pattern. Further, in order to calculate the corresponding frame type, lane number, and skew amount in association with the interval between the two adjacent pattern matching signals, for example, from the generation of the two adjacent pattern matching signals to the frame synchronization information. A counter value table 2210 as shown in FIG. The distance to the frame synchronization information may be the number of bits or time. “Pseudo FAS” in the figure is not a frame synchronization information (FAS) part, but represents a pattern in which a bit string that matches the frame synchronization information exists and a pattern matching signal is detected.

  In FIG. 21, the counter 2120 that has received the pattern matching signal resets its value and starts counting again. Thereby, the value of the counter when the pattern matching signal is generated indicates the interval between the current pattern matching signal and the adjacent (immediately preceding) pattern matching signal. Further, when the pattern matching signal is generated, the counter value comparison unit 2110 searches the counter value when the pattern matching signal is generated from two adjacent pattern matching signal generation intervals stored in the counter value table 2210. If a coincidence occurrence interval is found in the counter value table 2210, the frame type and lane can be identified.

  If the distance 2230 to the frame synchronization information in the counter value table 2210 is used, the frame synchronization information can be found and the skew amount can be calculated. As an example, a method using the same method as in Example 10 will be described. In the counter value table 2210, the distance 2230 to the frame synchronization information stored in association with the interval 2220 with the adjacent (previous) pattern matching signal is set as the maximum value of the next counter 2130, and the count of the counter 2130 is set. Start. When the counter 2130 reaches the set counter maximum value, that is, when the position of the frame synchronization information is reached, a counter end signal is generated. This is input to the register 1810 and the counter 1820 of the tenth embodiment (FIG. 18), and the skew amount is calculated by the skew amount calculation unit 1840 as in the tenth embodiment.

  Here, for the sake of simplicity, the distance 2230 to the frame synchronization information is used. However, the present invention is not limited to the above example, and between the lanes at the position of the subsequent pattern matching signal among the two adjacent pattern matching signals. Differences can also be used.

  Further, as shown in FIG. 23, the counter value of the counter 2120 at the time of generation of the most recent pattern matching signals is stored in the memory 2310, so that a pattern matching signal that is not adjacent to each other or a plurality of patterns is used. The interval of the matching signal can also be used. FIG. 24 shows the operation of the memory 2310 when pattern matching signals that are not adjacent to each other are used. The double line arrows in the figure are arbitrarily selected pattern matching signals, and the counter value table 2210 stores in advance the intervals between the arbitrarily selected pattern matching signals and other pattern matching signals. deep. The storage areas required for the counter value table 2210 and the memory 2310 differ in size depending on how many times the pattern matching signals are generated between arbitrarily selected pattern matching signals. In the example of FIG. 23, since the pattern matching signal is generated three times between arbitrarily selected pattern matching signals, the memory 2310 needs an area where the counter value can be written four times. When the pattern matching signal is detected, the value in the counter value table 2210 is compared with the value in the memory 2310. When all the values in the counter value table 2210 do not match, the first written data is discarded according to the FIFO (First-In First-Out) rule, and the interval until the newly detected pattern matching signal is newly stored in the memory 2310. Add to This is performed until the value in the counter value table 2210 matches the value in the memory 2310.

    Further, FIG. 25 shows an operation example of the memory 2310 for saving the area of the counter value table 2210. In the counter value table 2210, only an interval between arbitrarily selected pattern matching signals is held in advance. In the memory 2310, the number of bits until the next pattern matching signal is generated is counted, added to the previously held value, and the memory 2310 area is newly increased by one. If the value is larger than the value held in the counter value table 2210 at this time, the value is deleted to save the memory 2220 area. The above series of operations is repeated until the value matches the value in the counter table.

  In addition, when three adjacent pattern matching signals are used, the configuration example of FIG. 24 in which the generation intervals of each pattern matching signal are stored can be applied as it is. In the configuration of FIG. 24, all of the pattern matching signals included between them in addition to the arbitrarily selected pattern matching signal are held in the counter value table 2210 and the memory 2310, so that the storage area becomes excessive in some cases. Therefore, it is possible to save the memory 2310 area and use the configuration of FIG. 26 in which only the interval between arbitrarily selected pattern matching signals is considered. The counter value table 2210 holds the number of bits representing the interval between pattern matching signals. When three pattern matching signals are used, two pieces of interval information are held. As in the operation method of the counter and the memory 2310, the number of bits until each pattern matching signal is generated is counted, added to the previously held value, and a memory 2310 area is newly added. If it is larger than the value in the counter value table 2210 at this time, it is deleted to save the memory 2310 area. When the value in the counter value table 2210 matches, the information stored in the memory 2310 is reset once to match the value stored in the next counter value table 2210, and the above operation is performed for all the counter value tables. Repeat until it matches the value of 2210.

  Regarding the determination of the frame type of the OTN maintenance frame, when transmitted in 4 lanes as in the configuration shown in FIG. Things exist. “◯” in Table 1 is the only one different from the other maintenance frames, and “X” indicates the same as the other maintenance frames. Since each maintenance frame has a unique generation pattern in any lane, the frame type can be identified.

さらにいずれの発生間隔にも合致しない場合は上記以外（通常のＯＴＵフレーム若しくはｇ−ＡＩＳ）のマッチングにより生じたパターンマッチング信号であると判定できる。また、送信側のインバータの配置を変更した場合でも、上記の関係が成り立つため、パターンマッチング信号発生間隔を監視することで信号種別の判定が可能である。

Further, if it does not match any generation interval, it can be determined that the pattern matching signal is generated by matching other than the above (normal OTU frame or g-AIS). Even when the arrangement of the inverters on the transmission side is changed, the above relationship is established, so that the signal type can be determined by monitoring the pattern matching signal generation interval.

[Example 12]
Example 12 will be described. As described in the eleventh embodiment, two adjacent matching signal generation intervals are stored in the counter value table 2210 in advance and compared with the counter value of the counter 2120 or the counter value stored in the memory 2310 when the pattern matching signal is generated. However, the same pattern matching signal generation interval as the pattern matching signal generation interval used here should not exist in another position or other lane of the same frame. For this reason, the one that is the only interval with respect to a predetermined time or number of bits (for example, the number of bits of one frame or transmission time) is selected.

  In particular, in the OTN frame, there are non-fixed parts in the MFAS (Multi-Frame Alignment Signal), OTUk-OH (Optical Transport Unit Overhead) and FEC (Forward Error Correction) areas. However, a combination of pattern matching signals that does not have a plurality of intervals between the selected pattern matching signals is selected.

  A method for deriving a combination of pattern matching signals will be described specifically using an OTN maintenance frame as an example. In the OTN maintenance frame, most of the frame including the payload has a fixed value (a specific pattern is repeated with a scrambler or the like). A bit string having a fixed value is obtained based on a bra or the like. The generation interval of the pattern matching signal is obtained from the matching pattern used next. FIG. 20 shows an example in which this is performed using the configuration of FIG. An arbitrary plurality of pattern matching signals are selected from the obtained pattern matching signal generation intervals. Furthermore, even if the pattern matching signal is generated at any position in the region where the combination of the pattern matching signals having the same interval as the selected combination of the pattern matching signals is not a fixed value as described above, Can be selected as a combination that can be used for skew amount calculation or the like. Whether or not there is a combination of pattern matching signals with the same interval, the pattern matching signal that appears as described above is already known in the fixed value area. This makes it possible to make a determination.

For example, in the pattern matching signal generation interval when the FAS pattern (110011110011) of lane 1 is used for lane 1 in the configuration shown in FIG. 15 shown in FIG. 20, the following combinations of the three pattern matching signals are given as an example. Can be used. These do not appear in other positions in the same frame or in other maintenance frames or other lanes.
Matching pattern starting from 10143 Matching pattern starting from 5712 bit interval 15855 Matching pattern starting from 4123 bit interval 19932 [Example 13]
In the maintenance frame of OTN, FAS which is frame synchronization information is a fixed value. MFAS and OTUk-OH are not fixed values. Therefore, as shown in FIG. 27, there are cases where the same bit string as the frame synchronization information is generated in these bit strings, and it is necessary to confirm that the bit string is repeatedly generated by being separated by a frame size over a plurality of frames. In the thirteenth embodiment, the position where the same bit string as the frame synchronization information that can appear in the MFAS and OTUk-OH is generated immediately after the frame synchronization information. In the meantime, even if the frame synchronization information is detected, the matching signal is not output, thereby reducing the number of frames to be acquired necessary for frame synchronization and skew amount calculation.

  Embodiment 13 will be described with reference to FIG. FIG. 13 shows only one lane.

  A pattern matching signal is first input to the register 2820. The register 2820 that has received the pattern matching signal sets its own state to High, and the mask counter 2810 resets the value and starts counting. The register 2820 is set to Low when the counter value reaches a predetermined time or bit number.

  By taking the logical product 2830 of the logical negation of the value of the register 2820 and the pattern matching signal, other pattern matching signals generated during a predetermined time or the number of bits from when the pattern matching signal is detected are excluded. Further, a corrected pattern matching signal 1 is obtained.

  Here, as an example of a predetermined time or the number of bits in which the register 2820 keeps the High state, there is a 16-bit time obtained by dividing 8 octets including the MFAS and the OTUk-OH of the OTN frame into 4 lanes. Shown in

[Example 14]
Example 14 will be described with reference to FIG. As shown in FIG. 30, even when the same bit string as the frame synchronization information exists immediately after the frame synchronization information and the frame synchronization information is immediately before the start of signal input to the physical port, the frame synchronization information immediately after the frame synchronization information The influence of the same bit string can be removed.

  As shown in FIG. 30, when signal input is started immediately after the frame synchronization information, the mask does not work on the same bit string as the frame synchronization information. Therefore, a new register 3010 is added as shown in FIG. The register 3010 is in a low state at the start of signal input, and is in a high state when a pattern matching signal is received. By taking the logical product 2830 of the register 3010, the register 2820 for masking, and the pattern matching signal, the corrected pattern matching signal 2 can be obtained.

  Here, a method of cutting off the first pattern matching signal after the start of signal input is shown. Instead, by adding a counter to the register 3010, a predetermined time interval or a plurality of pattern matching signal outputs can be cut off.

[Example 15]
When parallel transmission is performed with the configuration shown in FIG. 15, a bit string for pattern matching of each lane is as follows.
Lane 1: 110011110011
Lane 2: 100110100110,
Lane 3: 10000110001100
Lane 4: 110011100110
In the fifteenth embodiment, as shown in FIG. 31, a pattern matching circuit 601 for all lanes is provided at each port to perform pattern matching. Based on the pattern matching signals obtained in this way (16 in the case of 4 lanes), lane identification and skew amount calculation are performed.

  By using the lane identification method and the skew amount calculation method described in the above embodiment together, lane identification and the skew amount are calculated based on the 16 pattern matching signals as shown in FIG. It is possible. Specific examples are shown below.

  An example when combined with the method of the tenth embodiment will be described. Similar to the tenth embodiment, it is necessary to detect that the pattern matching signal is generated in all the lanes. FIG. 31 shows the simplest configuration example. A logical sum 3110 of pattern matching signals generated from a plurality of pattern matching circuits 601 is taken in each lane, and this is inputted to the register 1810 and the counter 1820 shown in the tenth embodiment. A predetermined time or number of bits is appropriately set, and lane identification and skew amount calculation are performed by the method described in the tenth embodiment.

In addition, there is a case where it is known that the correspondence between the physical port and the lane is one of the following cyclic relationships.
(Physical ports 1, 2, 3, 4)
= (Lane 1, 2, 3, 4) or (lane 2, 3, 4, 1) or (lane 3, 4, 1, 2) or (lane 4, 1, 2, 3)
In this case, as shown in FIG. 32, all the lane pattern match flags indicating that the pattern matching signals are generated in all the lanes in the same manner as in the tenth embodiment in each of the above four sets of physical ports and lanes. Detect. At this time, an all lane pattern match flag for detecting the occurrence of a pattern matching signal in all lanes is obtained from a set in which the correspondence between physical ports and lanes is correct. Calculate the amount.

  FIG. 33 shows an example of combination with Example 12 as an example of combination with the methods of Examples 11 and 12. Here, the pattern matching signal generation interval when pattern matching is performed on all lane signals using all matching pattern circuits 601 is stored in the counter value table 2210 in advance. Then, using all the pattern matching signal generation intervals obtained by pattern matching with the reception signals of the eleventh and twelfth embodiments and the generation intervals stored in advance in the counter value table 2210, the lane identification and the skew amount are determined. Calculation or transmission frame type determination is performed.

[Example 16]
Example 16 will be described. Taking an OTN maintenance frame as an example, if the FAS, which is frame synchronization information, is divided into 4 lanes, 12 bits of frame synchronization information flows per lane per frame time. However, when a short matching pattern of 12 bits is used, matching may occur in a portion other than the frame synchronization information in the frame. On the other hand, the payload portion or the like of the frame is a fixed value, and is known because a non-self-synchronizing scrambler is applied to the maintenance frame by repeating a specific bit string.

  Therefore, a bit string that exists only once in the known bit string is used instead of a bit string obtained when the frame synchronization information is made parallel as a matching pattern.

  The above method cannot cope with a case where there is an area in which a bit changes depending on a frame in one frame. For example, the OTN maintenance frame is an MFAS or OTUk-OH area or an FEC (Forward Error Correction) area that is calculated using these as an information bit string, and the SDH maintenance frame is an STM-N RSOH (Regenerator Section Overhead) area. However, in these areas, the length of the bit string is limited, and the bit string is limited to several types, which can be calculated in advance.

  Therefore, when there is a region where the bit changes depending on the frame as described above, a bit string which does not appear in that region as a matching pattern and exists only once in a known bit string whose bit does not change depending on the frame. Select. A general derivation method of a bit string generated only once used for matching is as follows. Since the pattern matching signal is obtained only once in the corresponding frame for each lane regardless of the value of the bit changing area, the pattern matching signal generation interval of each lane and the actually observed pattern matching when there is no skew The skew amount is calculated by taking the difference between the signal generation intervals.

  A method for deriving a specific bit string used as a pattern for detecting matching will be described below using an OTN maintenance frame as an example. As described above, in the OTN maintenance frame, most of the frame including the payload has a fixed value (the scrambler etc. is applied to the repetition of the specific pattern), but the MFAS and OTUk-OH areas and these are information. The FEC area calculated as a bit string can change from frame to frame.

  In order to derive the specific bit string, first, all values that can be taken by these variable regions are calculated on the receiving side. Specifically, since the MFAS and OTUk-OH areas can take any value, it is calculated what bit string the FEC area becomes in all the patterns. On the other hand, a bit area that does not change can be obtained in advance for each type of maintenance frame, and all receivable frame patterns are obtained.

Next, it is inspected whether any of the following arbitrary bit strings meets the following conditions for each lane and each maintenance frame, and if it is true, the bit string can be used as a bit string for detecting the pattern matching.
Appears only once in the bit area that does not change.
-All the bit strings appearing in the entire frame pattern do not include an area that can change even a part.

[Example 17]
G-AIS (Generic-AIS, OTUk-AIS), which is one of OTN maintenance signals, has no frame structure and no frame synchronization information. In g-AIS, a bit string having a period 2047 called PN-11 is repeatedly output. The seventeenth embodiment provides a method for performing lane identification and deskew when signals having such repetition periods are transmitted in parallel. A signal having a repetition period such as g-AIS has a repetition period even if it is interleaved with a plurality of lanes in parallel transmission. Generally, a signal of each lane is shifted by a certain number of bits. become. When g-AIS is bit-interleaved on four lanes, the signal of one lane has a period of 2047 bits as shown in FIG. 34, and is shifted by 511 bits from the signal of adjacent lanes.

  Example 17 will be described with reference to FIG. A pattern matching signal is first input to the register 1810, and the register 1810 enters a high state. At the same time, the counter 1820 starts counting. However, even if the counter 1820 that has already started counting receives the pattern matching signal again, the counter value is not reset. By taking the logical product 1830 of the four-lane register 1810, an all-lane pattern match flag for detecting that the pattern matching signal is generated in all the lanes is obtained. At this time, the all-lane pattern match flag is also used as a signal for resetting the registers 1810 and the counters 1820 of all the lanes. The register 1810 that has received the all-lane pattern match flag goes to a low state, and the counter 1820 stops counting and is reset. When an all lane pattern match flag for detecting that a pattern matching signal is generated in all lanes is generated, the skew amount calculation unit 1840 calculates the skew amount of each lane based on the value of the counter 1820 of each lane at that time. Calculate and output the calculated skew amount.

[Example 18]
As shown in FIG. 34, when the transmission signal is a predetermined periodic signal as in g-AIS, the repeated signal received by each lane on the receiving side is the same. In the g-AIS, the repetitive signal is shifted by 511 bits. Therefore, when the skew amount is small, as shown in the seventeenth embodiment, the lane 4, lane 3, lane 2, and lane 1 Can be identified.

  However, when the skew amount is large, there is a possibility that the arrival order of the periodic signals does not match the above lane number order, and lane identification becomes impossible. Therefore, bit inversion is performed on the transmission side so that the signal received on the reception side differs for each lane. In FIG. 15, since bit inversion is repeated in all lanes (non-inversion, inversion, inversion, non-inversion), the periodic signal received by the receiving side remains the same, and it is necessary to perform different bit inversion for each lane. is there.

An example of performing bit inversion different for each lane is shown below using FIG. FIG. 35 is the same as FIG. 15 except that an inverter is provided in lanes 3, 5, 6, 8, 9, 11, 14, and 15 of SFI-5 and bit inversion is performed. At this time, the repetition of bit inversion in each lane is as follows.
Lane 1: (Non-inverted, inverted, inverted, non-inverted)
Lane 2: (Non-inverted, inverted, non-inverted, inverted)
Lane 3: (Inverted, non-inverted, inverted, inverted)
Lane 2: (Non-inverted, inverted, non-inverted, non-inverted)
Thus, by performing different bit inversion for each lane, a different periodic signal can be transmitted or received for each lane. Further, by combining this with other embodiments, lane identification and skew amount calculation are possible.

  Next, the case where it combines with Example 12 is shown. When g-AIS is transmitted with the configuration shown in FIG. 35, the period of the periodic signal received by each lane is the period 2047 when there is no inverter and the least common multiple 8188 of period 4 in FIG. When the pattern matching signal generation interval is observed using the matching pattern 110011110011 for these four lane signals, it is as shown in FIG. Here, since the intervals of the three pattern matching signals are different in each lane, lane identification and skew amount calculation are performed by the method using the pattern matching signal interval described in the eleventh embodiment.

A deskew method using a conventional MLD will be described. A deskew method defined in the conventional SFI-5 will be described. It is an example of composition of Example 1 of the present invention. It is a detailed example of a structure of the receiving side of Example 1 of this invention. It is an example of optical skew calculation by Example 2 of this invention. It is an example of composition of Example 3 of the present invention. It is explanatory drawing of the pattern matching of Example 3 of this invention. It is explanatory drawing of the transmission by the pattern matching pulse width of Example 4 of this invention. It is explanatory drawing of the subject of Example 3 of this invention. It is an example of composition of Example 5 of the present invention. It is explanatory drawing of the pattern matching of Example 5 of this invention. It is an example of composition of Example 6 of the present invention. It is explanatory drawing of the pattern matching of Example 6 of this invention. It is an example of composition of Example 7 of the present invention. It is explanatory drawing of the pattern matching of Example 7 of this invention. It is an example of composition of Example 8 of the present invention. It is explanatory drawing of the change of the matching pattern of Example 9 of this invention. It is an example of a structure of Example 10 of this invention. 15 shows the position of a bit string where pattern matching occurs when ODUk-OCI is transmitted with the configuration shown in FIG. The position of the bit sequence which pattern matching generate | occur | produces of Example 11 of this invention is illustrated. The example which used the generation interval of two adjacent pattern matching signals as a pattern matching signal generation interval of Example 11 of this invention is shown. It is an example of the counter value table of Example 11 of this invention. The example which used the generation interval of the non-adjacent pattern matching signal as a pattern matching signal generation interval of Example 11 of this invention is shown. An example of the operation of the memory of FIG. 23 will be described. An example of memory operation that saves the counter value table area will be described. An example in which an arbitrarily selected pattern matching signal generation interval is used as the pattern matching signal generation interval according to the eleventh embodiment of the present invention will be described. An example of a bit string at the beginning of an OTN frame is shown. The structural example and operation example of Example 13 of this invention are shown. An example of a predetermined time or number of bits for which the register continues to take a high state is shown. The structural example and operation example of Example 14 of this invention are shown. The simplest structural example of Example 15 of this invention is shown. The structural example at the time of combining Example 10 and Example 15 of this invention is shown. The structural example at the time of combining Example 12 and Example 15 of this invention is shown. The structural example of Example 17 of this invention is shown. It is explanatory drawing of the pattern matching of Example 18 of this invention. The position of the bit string where pattern matching occurs when Example 11 and Example 18 of the present invention are combined is illustrated.

Explanation of symbols

300 Parallel Optical Transmission System 311 Transmission Side Framer 312 Transmission Side Converter 313 Parallel Optical Transmission Module 321 Optical Transmission Path 331 Reception Side Framer 332 Reception Side Converter 333 Parallel Optical Reception Module 334 FPGA or CPU
411 Frame synchronization information extraction unit 412, 424 SFI-5 interface 421 Buffer 422 Delay unit 423 Interleave unit 441 OOF (out of frame synchronization) / LOS (signal loss) detection unit 442 Delay amount determination unit 601 Pattern matching unit 1201, 1202, 1401 Inverter 1613 Serial conversion optical transmission module 1621 Serial optical transmission line 1633 Parallel conversion optical transmission module 1810 Register 1820 Counter 1830 AND gate 1840 Skew amount calculation unit 2110 Counter value table and counter value comparison unit 2120, 2130 Counter 2210 Counter value table 2220 Adjacent One matching signal generation interval 2230 Distance to frame synchronization information 2310 Memory 2810 Ma Kukaunta 2820 register 2830 AND gate 3010 register 3110 OR gate

Claims (30)

A method of performing deskew between lanes on the receiving side of a parallel optical transmission system,
Detecting pattern matching based on a plurality of specific bit strings simultaneously for each lane;
Identifying the lane and calculating a skew amount based on detection of the plurality of pattern matchings;
Determining a delay amount to be added to one or more lanes in which the pattern matching is detected;
A parallel transmission method comprising: reading a received signal from the received signal buffer of the one or more lanes according to the delay amount. Generating a signal indicating that a pattern is matched when the pattern matching is detected over a predetermined number of consecutive transmission frames per lane;
Determining a skew between the lanes based on a signal indicating that the pattern for each lane is matched;
Parallel transmission method of claim 1, further comprising the step, defining a different amount of delay for each of the lanes to deskew the skew. The parallel transmission method according to claim 2 , wherein the signal indicating that the pattern matches is a pulse signal. The parallel transmission method according to claim 3 , wherein a pulse width of the pulse signal is proportional to an amount of skew generated in a corresponding lane. When N <M, where N and M are natural numbers, on the transmission side of the parallel optical transmission system,
Interleaving and transmitting one or more bits to M lanes, and demultiplexing the N lanes to the M lanes in one or more bits on the receiving side of the parallel optical transmission system. The parallel transmission method according to claim 2 , further comprising: interleaving and inverting the signal of the one or more lanes of the M lanes. The specific bit sequence is configurable for each of the lane, changes every predetermined time or number of bits, a parallel transmission method of claim 1, wherein. A step of calculating a skew between the lanes from the pattern matching generation interval for each lane when the pattern matching is detected in all the lanes within a predetermined time or less than a predetermined number of bits; The parallel transmission method according to claim 1 . Preliminarily storing the pattern matching occurrence interval based on the specific bit string;
Measuring the interval of generation of the pattern matching from a received signal of the lanes, and parallel transmission of said step of calculating the amount of skew between the basis of the generation interval of the measured pattern matching lane, further comprising claim 1, wherein the Method. 9. The parallel transmission method according to claim 8 , further comprising identifying the lane based on the predetermined pattern matching occurrence interval and the measured pattern matching occurrence interval. 9. The parallel transmission method according to claim 8 , wherein the predetermined pattern matching occurrence interval is determined to be unique within a predetermined time or within a predetermined number of bits. 9. The parallel transmission method according to claim 8 , further comprising: determining a type of transmission frame based on the measured pattern matching occurrence interval. Wherein each lane, the pattern matching between or within a predetermined number of bits less than a predetermined time from the detection of the parallel transmission method of claim 1, further comprising the step, masking the detection of the pattern matching. Wherein each lane, the step of masking the detection of said pattern matching a predetermined time or number from a received signal is input, further parallel transmission method according to claim 1, comprising a. The particular bit sequence are not appearing in the area changes every frame in the transmission frame, only appearing and once in the region that does not change from frame to frame of the transmission frame, the parallel transmission method according to claim 1, wherein . Wherein the transmission side of the parallel optical transmission system, performing a signal inverted by different repeat for each of the lanes, further parallel transmission method according to claim 7, 8 or 14, wherein having. A device that performs deskew between lanes on the receiving side of a parallel optical transmission system,
Means for detecting pattern matching based on a plurality of specific bit strings simultaneously for each lane;
Means for identifying the lane and calculating a skew amount based on detection of the plurality of pattern matchings;
A parallel transmission apparatus comprising: means for determining a delay amount to be added to one or a plurality of lanes in which the pattern matching is detected; and a means for reading out a received signal from a reception signal buffer of the one or more lanes according to the delay amount . Means for generating a signal indicating that a pattern is matched when the pattern matching is detected over a predetermined number of consecutive transmission frames for each lane;
Means for determining a skew between the lanes based on a signal indicating that the pattern for each lane is matched;
The parallel transmission apparatus according to claim 16 , further comprising means for determining a different delay amount for each lane so as to de-skew the skew. The parallel transmission apparatus according to claim 17 , wherein the signal indicating that the pattern matches is a pulse signal. The parallel transmission apparatus according to claim 18 , wherein a pulse width of the pulse signal is proportional to an amount of skew generated in a corresponding lane. When N <M, where N and M are natural numbers, on the transmission side of the parallel optical transmission system,
Means for interleaving and transmitting one or more bits to M lanes, and demultiplexing the N lanes to the M lanes in one or more bits on the receiving side of the parallel optical transmission system. 18. The parallel transmission apparatus according to claim 17 , further comprising means for interleaving and inverting the signal of the one or more lanes of the M lanes. 17. The parallel transmission apparatus according to claim 16 , wherein the specific bit string can be set for each lane and changes for each predetermined time or number of bits. Means for calculating a skew between the lanes from an interval of the pattern matching for each lane when the pattern matching is detected in all the lanes within a predetermined time or within a predetermined number of bits or less; The parallel transmission apparatus according to claim 16 . Means for predetermining and storing the occurrence interval of the pattern matching based on the specific bit string;
The parallel transmission according to claim 16 , further comprising: means for measuring the occurrence interval of the pattern matching from the received signal of the lane; and means for calculating a skew amount between the lanes based on the measured occurrence interval of the pattern matching. apparatus. 24. The parallel transmission apparatus according to claim 23 , further comprising means for identifying the lane based on the predetermined pattern matching occurrence interval and the measured pattern matching occurrence interval. The parallel transmission apparatus according to claim 23 , wherein the predetermined pattern matching occurrence interval is determined to be unique within a predetermined time or within a predetermined number of bits. The parallel transmission apparatus according to claim 23 , further comprising means for determining a type of transmission frame based on the measured pattern matching occurrence interval. 17. The parallel transmission apparatus according to claim 16 , further comprising means for masking detection of the pattern matching within a predetermined time or not more than a predetermined number of bits after the pattern matching is detected for each lane. The parallel transmission apparatus according to claim 16 , further comprising means for masking detection of the pattern matching for a predetermined time or number of times after a reception signal is input for each lane. The parallel transmission apparatus according to claim 16 , wherein the specific bit string does not appear in a region that changes for each frame in the transmission frame, and appears only once in a region that does not change for each frame in the transmission frame. . 30. The parallel transmission apparatus according to claim 22, 23, or 29 , further comprising means for performing signal inversion by different repetition for each lane on a transmission side of the parallel optical transmission system.

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