JP2785755B2 - Hitless switching device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hitless switching device for securing normal frame synchronization in a short time after a recovery from a momentary interruption in a digital signal sent from a transmitting device. A hitless switching device that reduces the loss of frame synchronization due to momentary interruption when switching from a working system to a protection system due to an error occurring in a transmitter equipped with a working system and a protection system transmitter with frame synchronization. Related to

[0002]

2. Description of the Related Art In a transmitting apparatus for transmitting a digital signal such as video data through a radio line, when an abnormality occurs in a transmitter, a communication between an active system and a standby system is usually performed in order to avoid a long interruption of communication. System transmitter.
When an abnormality in the active system is detected, the system is immediately switched to the standby system and transmission is continued.

FIG. 4 shows an outline of the configuration of a digital data radio transmitting apparatus provided with a working system and a protection system transmitter conventionally used. The digital signal 101 to be transmitted has a frame structure, and a predetermined frame pattern for frame synchronization is arranged at the head of each frame. Digital signal 101
Is split into two, first and second transmitters 102,
103 are respectively input. First transmitter 102
Detects a frame pattern from the digital signal 101 and outputs a frame pulse 104 indicating the timing of the head position of each frame.

[0004] The second transmitter 103 includes the first transmitter 1
02, the frame pulse 104 output is input, and these transmitters are configured so that the transmission timing of each frame coincides with each other. When the first and second transmitters both detect an abnormality of their own, they output abnormality detection signals 105 ₁ and 105 ₂ indicating the abnormality. Switch 1
A circuit portion 06 selects one of the outputs of the first and second transmitters and performs transmission to the receiving device. For example, the first transmitter 102 is used as an active system, and its output is normally selected and transmitted. First transmitter 1
When the abnormality detection signal 105 ₁ from 02 is input, the switch 106 selectively sends an output from the second transmitter 103 which had been hot standby as a standby system.

Since the outputs of the first and second transmitters are frame-synchronized with each other and have the same transmission timing, even when switching from the active system to the standby system, the positions of the frames before and after the switching are changed. Are never different. When switching is performed by a relay circuit, usually
It takes 0 milliseconds, during which time the transmission output is momentarily interrupted.

FIG. 5 shows an outline of the configuration of a digital signal receiving apparatus conventionally used.
The receiving device includes a demodulator 111 for demodulating a received digital signal, and a frame pulse generator 114 for detecting a frame pattern from the demodulated data signal 112 and generating a frame pulse 113 representing a head position of the frame. Further, the demodulator 111 has a function of extracting a clock component included in the received digital signal, and outputting a reproduced clock signal 115 for sampling and reproducing the demodulated data signal. Demodulated data signal 112 is stored in a predetermined area of a RAM (random access memory) not shown.

The frame synchronization counter 116 is a circuit for generating an address for reading a data signal stored in the RAM. The frame synchronization counter 116
The reproduction clock signal 115 is counted, and each time the frame pulse 113 is input, the count value is initialized. For example, when the received digital signal is a video signal, an area for storing audio data and an area for storing image data are assigned in frame units. At this time, to read the audio data, the head address of the area where the audio data is stored is loaded as the initial value of the frame synchronization counter 116. When reading video data, the head address of the corresponding area is loaded when a frame pulse is input. As described above, in the receiving apparatus, the address information is obtained by operating the frame synchronization counter 116 based on the reproduction clock and the frame pulse, and the demodulated digital data is taken out from the RAM.

Japanese Patent Publication No. Sho 62-28903 discloses a hitless switching device that prevents loss of frame synchronization between a working transmitter and a backup transmitter on the transmitting device side. As shown in FIG. 4, normally, the frame timing from the active system always matches the frame timing of the standby system with that of the active system. However, if noise is mixed in the frame pulse, synchronization is lost. Therefore, in the hitless switching device according to the prior art, the frame timing of the standby system is made to coincide with that of the active system by the frame pulse from the active system only when an abnormality of the transmitter in the active system is detected.

[0009]

[Problems to be Solved by the Invention] Japanese Patent Publication No. 62-2890
In the prior art described in Japanese Patent Application Laid-Open No. 3 (1999) -1995, the frame timings of the active system and the standby system can be surely matched, so that the phases of the transmitted frames before and after the switching of the transmitter are matched. However, since the transmission output is momentarily interrupted at the time of switching, even if the frame timing on the transmitting side does not change, the receiving device may lose frame synchronization. That is, when the transmitting device switches from the working system to the standby system, the high-frequency power input to the receiving device is temporarily lost, and the reproduced clock cannot be output. Therefore, the counting operation of the frame synchronization counter stops. When the instantaneous interruption is recovered, the frame timing on the transmission side is the same as before the instantaneous interruption, but the readout address of the demodulated data is delayed by the time during which the frame synchronization counter is stopped only on the receiving device side. .

On the receiving side, in order to recover the frame synchronization, the clock is pulled in after the recovery from the instantaneous interruption to output the reproduced clock, and the frame pulse generator waits until the head position of the frame arrives after the instantaneous interruption. Needs to output a frame pulse to initialize the frame synchronization counter. That is, there is a problem that a burst error occurs by the sum of the switching time on the transmitting device side, the clock pull-in time, and the time until frame synchronization is restored.

SUMMARY OF THE INVENTION An object of the present invention is to provide a hitless switching device capable of recovering from loss of frame synchronization in a short time when the instantaneous interruption of a received signal is recovered.

[0012]

According to the first aspect of the present invention, there is provided a receiving means for receiving a frame-structured digital signal, and detecting and receiving a clock component contained in the digital signal received by the receiving means. Reproduction clock generation means for generating a reproduction clock for reproducing a digital signal, and frame synchronization pulse generation means for generating a frame synchronization pulse for identifying each frame position of the digital signal based on the digital signal received by the reception means Clock signal output means for outputting a clock signal having the same frequency as the clock component of the digital signal; reproduced clock cutoff detecting means for detecting whether or not the reproduced clock output from the reproduced clock generating means is cut off; The reproduction clock disconnection detecting means detects the reproduction clock disconnection. A clock signal output from the clock signal output means, and a clock selection means for selecting a reproduction clock when no interruption of the reproduction clock is detected, and a clock signal initialized by a frame synchronization pulse and selected by the clock selection means. The hitless switching device is provided with a frame synchronization counter which outputs an address signal indicating a position at which data is extracted from each frame of the digital signal received by counting the clocks received.

That is, in the first aspect of the invention, while the input digital signal is cut off, the counting operation of the frame synchronization counter is continued using the internal clock having the same frequency as the reproduction clock. As a result, the address output from the frame synchronization counter can be adjusted to the frame timing on the transmission side immediately after the momentary interruption is recovered.

According to the second aspect of the present invention, a receiving means for receiving a frame-structured digital signal, and a clock component included in the digital signal received by the receiving means for detecting and reproducing the received digital signal. Reproduction clock generation means for generating a reproduction clock of
A frame synchronizing pulse generating means for generating a frame synchronizing pulse for identifying each frame position of the digital signal based on the digital signal received by the receiving means, and a clock having a shorter cycle than the reproduction clock output from the reproduction clock generating means A clock signal output unit for outputting a signal; a reproduction clock interruption detection unit for detecting the interruption and recovery of the reproduction clock output from the reproduction clock generation unit; and an interruption of the reproduction clock detected by the reproduction clock interruption detection unit. Disconnection time detecting means for measuring the time from recovery until recovery is detected, and a data extraction position in each frame of a digital signal received by counting a clock initialized and input by a frame synchronization pulse. Frame synchronization counter that outputs an address signal indicating When the recovery of the reproduction clock is detected by the reproduction clock disconnection detecting means, the counting operation of the frame synchronization counter is performed by the clock signal, whereby the count value for the time measured by the disconnection detection time detecting means of the frame synchronization counter is detected. The hitless switching device is provided with clock selection means for inputting a clock signal to the frame synchronization counter for a time necessary to recover the delay and for inputting the reproduced clock to the frame synchronization counter during other periods.

That is, according to the second aspect of the present invention, when the instantaneous interruption is recovered, the count value of the frame synchronization counter is delayed by the time of the interruption. Therefore, the time of the interruption is measured, and the frame synchronization counter counts with a clock having a shorter cycle than the reproduction clock for a period necessary to recover the delay of the count value for the time.

According to the third aspect of the present invention, a receiving means for receiving a digital signal having a frame structure, and a clock component included in the digital signal received by the receiving means are detected to reproduce the received digital signal. Reproduction clock generation means for generating a reproduction clock of
Frame synchronizing pulse generating means for generating a frame synchronizing pulse for identifying each frame position of the digital signal based on the digital signal received by the receiving means, and disconnection and recovery of the reproduced clock output from the reproduced clock generating means. Recovery clock loss detection means for detecting, recovery clock loss detection means for measuring a time from when the recovery of the recovery clock is detected by the recovery clock loss detection means to when recovery of the recovery clock is detected, and initializing by the frame synchronization pulse. A frame synchronization counter for outputting an address signal indicating a data extraction position in each frame of the digital signal received by counting the reproduced clock and recovering the recovery of the reproduction clock from the reproduction clock disconnection detecting means. When the disconnection detection time detection means of the frame synchronization counter Ri is made to and a disconnection time compensation initializing means for initializing the frame synchronization counter hitless switching apparatus by the value calculated count value required to catch up measured count time duration.

That is, according to the third aspect of the present invention, when the instantaneous interruption is recovered, the count value of the frame synchronization counter is delayed by a time corresponding to the interruption. Therefore, the time during which the interruption has been stopped is measured, and the count value enough to recover the delay of the count value for this time is reloaded into the frame synchronization counter when the instantaneous interruption is recovered. As a result, the address output from the frame synchronization counter can be adjusted to the frame timing on the transmission side immediately after the recovery from the momentary interruption.

According to the fourth aspect of the present invention, the digital signal received by the receiving means is provided with an active system and a standby system transmitting apparatus which are synchronized with each other, and for a predetermined time when switching between the active system and the standby system. Sent from the transmitting station where transmission is momentarily interrupted.

In other words, according to the fourth aspect of the present invention, since the transmitting device of the active system and the transmitting device of the standby system are frame-synchronized with each other, the receiving side corrects the count value of the frame synchronization counter, etc. Immediately after the recovery, the same frame timing between transmission and reception is secured.

[0020]

FIG. 1 shows an outline of the configuration of a hitless switching device according to an embodiment of the present invention. A digital signal received by the hitless switching device (hereinafter referred to as a receiving device) is transmitted from a transmitting device having the same configuration as that shown in FIG. That is, the transmitting apparatus includes a working system and a protection system transmitter, and the framing counter of the protection system operates based on the frame pulse output from the working system transmitter, so that the working system and the protection system operate. The phase of the frame synchronization of the transmitter is matched. When an abnormality in the active system is detected, the transmitter is switched from the active system to the standby system in about several tens of milliseconds.

The receiving apparatus shown in FIG. 2 includes a demodulator 11 for demodulating a signal received through a radio channel and outputting demodulated data and a reproduced clock. Demodulated data 12 output from the demodulator 11 is input to a frame pulse generator 13 that detects a synchronization frame pattern and generates a frame pulse. The frame pulse 14 is input to a frame synchronization counter 15 that generates address extraction information of data in each frame. The reproduction clock 16 output from the demodulator 11 includes a disconnection detection circuit 17 that detects disconnection of the reproduction clock 16 and recovery thereof,
The signal is input to a selector 19 that switches a clock 18 input to the frame synchronization counter 15. Selector 1
9, a clock signal 21 having substantially the same frequency as the reproduction clock 16 is input from a crystal oscillator 22. Since the bit rate of the digital signal sent from the transmitting device is known, the frequency of the clock signal 21 output from the crystal oscillator 22 is set in accordance therewith.

The frame synchronization counter 15 receives the clock 1
This is a counter for counting 8, and the number of bits to be counted is equal to or more than the number of digits required to specify the data extraction position in the frame. Also, the frame synchronization counter 15
Is the frame pulse from the frame pulse generator 13
Each time is input, the count value is initialized. The selector 19 receives a disconnection detection signal 23 from the disconnection detection circuit 17 as a clock selection signal to be output. The selector 19 outputs the clock signal 21 output from the crystal oscillator 22 when the disconnection detection signal 23 is in a “high” state, and outputs the clock signal 21 when the disconnection detection signal 23 is in a “low” state.
The reproduction clock signal 16 is output.

When the signal from the transmitting device is arriving, the reproduction clock 16 is output from the demodulator 11, and the disconnection detection circuit 17 outputs the disconnection detection signal 23 in the “low” state to the selector 19. Thereby, the frame synchronization counter 1
A reproduction clock 16 is input to 5. If an error occurs in the active transmitter of the transmitting device and switching to the standby system occurs, input power to the receiving device is lost during the switching operation. Therefore, the demodulator 11 does not output the demodulated data 12 and the reproduction clock 16. Disconnection detection circuit 17
Detects that the reproduction clock 16 has been cut off, and changes the cut-off detection signal 23 from the “low” state to the “high state.” Accordingly, the selector 19 sets the crystal oscillator 22
And selectively outputs the clock signal 21 from. The frame synchronization counter continues the counting operation during the switching period by counting the clock signal 21 from the crystal oscillator 22.

When the switching operation in the transmitting device is completed and the recovered clock 16 is output again from the demodulator 11, the recovery of the recovered clock is detected by the disconnection detecting circuit 17 and the disconnection detection signal 23 is set to the "low" state. Return. As a result, the reproduction clock 16 is input to the frame synchronization counter 15,
Return to normal state. As described above, even during the switching operation period of the transmission device, the counting operation of the frame synchronization counter 15 is continued by the clock signal 21 from the internal crystal oscillator 22, so that the phase of the frame synchronization is prevented from being out of phase. be able to. Therefore, the data in the frame can be taken out at the same phase as the transmitting side immediately after the switching in the transmitting device is completed and the demodulated data 12 and the reproduced clock 16 start to be output again.

First Modified Example

In the first modification, the time during which the reproduction clock is cut off is measured. Then, when the recovered clock is recovered, a clock having a shorter cycle than the recovered clock is supplied to the frame synchronization counter for a necessary time, thereby recovering the delay of the count value of the frame synchronization counter during the interruption. .

FIG. 2 shows an outline of the configuration of the receiving apparatus according to the first modification. The same parts as those of the receiving apparatus shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The first modification does not include a crystal oscillator or a selector. Further, instead of the disconnection detection circuit, a disconnection time detection circuit 31 for measuring the time during which the reproduction clock is disconnected is provided. The disconnection time detection circuit 31
The correction signal 33 for changing the counting speed of the frame synchronization counter 32 is output only for a predetermined period according to the time when the reproduction clock is cut off. While the correction signal 33 is being input, the frame synchronization counter 32
It has a function of outputting an address signal obtained by counting the input reproduction clock faster than usual.

For example, while the correction signal 33 is not input, the count value is incremented by one each time the reproduction clock is input, and while the correction signal 33 is input, the count value is increased each time the reproduction clock is input. Increment the value by two. The interruption time detection circuit 31 is provided with a table in which a correspondence between the time when the reproduction quok 16 is interrupted and the time when the correction signal 33 is output is registered in advance. For example, assuming that the frame synchronization counter 32 counts the reproduction clock at twice the increase speed while the correction signal 33 is being output, the output time of the correction signal 33 is the same as the interruption time. Also,
When the frame synchronization counter 32 counts at a quadruple increase speed, the output time of the correction signal 33 is one third of the interruption time. Assuming that the interruption time is “X”, the output time of the correction signal is “Y”, and the magnification of the counting speed during the correction period is “K”, the relationship of K × Y = X + Y holds. Therefore, the correction time “Y” is Y = X ÷ (K−1).

As described above, by increasing the counting speed by the correction time obtained by multiplying the counting speed of the frame synchronizing counter by the time cut off after the recovered clock is recovered,
After the correction time, the address output from the frame synchronization counter can be returned to the same value as when no instantaneous interruption occurred. For example, if the momentary interruption has recovered immediately after the frame pattern, no frame pulse is output until the next frame pattern arrives. Therefore,
Unless the delay of the count value due to the instantaneous interruption is compensated, the synchronization is lost until the next frame pulse is output. By increasing the count speed of the reproduction clock for a necessary period to recover the delay of the count value, the time during which synchronization is lost can be shortened.

FIG. 3 shows an example of a circuit configuration of a frame synchronization counter capable of increasing the counting speed. The frame synchronization counter includes a D flip-flop circuit 42 and an exclusive OR circuit 44 to which the inverted output 43 of the D flip-flop circuit 42 and the correction signal 33 are input. Further, a counter 45 for outputting an address and a non-inverted output 41 of the D flip-flop circuit 41 are provided.
And a logical sum circuit 46 for calculating the logical sum of the correction signals. The output of the exclusive OR circuit 44 is input as a data signal of the D flip-flop circuit 42. The output of the OR circuit 46 is input as an enable signal of the counter 45. Each of the D flip-flop circuit 42 and the counter 45 has a reproduction clock 1
6 is input as a clock signal.

This frame synchronization counter outputs the correction signal 3
When 3 is "0", the reproduction clock 16 is counted every two times, and when the correction signal 33 is "1", the reproduction clock 16 is counted every time. While the correction signal 33 is "1", the enable signal is also "1", and the counter 45 counts the reproduction clock every period during that time. If the inverted output 43 is "0" when the correction signal 33 is "0", the output of the exclusive OR circuit 44 becomes "0". Therefore, the inverted output 43 becomes "1" at the next clock timing. At this time, the output of the exclusive OR circuit 44 changes to "1", and at the next clock timing, the inverted output 43 becomes "0". Thus, D
The flip-flop circuit 42 divides the frequency of the reproduction clock 16 by two. Therefore, the counter 45 counts once every two cycles of the reproduction clock 16.

In the first modification, the count value of the frame synchronization counter is changed to recover the delay of the count value during the interruption. May be added at one time when is recovered. The correction value of the count value is registered in the disconnection time detection circuit in advance in association with the disconnection time. The value obtained by multiplying the frequency of the reproduction clock by the interruption time is the correction value. The disconnection time detection circuit detects the time when the reproduction clock is disconnected, reads a correction value corresponding to the disconnection time when the reproduction clock is recovered, and reloads the counter value together with the correction value to initialize the count value of the counter. Output a signal. The frame synchronization counter includes an adding circuit that adds the count value and the correction value input from the break time detection circuit. Then, when the reload signal is input from the interruption time detecting circuit, the output value of the adding circuit is initialized as the count value of the counter. By doing so, when the recovered clock is recovered, the delay of the count value generated during the interruption can be recovered at a stretch, and loss of synchronization can be avoided.

[0033]

As described above, according to the first aspect of the present invention, the counting operation of the frame synchronization counter using the internal clock having the same frequency as the reproduction clock while the input digital signal is interrupted. Has been continued. As a result, the address output from the frame synchronization counter matches the phase of the frame on the transmission side immediately after the momentary interruption is recovered, and the frame can be prevented from being out of synchronization.

According to the second aspect of the present invention, the time during which disconnection is detected is measured, and when the instantaneous interruption is recovered, a clock having a shorter cycle than the reproduced clock is supplied to the frame synchronization counter, and the disconnection is performed. It is catching up the count value in time. Thus, the period during which frame synchronization is lost can be shortened.

Further, according to the third aspect of the present invention, the time during which the disconnection is stopped is measured, and when the momentary interruption is recovered, the count value enough to recover the delay of the count value corresponding to the interruption time is reloaded into the frame synchronization counter. doing. As a result, the address output from the frame synchronization counter can be matched with the phase of the frame on the transmission side immediately after the recovery from the instantaneous interruption, and loss of frame synchronization can be avoided.

According to the fourth aspect of the present invention, the frame synchronization between the active system and the standby system is established on the transmitting device side, so that the receiving side compensates for the deviation of the count value of the frame synchronization counter, thereby Immediately after the recovery from the momentary interruption, the phases of the frames can be matched between transmission and reception.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an outline of a configuration of a hitless switching device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an outline of a configuration of a receiving device according to a first modified example.

FIG. 3 is a block diagram showing a circuit configuration of a frame synchronization counter capable of changing a counting speed.

FIG. 4 is a block diagram showing an outline of a configuration of a digital data radio transmitting apparatus including a working transmitter and a backup transmitter which are conventionally used.

FIG. 5 is a block diagram showing an outline of a configuration of a conventionally used digital signal receiving apparatus.

[Explanation of symbols]

 Reference Signs List 11 demodulator 13 frame pulse generator 15, 32 frame synchronization counter 17 disconnection detection circuit 19 selector 22 crystal oscillator 31 disconnection time detection circuit

Claims (4)

(57) [Claims] 1. A receiving means for receiving a frame-structured digital signal, and a clock component included in the digital signal received by the receiving means is detected to generate a reproduction clock for reproducing the received digital signal. Reproduction clock generation means; frame synchronization pulse generation means for generating a frame synchronization pulse for identifying each frame position of the digital signal based on the digital signal received by the reception means; and the same clock component as the digital signal Clock signal output means for outputting a clock signal having a frequency; reproduction clock cutoff detection means for detecting whether or not the reproduction clock output from the reproduction clock generation means has been cut off; When a clock loss is detected, the clock Clock selection means for selecting a clock signal output from the clock signal output means, and selecting the reproduction clock when the interruption of the reproduction clock is not detected; and initialization by the frame synchronization pulse and selection by the clock selection means. And a frame synchronization counter for outputting an address signal indicating a data extraction position in each frame of the digital signal received by counting the number of clocks received. 2. Receiving means for receiving a frame-structured digital signal, and detecting a clock component included in the digital signal received by the receiving means to generate a reproduction clock for reproducing the received digital signal. Reproduction clock generation means; frame synchronization pulse generation means for generating a frame synchronization pulse for identifying each frame position of the digital signal based on the digital signal received by the reception means; and output from the reproduction clock generation means. Clock signal output means for outputting a clock signal having a shorter cycle than the reproduced clock to be reproduced, reproduced clock cutoff detecting means for detecting the cutoff and recovery of the reproduced clock output from the reproduced clock generating means, Means that the interruption of the reproduction clock is detected by Disconnection time detecting means for measuring the time until recovery of the digital signal is detected, and extracting data in each frame of the digital signal received by counting the clocks initialized and input by the frame synchronization pulse. A frame synchronization counter for outputting an address signal indicating a position; and when the recovery of the recovery of the reproduction clock is detected by the reproduction clock disconnection detection means, the frame synchronization is performed by the clock signal. The clock signal is input to the frame synchronization counter only for a time necessary to recover the delay of the count value of the time measured by the disconnection detection time detection means of the counter, and the reproduction clock is input to the frame synchronization counter in other periods. Clock selection means to perform Hitless switching device. 3. A receiving means for receiving a digital signal having a frame structure, and detecting a clock component included in the digital signal received by the receiving means to generate a reproduction clock for reproducing the received digital signal. Reproduction clock generation means; frame synchronization pulse generation means for generating a frame synchronization pulse for identifying each frame position of the digital signal based on the digital signal received by the reception means; and output from the reproduction clock generation means. Clock recovery detecting means for detecting the recovery of the recovery clock and recovery thereof, and a recovery time for measuring the time from when the recovery of the recovery clock is detected by the recovery clock recovery detecting means until recovery is detected. Detection means; initialized by the frame synchronization pulse and the reproduction A frame synchronization counter that outputs an address signal indicating a data extraction position in each frame of the digital signal received by counting the lock, and when the recovery of the recovery clock is detected by the recovery clock loss detection means, And a disconnection time compensation initializing means for obtaining a count value necessary for recovering the delay of the count value of the time measured by the disconnection detection time detecting means of the frame synchronization counter and initializing the frame synchronization counter based on this value. A hitless switching device, characterized in that: 4. A digital signal received by said receiving means is provided with an active transmission system and a standby transmission device which are frame-synchronized with each other, and transmission is momentarily interrupted for a predetermined time when switching between the active transmission system and the standby transmission system. 4. The hitless switching device according to claim 1, wherein the hitless switching device is transmitted from a transmitting station.