JP3157029B2 - Data receiving device - Google Patents

Data receiving device

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Publication number
JP3157029B2
JP3157029B2 JP04288192A JP4288192A JP3157029B2 JP 3157029 B2 JP3157029 B2 JP 3157029B2 JP 04288192 A JP04288192 A JP 04288192A JP 4288192 A JP4288192 A JP 4288192A JP 3157029 B2 JP3157029 B2 JP 3157029B2
Authority
JP
Japan
Prior art keywords
clock
data
latch
means
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP04288192A
Other languages
Japanese (ja)
Other versions
JPH05244134A (en
Inventor
仁 厚川
晃一 小野田
Original Assignee
沖電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 沖電気工業株式会社 filed Critical 沖電気工業株式会社
Priority to JP04288192A priority Critical patent/JP3157029B2/en
Publication of JPH05244134A publication Critical patent/JPH05244134A/en
Application granted granted Critical
Publication of JP3157029B2 publication Critical patent/JP3157029B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving apparatus.
And, there is so suitable be applied for example exchange such as high-speed data received package (board), etc. in the inside of the.

[0002]

2. Description of the Related Art Recently, in data transmission between packages (boards) in an exchange system, for example, 10M
In order to realize high-speed transmission of bps or more, a bit buffer circuit for phase adjustment is required in the receiving side package in consideration of the steady phase error of the transmitting package (board) and the line length difference between the receiving package and the package. , necessary to transmit the like in addition to the bit phase information and frame phase information data Ru Tei occur.

[0003] Therefore, a three-wire interface using a data signal, a clock signal, and a frame signal is generally used as an interface signal between the transmission package and the reception package. With such an interface, the receiving package takes in the data signal, the clock signal, and the frame signal into the bit buffer circuit, and adjusts the bit phase, the frame phase, and the like of the data signal with the clock signal and the frame signal.

[0004]

However, in general, a large number of packages are mounted in an exchange system or the like. For example, data is transferred from one package A to m receiving packages such as other packages B, C. May need to be transmitted. In such a case, if the above-described conventional three-wire interface is used, three-wire × m interface lines are required, the number of pins required for each interface connector is increased, and the interface efficiency is extremely poor. There is a problem that the size also increases.

[0005] Also, when the number of interface lines is increased,
When sending these interface signals to the line,
The number of elements of the high-speed driver and the high-speed receiver on the receiving side also increases. These high-speed drivers and high-speed receivers generally have high power consumption, and therefore have a problem of increasing the overall power consumption.

[0006] The present invention has been made in view of the above problems, and an object of the present invention is to provide a data receiving apparatus which can be applied to efficient data transmission using a minimum number of interface signal lines. is there.

[0007]

SUMMARY OF THE INVENTION A data receiving apparatus according to the present invention is provided.
Location, in order to achieve the above object, has the following characteristic each means.

That is, (a) one bit of a received data string
High period including n / 2 pulses (n is an integer of 3 or more) in the period
Fast clock and a clock that generates readout frame pulses.
Lock generating means; and (b) receiving from the high-speed clock.
The phase differs by a period obtained by dividing one bit period of the data string into n equal parts.
, N write clocks having a duty ratio of 1: (n-1)
Write clock generating means for generating a lock;
The received data string is divided into n write clocks having different phases.
And outputs n pieces of latched data.
Latch means, and (d) capturing the n pieces of latch data
The latch data with the same logic value change timing is the fastest.
Data, and from the latch data, one of the received data
Half of bit period or closest to half of it
Latch data whose phase is delayed by the period and this latch
Form a selection signal to indicate a write clock for data
(E) converting the n pieces of latch data into
Capture and select the latch data indicated by the above selection signal
And (f) writing the n pieces of data.
The clock is captured and the write clock specified by the selection signal
Write clock selecting means for selecting lock;
To the latch data output from the latch data selection means.
To detect the included frame pattern, written inclusive frame
Frame phase synchronizing means for forming a system pulse;
The high-speed clock is divided to form the read clock.
Peripheral means; and (i) output from the write clock selecting means.
Write clock from the frame phase synchronization means
Latch data based on the write frame pulse of
Of the latch data output from the selection means,
Write the part excluding the pattern, and
Lock and read synchronized with the above read frame pulse
First-in first-out bit buffer means for performing
You.

[0009]

SUMMARY OF] According to the data receiving apparatus of the present invention, compared with the past, the number of signal Route can mitigate, it is possible to realize a data receiving device for high-speed data transmission with a simple configuration.

[0010]

EXAMPLES The following will be described with reference to the drawings an actual <br/>施例of the data receiving apparatus according to the present invention.

This embodiment is intended to realize a data receiving apparatus capable of taking in only a data signal into which a frame pattern is inserted from a data transmitting apparatus and efficiently extracting data with a synchronous circuit having a simple structure. It is .

The data receiving apparatus according to this embodiment includes a four-phase clock generating unit that generates a clock having a different phase every quarter of a period T corresponding to one bit of received data, and four types of these clocks. A latch circuit that latches the received data with the clock, monitors the values of these four latch outputs and their changes, and optimizes the latch output that follows the change in the value of the received data. a corresponding determining phase decision section of the clock, the optimum latch output by the decision, and a selecting unit for selecting a clock optimum phase, by matching the frame pattern from the above optimum latch output and the optimum phase clock, It is designed to extract data.

FIG. 1 is a functional diagram of a data receiving apparatus according to an embodiment .
The configuration is shown together with the functional configuration of the opposing data transmission device.
It is a functional block diagram.

In FIG . 1, a data receiving device 20 includes a clock phase synchronization circuit 1, a frame phase synchronization circuit 2,
Clock generator 3, bit buffer 4, frequency divider 5
And, and a high-speed receiver 6.

[0015] Data transmission device 30 includes a frame pattern inserting section 31, and a high-speed driver 33.

In the data transmitting device 30, data is supplied with a frame pattern inserted by a frame pattern insertion unit 31 to a high-speed driver 33. High-speed driver 33
Uses this data as transmission data (for example, 10 Mbps).
) To the high-speed receiver 6 of the data receiving device 20.

The clock generator 3 generates a 20 MHz clock signal and supplies it to the four-phase clock generator 15 and the frequency divider 5. Also, a frame pulse FP is generated and supplied to the bit buffer 4. The frequency divider 5 divides the frequency of the clock signal of 20 Mbps by 供給 す る and supplies it to the bit buffer 4.

[0018] The high-speed receiver 6 supplies the received data to the latch 11 to 14. The four- phase clock generator 15 generates clocks A to D having different phases as shown in FIG. 2 from the supplied clock signal of, for example, 20 Mbps, and supplies the clock A to the latch 14 and the clock B to the latch 13.
, The clock C is supplied to the latch 12, and the clock D is supplied to the latch 11. The clocks A to D are also supplied to the selection unit 18.

The latch 11 is supplied from the high-speed receiver 6.
The received data is latched at the pulse rising timing of the clock D, and a latch signal LD is
And the phase determination unit 16. The latch 12 latches the received data supplied from the high-speed receiver 6 at the pulse rising timing of the clock C and supplies a latch signal LC to the selector 17 and the phase determiner 16. The latch 13 latches the received data supplied from the high-speed receiver 6 at the pulse rising timing of the clock B, and outputs the latch signal LB to the selector 17 and the phase determiner 1.
And 6. The latch 14 latches the received data supplied from the high-speed receiver 6 at the rising edge of the clock A, and supplies the latch signal LA to the selector 17 and the phase determiner 16.

The phase judging section 16 takes in the latch signals LA to LD supplied from the latches 11 to 14, and outputs these four signals.
The change of 0 and 1 of the type of latch signal is monitored, for example ,
First, selection signals S1 and S2 for selecting a latch signal and a clock delayed by two phases from the latch signal of the phase in which the change of “0 → 1” is detected are formed, and the selection units 17 and 1 are selected.
8

For example, in FIG. 2, since a change of "0 → 1" can be first detected in the latch signal LA, the latch signal LC and the clock C delayed by two phases from the latch signal LA are set to the optimum latch signal. And selecting signals S1 and S2 for selecting the received clock phase. In this case, the reason why the latch signal and the clock delayed by two phases are selected is that the latch is performed at a stable timing substantially at the center of the bit section of the received data.
This is, for example, in the waveform of logic 1 of the second bit of the received data in FIG.
In the vicinity of the transition point to 0, the influence of pulse disturbance and the influence of jitter occur, so that a latch signal latched at a stable timing near the center is selected.

The selection signals S1 and S2 are latch signals L
When selecting A and clock A, (S1, S2) =
It is (0, 0). Also, the latch signal LB and the clock B
If Select and (S1, S2) = (1,0 ) der
You . When the latch signal LC and the clock C are selected, (S1, S2) = (0 , 1). When the latch signal LD and the clock D are selected, (S1, S1
2) = (1, 1).

The selector 17 selects and outputs any one of the latch signals LA to LD based on the select signals S1 and S2 supplied from the phase determiner 16, and outputs the selected signal to the bit buffer 4 and the CRC checker 22. Is supplied to the frame pattern detection unit 21. Further, the selection unit 18 selects one of the clocks (CK) having the optimum phase of the clocks A to D based on the selection signals S1 and S2 supplied from the phase determination unit 16 and supplies the clock (CK) to the bit buffer 4.

The CRC check unit 22 performs a CRC (Cyclic Redundancy Check: Cycl) on the supplied latch signal (data of the optimal timing synchronized with the clock of the optimal phase).
icRedundancy Check) check. For example, a predetermined frame check sequence (FC
S) to check the received frame for errors,
The erroneous frame is discarded or the erroneous frame is retransmitted from the transmission side. Then, information such as an error frame number is supplied to the frame pattern detection unit 21. Although this CRC check method is not particularly limited, for example, an existing vertical parity (generating polynomial P (x)
= Ru good to X + X0) and, horizontal parity (generating polynomial P
(X) = Ru good to Xm + X0) and, 2 consecutive transmission collation and, CRC
−16 (Generator polynomial P (x) = X16 + X12 + X2 +
Good Ru) or to 1, CRC-CCITT (generating polynomial P
(X) = X16 + X12 + Ru good to X5 + 1) can also be used a method such as.

The frame pattern detecting section 21 fetches the latch signal at the optimum timing, detects and outputs a predetermined frame pattern FP, and supplies it to the bit buffer 4. At this time, discard control of the error frame is performed based on the information such as the error frame supplied from the CRC check unit 22.

The bit buffer 4, the optimal latch signal supplied from the selecting unit 17, the frame pattern FP
The frame pulse is extracted based on the timing of (1), and a clock generated by its own clock generation unit 3 and data synchronized with the frame pulse FP (R) are output. The bit buffer 4 is, for example, an MSM6903 manufactured by Oki Electric Company.
(256-bit elastic store) or the like, and can be realized with a simple circuit configuration. Ru it is possible to obtain only the data in the manner described above.

FIG. 2 is an operation timing chart (part 1) of the digital synchronous circuit according to this embodiment. In addition,
FIG. 2 shows that the received data and one of clocks A to D are the same.
It shows the case where it was expected. In FIG.
(A) shows received data (0, 1, 0),
(B) shows a clock A output from the four-phase clock generator 15, and (C) shows a clock B (a clock delayed by 1 / phase with respect to the clock A ) from the four-phase clock generator 15. )
(D) shows the clock C output from the four-phase clock generator 15 (a clock delayed by 2/4 phase with respect to the clock A).
Indicates a click), (E) is click delayed 3/4 phase with respect to the clock D (clock A four-phase clock generator 15 outputs
Shows the lock), (F) shows the latch output LA of the latch 14, (G) shows the latch output LB of the latch 13, (H) the latch output of the latch 12 L
C, and (I) shows the latch output LD of the latch 11.
Is shown.

FIG. 3 is an operation timing chart (part 2) of the digital synchronous circuit according to this embodiment. In addition,
FIG. 3 shows that all of the clocks A to D are the same for the received data.
It shows the case when it is not expected. In FIG.
(A) shows received data (0, 1, 0),
(B) shows a clock A output from the four-phase clock generator 15, (C) shows a clock B output from the four-phase clock generator 15, and (D) shows a clock B from the four-phase clock generator 15.
The output clock C is shown, (E) shows the clock D of the output of the four-phase clock generator 15, (F) shows the latch output LA of the latch 14, and (G) shows the latch output of the latch 13. (H) shows the latch output LC of the latch 12, and (I) shows the latch output LB.
1 shows a latch output LD.

In FIG. 3, the change from "0 to 1" is first detected at the timing of the latch signal LA and the clock A, and the latch signal LC delayed by two phases from these signals is output . Near the stable center of the received data waveform
At (time) latched based on clock C
handle. According to the above-described embodiment, the received data in which the frame pattern is inserted is taken in, and the clock phase synchronization and the frame phase synchronization are performed, so that the frame pattern can be collated at the optimal timing and the data can be extracted. Therefore, data can be efficiently extracted only by taking in one type of data as compared with the related art. Therefore, even when it is desired to transmit data from one data transmission device to a plurality of data reception devices, the signal line can Since the number of devices and the number of high-speed drivers and high-speed receivers can be reduced, power consumption can be reduced.

In FIG. 1 of the above embodiment, one pulse (0 and 1) of the received data is latched by four-phase clocks having different phases, but the present invention is not limited to this. For example, it may be realized by a two-phase or three-phase clock, or may be realized by a five-phase or more clock.

Further, in the above embodiment, the pulse width of the clock is not limited to the examples shown in FIGS. For example, two or more n (for example, 4
), And the pulse width of the clock may be small or large. That is,
The lock duty ratio does not matter. In the above-described embodiment, the description has been given of the case where the received data is an NRZ signal (including a clock component incompletely and including a DC component). However, the present invention is not limited to this. For example, a code including a clock component or a code including no DC component can be applied.

In the above embodiment, the phase determination unit 16 monitors the change of the latch outputs LA to LD from “0 → 1”. However, the present invention is not limited to this. For example, “1 → 0”
It can be applied even to monitoring the change of.

In FIG. 2 of the above embodiment,
First, control is performed so as to select the latch signal LC and the clock C which are delayed by two phases from the latch signal LA in which the change of “0 → 1” is detected, but the present invention is not limited to this. For example, control may be performed so as to select an optimal latch signal when the waveform from the center to the latter half of the 1-bit section becomes stable and a clock having an optimal phase corresponding to the optimal latch signal . Further, in FIG. 1 of the above embodiment, the configuration of the data transmitting apparatus and the data receiving apparatus has been described, but the present invention is not limited to this. Data transmission board (PWB) and may be configured with the data receiving board (PWB).

In the above embodiment, the configuration of the frame phase synchronization circuit 2 is not limited to that shown in FIG. For example, CCITT Recommendation G. 706 specification or the like.

Although the latches 11 to 14 are used in FIG. 1 of the above embodiment, the present invention is not limited to this.

In FIG. 1 of the above embodiment,
Clocks having different phases are generated from the clock from one clock generator 3, but the present invention is not limited to this. For example, to generate a desired n-phase clock,
It may be configured to include a plurality of corresponding clock generators.

[0037]

According to the above mentioned present invention as according to the present invention, it is possible to reduce the number of interface lines between the devices compared to traditional, power consumption is reduced, to realize a data receiving apparatus having a simple configuration .

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a data receiving device according to an embodiment of the present invention.

FIG. 2 is an operation timing chart (1) of the data receiving apparatus according to one embodiment of the present invention;

FIG. 3 is an operation timing chart (No. 2) of the data receiving apparatus according to one embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Clock phase synchronous circuit, 2 ... Frame phase synchronous circuit, 11-14 ... Latch, 15 ... 4 phase clock generation part,
16: phase determination unit, 17, 18: selection unit, 20: data receiving device.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H04L 7/00 H04L 7/02 H04L 7/08

Claims (1)

(57) [Claims]
1. A data storage device in which a frame pattern is inserted.
In a data receiving apparatus that receives a data sequence, n / 2 (n is 3 or more) in one bit period of the received data sequence.
High-speed clock with integer pulses) and readout frames
A one-bit period of a received data string from a clock generating means for generating a frame pulse and the high-speed clock.
The phases are different for each period equally divided by n, and the duty ratio is 1:
A write clock for generating (n-1) n write clocks
A lock generating means, and the received data string is divided into n write clocks having different phases.
Latch and outputs n latch data.
Latch means for fetching the n pieces of latch data and changing the same logical value.
Latch data with the fastest timing
Half of the 1-bit period of the received data from the
Phase lags by the period closest to the interval or half of the interval
Latch data and a write clock related to the latch data.
A phase determination means for forming a selection signal instructing the lock takes the n latches data, the selection signal finger
Latch data selecting means for selecting latch data to be displayed
And the above-mentioned n write clocks, and the selection signal
Write clock selection to select the specified write clock
Means, and latch data output from the latch data selecting means.
Frame pattern contained in the
Frame phase synchronizing means for forming a frame pulse, and dividing the high-speed clock to form a read clock
Frequency dividing means and the write clock output from the write clock selecting means.
The write frame from the frame phase synchronization means.
Output from the latch data selection means based on the pulse
Of the latch data excluding the frame pattern
Write the read clock and the read clock.
First-in first-out with readout synchronized with the outgoing frame pulse
And a bit buffer means of a switching method .
Data receiving device.
JP04288192A 1992-02-28 1992-02-28 Data receiving device Expired - Fee Related JP3157029B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04288192A JP3157029B2 (en) 1992-02-28 1992-02-28 Data receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04288192A JP3157029B2 (en) 1992-02-28 1992-02-28 Data receiving device

Publications (2)

Publication Number Publication Date
JPH05244134A JPH05244134A (en) 1993-09-21
JP3157029B2 true JP3157029B2 (en) 2001-04-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3157029B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005328138A (en) * 2004-05-12 2005-11-24 Ricoh Co Ltd Phase adjuster
JP5448795B2 (en) 2009-12-25 2014-03-19 キヤノン株式会社 Information processing apparatus or information processing method
JP5377275B2 (en) * 2009-12-25 2013-12-25 キヤノン株式会社 Information processing apparatus or information processing method

Also Published As

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