JP2012222497A - Receiving circuit and error detection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiving circuit and an error detection method, facilitating timing adjustment in design.SOLUTION: A receiving circuit comprises: a DL circuit section 1 for sampling a reception serial data bit string in which data transits as a rectangular wave, using a plurality of clocks having different phases to generate a reception data bit string by using the sampled reception serial data bits; and a PD circuit section 2 for detecting an error period of the reception data bit string, based on a result obtained by comparing whether or not values of the reception serial data bits sampled by using the clock having a different phase in a predetermined period are identical to those of the sampled reception serial data bits.

Description

  The present invention relates to a receiving circuit that samples received data using clocks having different phases and an error detection method.

  Currently, serial transfer that can easily achieve a high data rate is mainly used in high-speed data transfer between devices or circuits. For high-speed serial transfer, an embedded clock system in which a clock is embedded in data is used. A receiving side device or circuit (hereinafter referred to as a receiving side device or the like) detects an embedded clock from serial data by CDR (Clock Data Recovery). The receiving device or the like can receive data by synchronizing the phase of the received data and the clock for sampling the received data. However, when jitter is added to the serial data or the receiving PLL, synchronization may be lost and erroneous data may be received.

  Patent Document 1 discloses a configuration of a data receiving device intended to detect received data at an early stage. Specifically, the data receiving device has a function of checking whether the sampling clock generated by the CDR circuit is generated at a timing necessary for capturing data in the serial communication receiving operation unit. As a result, it is possible to detect in real time whether an error occurs in the received data.

  The configuration of the data receiving device disclosed in Patent Document 1 will be described with reference to FIG. The CDR circuit 101 is a circuit that generates a sampling clock (SCLK) for correctly sampling the serial data (SD). That is, the CDR circuit 101 has a function of generating a sampling clock having a constant cycle synchronized with serial data in order to correctly receive data in the data receiving unit in serial data communication. In serial data communication, there is a transmission system that transmits only data instead of transmitting data and a capture clock (CLK) from the transmission side. In this system, the data is captured on the reception side. Therefore, the CDR circuit 101 is necessary. The CDR circuit 101 is configured using, for example, a PLL (phase locked loop) circuit. In the PLL circuit, the VCO is controlled so that the phase of the oscillation clock of the VCO (voltage controlled oscillator) coincides with the phase of the serial data, and the PLL derives the oscillation clock of the VCO as a reproduction clock.

  An oversampling clock recovery circuit has also been proposed to support high-speed data transmission. The oversampling type clock recovery circuit outputs the sampling clock (SCLK) error from the CDR circuit 101, whether the sampling clock satisfies the timing for accurately capturing the data, or outputs the correct number of sampling clocks for the data Detect if there is an error.

  Reference numeral 114 denotes a sampling clock error detection circuit, and reference numeral 102 denotes a sample CK error detection circuit that checks whether a clock is output at the correct timing (the setup time and hold time are satisfied) with respect to data. The sample CK error detection circuit 102 receives the serial data (SD) and the sampling clock (SCLK) derived from the CDR circuit 101, and outputs an error signal SCLKERR.

  103 is a data duty (DUTY) adjustment unit, 112 is a data high (HIGH) period error detection circuit, 113 is a data low (LOW) period error detection circuit, and outputs a correct number of sampling clocks for data. It is a block to check. The data DUTY adjustment unit 103 adjusts the duty (DUTY) of the serial data and outputs SDH (a signal with a slightly longer SD HIGH period) and SDL (a signal with a slightly longer SD LOW period), and outputs SDH. The data HIGH period error detection circuit 112 is supplied with SDL to the data LOW period error detection circuit 113.

  The data HIGH period error detection circuit 112 checks a clock error in the data HIGH period, and the data LOW period error detection circuit 113 checks a clock error in the data LOW period. The data HIGH period error detection circuit 112 includes a HIGH counter control circuit 104, a HIGH sample number count circuit 105, a HIGH data length count circuit 106, and a HIGH sample number error detection circuit 107. The data LOW period error detection circuit 113 includes: , A LOW counter control circuit 108, a LOW sample number count circuit 109, a HIGH data count circuit 110, and a LOW sample number error detection circuit 111.

  The HIGH counter control circuit 104 receives the SDH output from the data DUTY adjustment unit 103 and the system clock SYSCLK having a frequency that is the communication rate of serial communication, and outputs DHCNTCK to the HIGH data length count circuit 106. The HIGH data length count circuit 106 is a counter that performs a count operation with the DHCNT clock provided from the HIGH counter control circuit 104, and the count result HDCNT is output to the HIGH sample number error detection circuit 107.

  The HIGH sample number count circuit 105 is a counter that receives the serial data SD and the sampling clock SCLK and counts the number of sampling clocks SCLK generated by the CDR circuit 101. The counted result HSCNT is output to the HIGH sample number error detection circuit 107. The HIGH sample number error detection circuit 107 receives the HSCNT and HDCNT signals that are the outputs of the HIGH sample number count circuit 105 and the HIGH data length count circuit 106, and outputs the HSERR signal if the comparison result is different. Has function.

  The data LOW period error detection circuit 113 is configured in the same manner as the data HIGH period error detection circuit 112, and includes a LOW counter control circuit 108, a LOW sample number count circuit 109, a LOW data length count circuit 110, and a LOW sample number error. The detection circuit 111 is configured. The LOW counter control circuit 108 receives the SDL output from the data DUTY adjustment unit 103 and the system clock SYSCLK having a frequency that is a communication rate of serial communication, and outputs DLCNTCK to the LOW data length count circuit 110. The LOW data length count circuit 110 is a counter that performs a count operation with the DLCNT clock provided from the LOW counter control circuit 108, and the count result LDCNT is output to the LOW sample number error detection circuit 111.

  The LOW sample number count circuit 109 receives the serial data SD and the sampling clock SCLK, and serves as a counter that counts the number of sampling clocks SCLK generated by the CDR circuit 101. The counted result LSCNT is output to the LOW sample number error detection circuit 111. The LOW sample number error detection circuit 111 receives the LSCNT and LDCNT signals output from the LOW sample number count circuit 105 and the LOW data length count circuit 106, and outputs an LSERR signal if the comparison result is different. Has function.

  Further, Patent Document 2 discloses a symbol detection apparatus that enables reliable symbol detection by detecting and correcting a deviation of the Nyquist point indicating a point indicating a true symbol value from the center position of the data buffer. Has been.

  Further, Patent Document 3 discloses a clock data reproduction method in which a normal identification operation is performed even when the duty of input data is greatly deviated from 100%.

JP 2004-242243 A JP 2007-036976 A JP 2008-227786 A

  However, the data receiving device disclosed in Patent Document 1 has a problem that it is difficult to design a timing at the time of designing. Specifically, the data receiving device disclosed in Patent Document 1 detects errors early by providing a detection circuit. However, since a detection circuit is provided separately from the data sampling circuit, if the data sampling circuit and the detection circuit have different timings for sampling data, the data sampling circuit can correctly sample the data. Nevertheless, the detection circuit may detect an error. In addition, the data sampling circuit may sample erroneous data, but the detection circuit may not detect an error. For this reason, timing adjustment is necessary at the time of design so that the data sampling circuit and the detection circuit sample data at the same timing. However, since the data sampling circuit and the detection circuit operate at high speed, it is difficult to adjust the timing at the time of design. Also, Patent Documents 2 and 3 do not disclose a method for solving the above-described problem.

  The receiving circuit according to the first aspect of the present invention samples received data using a plurality of clocks, and whether or not the values of the data bits match within a predetermined period for a plurality of sampled received data bit strings. Are detected and an error in the received data is detected.

  By providing such a receiving circuit, sampling data can be generated for each of a plurality of clocks. Therefore, by comparing the values of the respective sampling data, it is possible to detect the error section of the received data bit string generated using a plurality of sampling data.

  The error detection method according to the second aspect of the present invention samples received data using a plurality of clocks, and whether the values of the data bits match within a predetermined period for a plurality of sampled received data bit strings. The received data error is detected.

  By using such an error detection method, sampling data can be generated for each of a plurality of clocks. Therefore, by comparing the values of the respective sampling data, it is possible to detect the error section of the received data bit string generated using a plurality of sampling data.

  According to the present invention, it is possible to provide a receiving circuit and an error detection method that facilitate timing adjustment at the time of design.

1 is a configuration diagram of a CDR circuit according to a first embodiment; 3 is a timing chart when sampling is performed using the multiphase clock according to the first embodiment; 3 is a timing chart when sampling is performed using the multiphase clock according to the first embodiment; 1 is a configuration diagram of a correction circuit according to a first embodiment; 3 is a timing chart of the inverting operation in the bit inverting circuit unit according to the first embodiment; 1 is a configuration diagram of a bit inverting circuit unit according to a first embodiment; FIG. 6 is a configuration diagram of a correction circuit according to a second embodiment. FIG. 6 is a configuration diagram of a correction circuit according to a third embodiment. 1 is a configuration diagram of a data receiving device according to Patent Document 1. FIG.

(Embodiment 1)
Embodiments of the present invention will be described below with reference to the drawings. A configuration example of the CDR circuit unit 7 according to the first embodiment of the present invention and a connection example between the CDR circuit unit 7, the PLL circuit unit 5, and the reception serial data bit input port 19 will be described with reference to FIG. 1. The CDR circuit unit 7, the PLL circuit unit 5, and the reception serial data bit input port 19 are included in a reception circuit that receives serial data.

  The CDR circuit unit 7 includes a DL (direct latch) circuit unit 1, a PD (phase detector) circuit unit 2, a CDR controller circuit unit 3, and a PI (phase interpolator) circuit unit 4.

  The DL circuit unit 1 samples a received serial data bit string input from the received serial input port 19 using a multiphase clock whose phase is adjusted (hereinafter referred to as a multiphase clock (after phase adjustment)), and performs sampling. Data and a received data bit string are generated. Furthermore, the DL circuit unit 1 generates a sampling clock using a multiphase clock. The received serial data bit string is a bit string in which data transitions as a rectangular wave. That is, the received serial data bit string is a bit string in which data alternately changes like “1010”, and is a bit string that does not have the same continuous data like “1110”.

  The multiphase clock is composed of a plurality of clocks having different phases. For example, the multiphase clock includes a reference clock (CLK0), a CLK90 that is 90 degrees different from CLK0, a CLK180 that is 180 degrees different from CLK0, and a CLK270 that is 270 degrees different from CLK0. Data sampled using CLK0 is CLK0 sampling data, data sampled using CLK90 is CLK90 sampling data, data sampled using CLK180 is CLK180 sampling data, and data sampled using CLK270 Is CLK270.

  The received data bit string is generated by combining some sampling data among the sampling data described above. For example, the reception data bit string may be generated by combining CLK0 sampling data and CLK180 sampling data.

  The sampling clock is composed of a clock used for generating a received data bit string. For example, the sampling clock is composed of CLK0 and CLK180.

  The DL circuit unit 1 outputs the generated received data bit string and sampling clock to the bit inverting circuit unit 6 and outputs sampling data to the PD circuit unit 2.

  The PD circuit unit 2 detects the phase difference of the sampling data output from the DL circuit unit 1 and outputs a phase difference detection signal to the CDR controller circuit unit 3. Further, the error values in the received data bit string are detected by comparing the values of the sample data generated using clocks having different phases. The detected error interval is output to the retiming circuit unit 12 as a CDR error signal. The detection of the retiming circuit unit 12 and the error section will be described later in detail.

  The CDR controller circuit unit 3 outputs a PI control signal to the PI circuit unit 4 in order to adjust the phase of the multiphase clock (original) based on the phase difference detection signal output from the PD circuit unit 2. The PI circuit unit 4 generates a multiphase clock (after phase adjustment) in which the phase of the multiphase clock (original) is adjusted based on the PI control signal from the CDR controller circuit unit 3. The multiphase clock (original) is a multiphase clock output from the PLL circuit unit 5. The PLL circuit unit 5 is configured by a VCO (voltage controlled oscillator) and outputs a plurality of clocks having different phases to the PI circuit unit 4.

  Next, a timing chart in the case of sampling at the rising timing of two sampling clocks per received serial data bit will be described with reference to FIG. FIG. 2 shows an example in which data sampled at the rising timing of CLK0 and CLK180 is used as a received data bit. The CLK0 sampling data samples data A1 and data A3 at the rising timing of CLK0. The CLK180 sampling data samples data A2 and A4 at the rising timing of CLK180. The received data bit string is a combination of CLK0 sampling data and CLK180 sampling data, and includes data A1 to A4.

  Here, the phase difference detection processing in the PD circuit unit 2 and the CDR controller circuit unit 3 will be described. In the example of FIG. 2, the CLK0 sampling data includes data A1 and A3, and the CLK90 sampling data includes data A2 and A4. Thus, the data sampled using CLK0 and CLK90 are different. The PD circuit unit 2 outputs to the CDR controller circuit unit 3 a phase difference detection signal indicating that the CLK0 sampling data and the CLK90 sampling data are different.

  When receiving the phase difference detection signal indicating that the CLK0 sampling data and the CLK90 sampling data are different, the CDR controller circuit unit 3 shifts the phases of the CLK0, 90, 180, and 270 in the direction opposite to the time axis. The PI control signal is output to the PI circuit unit 4. Further, when the CDR controller circuit unit 3 receives the phase difference detection signal indicating that the CLK90 sampling data and the CLK180 sampling data are different, the phase of the CLK0, 90, 180, and 270 is shifted in the time axis direction. The PI control signal is output to the PI circuit unit 4. Thus, CLK0 and CLK180 for sampling the received serial data are in a state of sampling the center of the data, and the received serial data bits can be sampled stably.

  Next, the error detection process will be described using the timing chart of FIG. FIG. 3 shows an example in which data sampled at the rising timing of CLK0 and CLK180 is used as a received data bit, as in FIG. As shown in FIG. 3, CLK0 sampling data samples data A1 and data A3, and CLK180 sampling data samples data A3 and data A4. Therefore, when a reception data bit string is generated using these sampling data, the data A2 is not sampled and an erroneous reception data bit string is generated.

  The value of the received serial data bit sampled at the timing of CLK0 at t40 is different from the value of the received serial data bit sampled at the timing of CLK90 at t41, and CLK90 is received at the timing of t41, and CLK180 is t42. If the value of the received serial data bit sampled at the timing is different from that of the received serial data bit, the PD circuit unit 2 determines that an error has occurred in two consecutive cycle periods of the data A1 and A3 in the received data bit string. Therefore, the PD circuit unit 2 sets the CDR error signal to active (High) and outputs it for two consecutive cycle periods of the data A1 and A3 in the received data bit string. The CDR error signal specifies that one of the two received data bits is incorrect, but does not specify which received data bit is incorrect.

  Timing t40 is the rising timing of CLK0, and timing t42 is the falling timing of CLK0 and the rising timing of CLK180. Timing t41 is between timing t40 and t42, and is the rising timing of CLK90. That is, assuming that one clock is from the rising timing of CLK0 to the next rising timing, t40 and t42 have a period of 0.5 clock.

  Next, a configuration example of the correction circuit according to the first embodiment of the present invention will be described with reference to FIG. The correction circuit 50 is included in a receiving circuit that receives serial data. The correction circuit 50 includes a bit inversion circuit unit 6, a 10b8b conversion circuit unit 8, a CRC circuit unit 9, a 10b8b conversion circuit unit 10, a CRC circuit unit 11, a retiming circuit unit 12, a data buffer 13, An alternative data buffer 14, a CDR error buffer 15, an AND circuit 16, an AND circuit 17, a selector 18, a CRC error output 21, and a data output 22 are provided.

  When the CDR error signal is inactive (Low), the bit inversion circuit unit 6 outputs the received data bit as it is to the 10b8b conversion circuit units 8 and 10 as the first half bit inverted data and the second half bit inverted data. The bit inversion circuit unit 6 outputs the first half bit inversion data to the 10b8b conversion circuit unit 8, and outputs the second half bit inversion data to the 10b8b conversion circuit unit 10. The bit inversion circuit unit 6 receives the CDR error signal from the PD circuit unit 2.

  When the CDR error signal is active (High) and the sampling clock is High, the bit inverting circuit unit 6 outputs data obtained by inverting the corresponding received data bit to the 10b8b conversion circuit unit 8 as the first half bit inverted data. Further, when the CDR error signal is active (High) and the sampling clock is High, the bit inverting circuit unit 6 outputs the corresponding received data bit as it is to the 10b8b conversion circuit unit 10 as the latter half bit inverted data.

  When the CDR error signal is active (High) and the sampling clock is Low, the bit inversion circuit unit 6 outputs the data obtained by inverting the corresponding received data bit to the 10b8b conversion circuit units 8 and 10 as the second half bit inverted data. Further, when the CDR error signal is active (High) and the sampling clock is Low, the bit inverting circuit unit 6 outputs the corresponding received data bit as it is to the 10b8b conversion circuit unit 8 as the first half bit inverted data.

  Here, a timing chart of the inverting operation in the bit inverting circuit unit 6 will be described with reference to FIG. In the period from t20 to t22 and the period from t24 to t25 in which the CDR error signal is set inactive, the bit inverting circuit unit 6 outputs the received data bits as the first half bit inverted data and the second half bit inverted data. To do. In the period from t22 to t23 when the CDR error signal is set to active and the sampling clock is set to High, the bit inverting circuit unit 6 inverts the received data bit and outputs the first half bit inverted data. In the period from t23 to t24 when the CDR error signal is set active and the sampling clock is set low, the bit inverting circuit unit 6 inverts the received data bit and outputs the second half bit inverted data.

  Next, a circuit configuration example of the bit inverting circuit unit 6 will be described with reference to FIG. The bit inverting circuit unit 6 includes XOR circuits 40 and 41 and selectors 42 and 43. The received data bits output from the DL circuit unit 1 are input to the XOR circuits 40 and 41 and the selectors 42 and 43. The CDR error output from the PD circuit unit 2 is input to the XOR circuits 40 and 41. The XOR circuit 40 and the XOR circuit 41 perform an XOR operation based on the received data bit and the value of the CDR error, and output the operation result to the selectors 42 and 43. The selectors 42 and 43 receive the received data bits and the sampling clock from the DL circuit unit 1.

  When the selector 42 receives the sampling clock set to Low, the selector 42 outputs the operation result output from the XOR circuit 40 to the second half bit inverted data output port, and receives the sampling clock set to High. The received data bit is output to the latter half bit inverted data output port. When the selector 43 receives the sampling clock set to Low, the selector 43 outputs the received data bit received to the first half bit inverted data output port. When the selector 43 receives the sampling clock set to High, it is output from the XOR circuit 41. The calculated result is output to the first half bit inverted data output port.

  In this way, the bit inverting circuit unit 6 outputs data obtained by inverting one of the two bits of the received data bits corresponding to the CDR error signal High as the first half bit inverted data and the second half bit inverted data.

  Returning to FIG. 4, the 10b8b conversion circuit units 8 and 10 are circuits that restore the original 8-bit data from the 10-bit received data bits in which the embedded clock is embedded. The circuit configurations of the 10b8b conversion circuit units 8 and 10 are the same. The 10b8b conversion circuit units 8 and 10 receive the first half bit inverted data or the second half bit inverted data corrected by the bit inverting circuit unit 6, respectively.

  The data buffer 13 is a buffer for storing the 8-bit data restored by the 10b8b conversion circuit unit 10. The data buffer 13 has a sufficient depth, that is, a sufficient capacity so that data can be output from the data output 22 after checking the CRC every 512 to 2048 bytes.

  The retiming circuit unit 12 generates a CDR error flag signal that becomes active at a timing at which 8-bit data after 10b8b conversion having a CDR error is stored in the data buffer 13 and the alternative data buffer 14.

  The alternative data buffer 14 stores 8-bit data restored by the 10b8b conversion circuit 8 when the CDR error flag signal is active, and is stored in the alternative data buffer 14 when the CDR error flag signal is inactive. A buffer that maintains a value. The alternative data buffer 14 can store one 8-bit data.

  The CRC circuit units 9 and 11 perform a CRC check on the output data output from the 10b8b conversion circuit units 8 and 10 every 512 to 2048 bytes. The CRC circuit units 9 and 11 generate a CRC error signal when a CRC error is detected. The circuit configuration of the CRC circuit units 9 and 11 is the same. The CRC error signal is a signal set to a high level.

  The CDR error buffer 15 is a buffer for storing a CDR error flag. The CDR error buffer 15 records an error flag for the data buffer line corresponding to the CDR error.

  The AND circuit 16 outputs a signal set to High when an error flag is output from the CDR error buffer 15 and a CRC error signal is output from the CRC circuit unit 11. In other cases, the AND circuit 16 outputs a signal set to Low.

  If the result of one of the CRC circuit units 11 and 9 is not an error (Low), the AND circuit 17 notifies the CRC error output port 21 that there is no error (Low). The AND circuit 17 outputs an error (High) from the CRC error output port 21 if both the results are errors (High).

  When the signal output from the AND circuit 16 is set to the High level, the selector 18 selects the data in the alternative data buffer 14 and the data in the alternative data buffer 14 is output from the data output port 22. The selector 18 selects the data in the data buffer 13 when the signal output from the AND circuit 16 is set to the Low level, and the data in the data buffer 13 is output from the data output port 22.

  The data in the data buffer 13 is sequentially output from the data output 22 to the upper layer after checking the CRC transmitted every 512 to 2048 bytes. At this time, if the output of the CRC circuit unit 11 indicates a CRC error and the output of the CDR error buffer 15 indicates an error flag, the data correction of the second half bit inverted data is incorrect, that is, the DL circuit unit. 1 is missed in the first half cycle, and the first half bit inverted data is more correct. Therefore, at this time, the selector 18 selects the data in the alternative data buffer 14 instead of the data in the data buffer 13 and outputs it from the data output 22.

  If the output of the CRC circuit unit 11 does not indicate a CRC error and the CDR error buffer 15 indicates an error flag, the data correction of the second half bit inverted data is correct, that is, the DL circuit unit 1 takes The loss was in the latter half cycle, and the latter half bit inverted data is more correct. Therefore, at this time, the selector 18 selects the data in the data buffer 13 and outputs it from the data output 22.

  When the CDR error buffer 15 does not indicate an error flag, there is no data that the DL circuit unit 1 misses. Therefore, the selector 18 selects the data in the data buffer 13 and outputs it from the data output 22.

  The correction circuit 50 outputs a CRC error signal to the upper layer together with the data. If there is no error in any one of the two CRC error signals, no error (Low) is output, and if both of the two CRC error signals are in error, an error is output (High).

  As described above, by using the receiving circuit according to the first embodiment of the present invention, the fact that the DL circuit unit 1 has failed in sampling of the received serial data bits is usually performed without providing a dedicated error detecting circuit. Can be detected based on the sampling data used for phase adjustment. Therefore, there is no need to worry about the mismatch between the dedicated error detection circuit and the sampling data result, so that the timing design in the receiving circuit can be easily performed.

  Further, by using the correction circuit 50, the data can be corrected without requesting the transmission side to retransmit the data in which the error is detected. Thus, even if a reception error occurs, data can be corrected without reducing the transfer rate.

(Embodiment 2)
Subsequently, a configuration example of the correction circuit 60 according to the second exemplary embodiment of the present invention will be described with reference to FIG. In the correction circuit of FIG. 4, the CDR error buffer 15 corresponding to the data buffer 13 is provided bit by bit. However, in the correction circuit 60 of FIG. 7, the buffer configuration for storing the buffer number of the data in which the CDR error has occurred. To. Since the other configuration is the same as that of the correction circuit of FIG. 4, detailed description thereof is omitted. The CDR error buffer 20 records the line number of the data buffer 13 in which the output data of the 10b8b conversion circuit unit 10 is stored when the CDR error flag becomes active (High). When the data when the CDR error flag becomes active is output from the data buffer 13 to the selector 18, the output of the CDR error buffer 20 becomes active and is output to the AND circuit 16.

  As described above, by using the correction circuit 60 according to the second embodiment of the present invention, the size of the CDR error buffer is reduced as compared with the correction circuit in FIG. Therefore, an increase in circuit scale can be suppressed.

(Embodiment 3)
Next, a configuration example of the correction circuit 70 according to the third embodiment of the present invention will be described with reference to FIG. The correction circuit 70 includes a bit inversion circuit unit 6, 10b8b conversion circuit units 8 and 10, CRC circuit units 9, 11, 24 and 26, a retiming circuit unit 12, a data buffer 13, a CDR error buffer 15, 31 and 32, AND circuit 17, CRC error output 21, data output 22, alternative data buffer selection circuit 23, selector 27, alternative data buffers 28 and 29, 33 and 34. . The same components as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The correction circuit 70 has two CRC circuit units and one alternative data buffer added as compared to the correction circuit of FIG. The correction circuit of FIG. 4 can correct a 1-bit error that occurs in one CRC check period, and the correction circuit 70 corrects a 2-bit error that occurs in one CRC check period. It is possible.

  The CRC circuit unit 9 always checks the CRC of the first half bit inverted data. The CRC circuit unit 11 always checks the CRC of the latter half bit inverted data. On the other hand, the CRC circuit unit 24 and the CRC circuit unit 26 check the CRC of data obtained by combining the first half bit inverted data and the second half bit inverted data.

  The selector 33 outputs the first half bit inverted data output from the 10b8b conversion circuit unit 8 to the CRC circuit unit 24, and the first half bit inverted data output from the 10b8b conversion circuit unit 8 even when the first CDR error is detected. Is output to the CRC circuit 24. The selector 33 outputs the latter half bit inverted data output from the 10b8b conversion circuit unit 10 to the CRC circuit unit 24 after the first CDR error is detected. The selector 34 outputs the latter half bit inverted data output from the 10b8b conversion circuit unit 10 to the CRC circuit unit 26, and the latter half bit inverted data output from the 10b8b conversion circuit unit 10 even when the first CDR error is detected. Is output to the CRC circuit unit 26. After the first CDR error is detected, the selector 34 outputs the first half bit inverted data output from the 10b8b conversion circuit unit 8 to the CRC circuit unit 26. The selectors 33 and 34 switch data to be output based on the CDR error flag output from the retiming circuit unit 12.

  The alternative data buffer 28 stores 8-bit data including data obtained by inverting the first half of the received data bit corresponding to the first CDR error, and the alternative data buffer 29 receives the received data corresponding to the second CDR error. 8-bit data including data obtained by inverting the first half of the bit is stored.

  The substitute data buffers 28 and 29 store the 8-bit data restored by the 10b8b conversion circuit 8 when the CDR error flag signal is active, and store the substitute data buffers 28 and 29 when the CDR error flag signal is inactive. It is a buffer that holds the stored value, and can store one 8-bit data. The CDR error flag signal output to the alternative data buffers 28 and 29 is controlled using AND circuits 31 and 32 and the alternative data buffer selection circuit 23. When a CDR error occurs for the first time, an active state signal is output from the alternative data buffer selection circuit 23 to the AND circuit 31, and an active state CDR error flag signal is output from the AND circuit 31. When a CDR error occurs for the second time, an active state signal is output from the alternative data buffer selection circuit 23 to the AND circuit 32, and an active state CDR error flag signal is output from the AND circuit 32.

  Next, the data selection processing operation of the selector 27 will be described. If the data can be corrected correctly by inverting the latter half bit in both the first and second times for the CDR error that has occurred twice, the output of the CRC circuit unit 11 becomes inactive. If the data can be corrected correctly by inverting the first half bit in both the first and second times for a CDR error that has occurred twice, the output of the CRC circuit unit 9 becomes inactive.

  If the data can be corrected correctly by inverting the first half bit of the CDR error generated twice and inverting the second half bit in the second time, the output of the CRC circuit unit 24 becomes inactive. Of the CDR errors that occur twice, if the data can be corrected correctly by inverting the latter half bit data at the first time and inverting the first half bit at the second time, the output of the CRC circuit unit 26 becomes inactive. .

  When the output of the CDR error buffer 15 is inactive (Low), the selector 27 selects the data in the data buffer 13 and outputs the selected data from the data output 22.

  When the output of the CDR error buffer 15 is active (High), the selector 27 selects data as follows according to the output results of the CRC circuit units 9, 11, 24 and 26. When the data output from the CRC circuit unit 11 is inactive, the selector 27 selects the data in the data buffer 13. When the data output from the CRC circuit unit 9 is inactive, the selector 27 selects the data in the alternative data buffer 28 when the data set to be active for the first time is output from the CDR error buffer 15. When the data set to be active for the second time is output, the data in the alternative data buffer 29 is selected.

  When the data output from the CRC circuit unit 24 is inactive, the selector 27 selects the data in the alternative data buffer 28 when the data set to be active for the first time is output from the CDR error buffer 15. When the data set to active for the second time is output, the data in the data buffer 13 is selected. When the data output from the CRC circuit unit 26 is inactive, the selector 27 selects the data in the data buffer 13 when the first active data is output from the CDR error buffer 15. When the data set to be active for the second time is output, the data in the alternative data buffer 29 is selected.

  As described above, when the correction circuit 70 according to the third embodiment of the present invention is used, correct data can be corrected even when a 2-bit error occurs in one CRC check period. Even when an error of 3 bits or more occurs in one CRC check period, it can be corrected by adding a CRC circuit unit and an alternative data buffer.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 DL circuit part 2 PD circuit part 3 CDR controller circuit part 4 PI circuit part 5 PLL circuit part 6 Bit inversion circuit part 7 CDR circuit part 8 10b8b conversion circuit part 9 CRC circuit part 10 10b8b conversion circuit part 11 CRC circuit part 12 Timing circuit unit 13 Data buffer 14 Alternative data buffer 15 CDR error buffer 16 AND circuit 17 AND circuit 18 Selector 19 Reception serial data bit input port 21 CRC error output 22 Data output 23 Alternative data buffer selection circuit 24 CRC circuit unit 26 CRC circuit unit 27 selector 28 alternative data buffer 29 alternative data buffer 31 AND circuit 32 AND circuit 33 selector 34 selector 40 XOR circuit 41 XOR circuit 42 selector 43 selector 50 correction circuit

Claims (10)

Using a plurality of clocks having different phases, sampling a received serial data bit sequence in which data transitions as a rectangular wave, and generating a received data bit sequence using the sampled received serial data bits; and
The received data bit string based on a result of comparing whether or not the values of the received serial data bits sampled using clocks having different phases within a predetermined period of the sampled received serial data bits match. And an error detection unit for detecting the error section. The plurality of clocks are:
A first clock, a second clock having a first phase difference from the first clock, and a third clock having a phase difference greater than the first phase difference from the first clock. Including
The received data bit string generator is
The receiving circuit according to claim 1, wherein a reception data bit string is generated by using the reception serial data bits sampled by using the first clock and the third clock. The error detection unit
A first received serial data bit sampled using the first clock and a second received serial data bit sampled using the second clock are different from each other within the predetermined period, When the two received serial data bits are different from the third received serial data bit sampled using the third clock, the received data bit string includes the first and third received serial data bits. The receiving circuit according to claim 2, wherein the section is detected as an error section. In the predetermined period, when the first received serial data bit and the second received serial data bit are different and the second received serial data bit and the third received serial data bit match, Adjusting the phase so that the first to third clocks are shifted in the direction opposite to the time axis;
When the first received serial data bit and the second received serial data bit match and the second received serial data bit and the third received serial data bit are different within the predetermined period, The receiving circuit according to claim 3, further comprising a phase adjusting unit that adjusts a phase so that the first to third clocks are shifted in a time direction. When an error section is detected in the error detection unit, the first received data bit string including the first half bit inverted data obtained by inverting the first received serial data bit and the third received serial data are inverted. A bit inverting unit for generating a second received data bit string including the second half bit inverted data;
A normality determination unit for determining normality of each of the first and second received bit data sequences, and the first or second in accordance with a determination result in the normality determination unit and an error detection result in the error detection unit The receiving circuit according to claim 3, further comprising a selector that selects a received data bit string. The normality determination unit
A first normality determination unit for determining normality of the first received bit data string;
A second normality determination unit for determining normality of the second received bit data string;
In the error detection unit, the first received serial data bit is inverted in the error interval detected for the first time, and the third received serial data bit is inverted in the error interval detected for the second time. A third normality determination unit that determines the normality of the third received data bit string including data;
Data obtained by inverting the third received serial data bit in the error interval detected for the first time and inverting the first serial data bit in the error interval detected for the second time in the error detection unit. A fourth normality determination unit for determining normality of a fourth received data bit string including
The selector is
6. The device according to claim 5, wherein one of the first to fourth received data bit strings is selected according to a determination result in the first to fourth normality determination units and an error detection result in the error detection unit. Receiver circuit. A second half bit storage buffer for storing the second half bit inverted data;
A first first half bit storage buffer for storing the first half bit inverted data when an error is detected for the first time;
A second first half bit storage buffer for storing the first half bit inverted data when an error is detected at the second time,
The selector is
When the first received bit data string is determined to be normal, the second to fourth received bit data strings are determined to be abnormal, or when an error is detected for the first time, the first first half When the first half bit inverted data stored in the bit storage buffer is selected and an error is detected at the second time, the first half bit inverted data stored in the second first half bit storage buffer is selected,
When the second received bit data string is determined to be normal and the first, third, and fourth received bit data strings are determined to be abnormal, an error is detected at the first time and the second time. In both cases, select the latter half bit inverted data stored in the latter half bit storage buffer,
If the third received bit data sequence is determined to be normal, the first, second, and fourth received bit data sequences are determined to be abnormal, or if an error is detected for the first time, the first Select the first half bit inverted data stored in the first half bit storage buffer, and if the second time the error is detected, select the second half bit inverted data stored in the second half bit storage buffer,
When it is determined that the fourth received bit data sequence is normal, the first to third received bit data sequences are determined to be abnormal, and when an error is detected for the first time, the latter half bit storage buffer is stored. 7. The reception according to claim 6, wherein when the second half bit inverted data stored is selected and an error is detected at the second time, the first half bit inverted data stored in the second first half bit storage buffer is selected. circuit.   The receiving circuit according to claim 7, further comprising an error buffer that manages an identifier indicating a storage location of the latter half bit storage buffer that stores data including the received data bits in a section in which the error is detected.   9. The receiving circuit according to claim 5, wherein the normality determining unit determines normality of each of the first and second received bit data sequences using a CRC. Using a plurality of clocks with different phases, sampling a received serial data bit string in which data transitions as a rectangular wave, and generating a received data bit string using the sampled received serial data bits,
The received data bit string based on a result of comparing whether or not the values of the received serial data bits sampled using clocks having different phases within a predetermined period of the sampled received serial data bits match. Error detection method to detect the error interval.

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