JP6738028B2 - Receiver circuit and semiconductor integrated circuit - Google Patents

Description

The present invention relates to a receiver circuit and a semiconductor integrated circuit.

A data transfer method is known that has a plurality of first-in first-out memories that store each of a plurality of divided data transferred in parallel (see Patent Document 1). The timing instruction means monitors the data storage state of each of the plurality of first-in first-out memories, and outputs a timing signal for instructing the reading of data when data is stored in all of them. The plurality of holding means are provided corresponding to each of the plurality of first-in first-out memories, and in synchronization with the timing signal output from the timing instructing means, the divided data stored in the plurality of first-in first-out memories are taken and held. ..

Further, there is known a skew correction circuit having a detection unit that detects an edge of one transmission signal from edges that should be at the same timing among a plurality of transmission signals transmitted through a parallel transmission path (see Patent Document 2). The correction signal generation means generates a correction signal according to the cycle of the edge detected by the detection means. The correction means synchronizes with the correction signal generated by the correction signal generation means and outputs the edges of the plurality of transmission signals in agreement with each other.

Further, there is known a semiconductor device having an input circuit that takes in a plurality of external data in synchronization with a plurality of external clock signals (see Patent Document 3). The pulse signal generation circuit generates a pulse signal. The drive circuit aligns the plurality of data captured by the input circuit with the same timing according to the timing of the pulse signal and supplies the data to the internal circuit.

There is also known an asynchronous transmission device that receives at least one notification signal transmitted according to a transmission clock according to a reception clock (see Patent Document 4). The trigger signal transmitter outputs a trigger signal based on the symbol period of the notification signal. The notification signal transmission unit outputs a notification signal with a timing shifted by a predetermined time with respect to the timing of the trigger signal output by the trigger signal transmission unit. The trigger signal synchronization unit receives the trigger signal output from the trigger signal transmission unit, synchronizes the trigger signal, and outputs a sampling timing signal indicating the sampling timing of the notification signal output from the notification signal transmission unit. Output. The notification signal holding unit holds the notification signal received from the notification signal transmission unit according to the sampling timing signal.

JP, 10-247175, A JP-A-6-54016 JP, 2003-85130, A Japanese Patent No. 4841927

For example, in the case of correcting a signal of an analog circuit by a digital circuit, there is a demand to simultaneously receive a plurality of data output by the analog circuit by a circuit located at a distant position in the semiconductor chip. In order to receive a plurality of data at the same timing, there is a method of transmitting a plurality of data and clock signals to a plurality of flip-flop circuits.

However, as the transmission distance increases, the skew between the data and the clock signal may increase. Therefore, in order to satisfy the constraint of the setup/hold time for the flip-flop circuit to normally receive the data, the design of the transmission circuit is performed. Timing constraints on all data and clock signals need to be tightened. Also, when the skew is large, it is difficult to design at the required operating frequency.

An object of the present invention is to provide a receiving circuit and a semiconductor integrated circuit that can match the data transition timings of a plurality of received data.

The receiving circuit includes a plurality of first holding circuits for respectively latching a plurality of received data whose data transition timing of at least one received data is different from that of other received data based on the same clock signal; After a lapse of a fixed time from the time point when the plurality of first holding circuits have latched the plurality of received data, the first received data that is the output signal of the plurality of first holding circuits and the plurality of first holding data are output. A comparison circuit for respectively comparing the second reception data, which is an input signal of the holding circuit, and an output signal of the comparison circuit indicates that the first reception data and the second reception data match, have a plurality of second holding circuit that latches the first reception data, respectively, the plurality of first holding circuit, the latches in synchronism with the first edge of the clock signal, said comparator circuit Compare in synchronization with a second edge of the clock signal, which is a subsequent edge of the first edge .

Even when the data transition timings of the plurality of received data received by the plurality of first holding circuits are different, the data transition timings of the plurality of received data latched by the plurality of second holding circuits can be matched. ..

FIG. 1 is a diagram showing a configuration example of a semiconductor integrated circuit according to the first embodiment. FIG. 2 is a circuit diagram showing a configuration example of the receiving circuit. FIG. 3 is a timing chart showing an operation example of the receiving circuit of FIG. FIG. 4 is a circuit diagram showing a configuration example of the receiving circuit according to the second embodiment. FIG. 5 is a timing chart showing an operation example of the receiving circuit of FIG.

(First embodiment)
FIG. 1 is a diagram showing a configuration example of a semiconductor integrated circuit 100 according to the first embodiment. The semiconductor integrated circuit 100 is a receiving device, and has a front end circuit 101, a logic circuit 102, and a clock generation circuit 103. The front end circuit 101 has a differential amplifier 104, a sampling circuit 105, a demultiplexer 106, and a receiving circuit 107. The logic circuit 102 has an offset cancel logic circuit 108 and a clock data recovery logic circuit 109. The offset cancel logic circuit 108 has a transmission circuit 110. The clock data recovery logic circuit 109 has a transmission circuit 111. The clock generation circuit 103 has a phase interpolation circuit 112 and a reception circuit 113.

The differential signals RXIN and RXINX are serial signals and are input to the front end circuit 101. The differential amplifier 104 amplifies the differential signals RXIN and RXINX. The sampling circuit 105 samples the signal amplified by the differential amplifier 104 in synchronization with the clock signal output by the clock generation circuit 103. The demultiplexer 106 converts the signal sampled by the sampling circuit 105 from a serial signal into a parallel signal, and outputs an output signal RXOUT.

The offset cancel logic circuit 108 generates offset cancel data based on the output signal RXOUT in order to cancel the offset of the differential amplifier 104. The transmission circuit 110 transmits, for example, 6-bit offset cancellation data and a clock signal to the reception circuit 107. The reception circuit 107 receives, for example, 6-bit offset cancellation data and a clock signal, and outputs, for example, 6-bit offset cancellation data to the differential amplifier 104. The differential amplifier 104 outputs, to the sampling circuit 105, an amplified signal whose offset has been canceled based on the offset cancel data.

The clock data recovery logic circuit 109 generates phase control data based on the output signal RXOUT in order to control the phase of the clock signal output by the clock generation circuit 103. The transmission circuit 111 transmits, for example, 7-bit phase control data and a clock signal to the reception circuit 113. The reception circuit 113 receives, for example, 7-bit phase control data and a clock signal, and outputs, for example, 7-bit phase control data to the phase interpolation circuit 112. The phase interpolation circuit 112 interpolates the phase of, for example, a 4-phase reference clock signal based on the phase control data, and outputs a clock signal of a desired phase to the sampling circuit 105. It is difficult for the sampling circuit 105 to sample correct data when sampling at the data transition timing of the input signal, and correct data can be sampled when sampling at the timing when the data of the input signal is stable. Since the clock data recovery logic circuit 109 controls the phase of the clock signal, the sampling circuit 105 can perform sampling at a timing when the data of the input signal is stable and recover correct data.

As described above, the transmission circuit 110 transmits a plurality of bits of offset cancel data to the reception circuit 107. The reception circuit 107 receives a plurality of bits of offset cancellation data from the transmission circuit 110. Further, the transmission circuit 111 transmits a plurality of bits of phase control data to the reception circuit 113. The receiving circuit 113 receives a plurality of bits of phase control data from the transmitting circuit 111.

When the positions of the transmission circuit 110 and the reception circuit 107 are distant from each other, and when the positions of the transmission circuit 111 and the reception circuit 113 are distant from each other, the transmission distance of the offset cancellation data and the phase control data becomes long, and the multi-bit data is transmitted. The skew of the clock signal becomes large. In that case, the receiving circuits 107 and 113 may not be able to correctly receive the offset cancel data and the phase control data, respectively. If the receiving circuits 107 and 113 cannot correctly receive all the bits of data at the same time, the differential amplifier 104 and the phase interpolating circuit 112 cannot perform proper operation. Therefore, the receiving circuits 107 and 113 need to correctly receive all bits of data at the same time.

2 is a circuit diagram showing a configuration example of each of the receiving circuits 107 and 113 in FIG. 1, and FIG. 3 is a timing chart showing an operation example of the receiving circuit in FIG. The receiving circuits 107 and 113 have the same configuration as each other. The reception circuits 107 and 113 respectively include flip-flop circuits 200 to 202, 207, 209 to 211, exclusive OR circuits 203 to 205, a NOR circuit 206, and an AND circuit 208.

The reception circuit 107 receives, for example, 3-bit reception data (offset cancellation data) DIN<0> to DIN<2> and the clock signal CLK from the transmission circuit 110, and, for example, 3-bit reception data (offset cancellation data) DOUT<. 0> to DOUT<2> are output to the differential amplifier 104.

The reception circuit 113 receives, for example, 3-bit reception data (phase control data) DIN<0> to DIN<2> and the clock signal CLK from the transmission circuit 111, and, for example, 3-bit reception data (phase control data) DOUT<. 0> to DOUT<2> are output to the phase interpolation circuit 112.

The three first flip-flop circuits 200 to 202 are first holding circuits, receive 3-bit reception data DIN<0> to DIN<2>, respectively, and receive the same rising edge of the same clock signal CLK (first The 3-bit received data DIN<0> to DIN<2> are respectively latched in synchronization with the edge 1).

The first flip-flop circuit 200 latches the reception data DIN<0>, holds the latched reception data, and outputs the latched reception data DF<0> in synchronization with the rising edge of the clock signal CLK. The first flip-flop circuit 201 latches the reception data DIN<1>, holds the latched reception data, and outputs the latched reception data DF<1> in synchronization with the rising edge of the clock signal CLK. The first flip-flop circuit 202 latches the reception data DIN<2>, holds the latched reception data, and outputs the latched reception data DF<2> in synchronization with the rising edge of the clock signal CLK.

The exclusive OR circuit 203 outputs a low level when the reception data DIN<0> and DF<0> are the same, and when the reception data DIN<0> and DF<0> are different from each other. Output high level. The exclusive OR circuit 204 outputs a low level when the reception data DIN<1> and DF<1> are the same as each other, and when the reception data DIN<1> and DF<1> are different from each other. Output high level. The exclusive OR circuit 205 outputs a low level when the reception data DIN<2> and DF<2> are the same, and when the reception data DIN<2> and DF<2> are different from each other. Output high level.

The NOR circuit 206 outputs a NOR signal XDIF of the output signals of the exclusive OR circuits 203 to 205. The flip-flop circuit 207 latches the NOR signal XDIF in synchronization with the falling edge (second edge) of the clock signal CLK, holds the latched signal, and outputs the latched signal WE. The AND circuit 208 outputs the AND signal of the signal WE and the clock signal CLK as the clock signal WCLK.

The three second flip-flop circuits 209 to 211 are second holding circuits and are latched by the three first flip-flop circuits 200 to 202 in synchronization with the rising edge of the same clock signal WCLK. The received data DF<0> to DF<2> are respectively latched.

The second flip-flop circuit 209 latches the reception data DF<0>, holds the latched reception data, and outputs the latched reception data DOUT<0> in synchronization with the rising edge of the clock signal WCLK. The second flip-flop circuit 210 latches the reception data DF<1>, holds the latched reception data, and outputs the latched reception data DOUT<1> in synchronization with the rising edge of the clock signal WCLK. The second flip-flop circuit 211 latches the received data DF<2>, holds the latched received data, and outputs the latched received data DOUT<2> in synchronization with the rising edge of the clock signal WCLK.

The transmission circuits 110 and 111 each simultaneously transmit 3-bit data DIN<0> to DIN<2>. However, due to differences in the lengths of the transmission lines of the 3-bit data DIN<0> to DIN<2>, the reception circuits 107 and 113 respectively receive the 3-bit data DIN<0> as shown in FIG. ~DIN<2> are received at different timings. For example, the reception data DIN<2> is received with the shortest delay time, the reception data DIN<1> is received with the second shortest delay time, and the reception data DIN<0> is received with the longest delay time. That is, during the times t4 to t6, the reception data DIN<0> to DIN<2> have different data transition timings.

At time t1, the first flip-flop circuits 200 to 202 latch the reception data DIN<0> to DIN<2> of "1", respectively, in synchronization with the rising edge of the clock signal CLK, and set them to "1". The received data DF<0> to DF<2> are output respectively. Since the exclusive OR circuits 203 to 205 have the same reception data DIN<0> to DIN<2> of “1” and reception data DF<0> to DF<2> of “1”, respectively. Output level. Then, the NOR circuit 206 outputs the high-level NOR signal XDIF.

Next, at time t2, the flip-flop circuit 207 latches the high-level NOR signal XDIF in synchronization with the falling edge of the clock signal CLK, and outputs the high-level signal WE. Here, the falling edge of the clock signal CLK that defines the latch timing of the flip-flop circuit 207 is the trailing edge of the rising edge of the clock signal CLK that defines the latch timing of the first flip-flop circuits 200 to 202. , The edge after half a cycle. The AND circuit 208 outputs the clock signal WCLK having the same cycle as the clock signal CLK.

Next, at time t3, the first flip-flop circuits 200 to 202 latch the reception data DIN<0> to DIN<2> of “1” respectively in synchronization with the rising edge of the clock signal CLK, and “ The reception data DF<0> to DF<2> of "1" are respectively output. Since the exclusive OR circuits 203 to 205 have the same reception data DIN<0> to DIN<2> of “1” and reception data DF<0> to DF<2> of “1”, respectively. Output level. Then, the NOR circuit 206 outputs the high-level NOR signal XDIF.

The second flip-flop circuits 209 to 211 respectively latch the reception data DF<0> to DF<2> of “1” in synchronization with the rising edge of the clock signal WCLK, and receive the reception data DOUT< of “1”. 0> to DOUT<2> are output.

Next, at time t4, the flip-flop circuit 207 latches the high-level NOR signal XDIF in synchronization with the falling edge of the clock signal CLK, and outputs the high-level signal WE. The AND circuit 208 outputs the same clock signal WCLK as the clock signal CLK.

Next, at time t5, the second flip-flop circuits 209 to 211 latch the reception data DF<0> to DF<2> of “1”, respectively, in synchronization with the rising edge of the clock signal WCLK. The reception data DOUT<0> to DOUT<2> of "1" are output.

The first flip-flop circuits 201 and 202 respectively latch the reception data DIN<1> and DIN<2> of “0” in synchronization with the rising edge of the clock signal CLK, and receive the reception data DF< of “0”. 1> and DF<2> are output. On the other hand, the first flip-flop circuit 200 latches the reception data DIN<0> of “1” and outputs the reception data DF<0> of “1” in synchronization with the rising edge of the clock signal CLK. To do.

Next, at time t6, the exclusive OR circuits 204 and 205 receive the received data DIN<1> and DIN<2> of “0” and the received data DF<1> and DF<2> of “0”, respectively. Output the low level. On the other hand, the exclusive OR circuit 203 outputs the high level because the reception data DIN<0> of “0” and the reception data DF<0> of “1” are different. Then, the NOR circuit 206 outputs the low-level NOR signal XDIF. The flip-flop circuit 207 latches the low-level NOR signal XDIF in synchronization with the falling edge of the clock signal CLK and outputs the low-level signal WE. The AND circuit 208 outputs a low level clock signal WCLK.

Next, at time t7, the first flip-flop circuits 200 to 202 respectively latch the reception data DIN<0> to DIN<2> of “0” in synchronization with the rising edge of the clock signal CLK, and The reception data DF<0> to DF<2> of "0" are respectively output. Since the exclusive OR circuits 203 to 205 have the same reception data DIN<0> to DIN<2> of “0” and reception data DF<0> to DF<2> of “0”, respectively. Output level. Then, the NOR circuit 206 outputs the high-level NOR signal XDIF. Since the clock signal WCLK maintains the low level, the second flip-flop circuits 209 to 211 do not latch.

Next, at time t8, the flip-flop circuit 207 latches the high-level NOR signal XDIF in synchronization with the falling edge of the clock signal CLK, and outputs the high-level signal WE. The AND circuit 208 outputs the same clock signal WCLK as the clock signal CLK.

Next, at time t9, the second flip-flop circuits 209 to 211 latch the reception data DF<0> to DF<2> of “0”, respectively, in synchronization with the rising edge of the clock signal WCLK. The reception data DOUT<0> to DOUT<2> of "0" are output.

The above times t1 to t3 indicate the operation during the period in which the reception data DIN<0> to <2> are stable over the half cycle or more of the clock signal CLK. Times t5 to t6 indicate the operation during the period during which the reception data DIN<0> to DIN<2> are in transition. Times t7 to t9 indicate an operation during a period in which the reception data DIN<0> to <2> are stable over a half cycle or more of the clock signal CLK, similarly to the times t1 to t3. At time t7 during which the reception data DIN<0> to DIN<2> are transitioning, the clock signal WCLK is at the low level, so that the reception data DOUT<0> to DOUT< output by the second flip-flop circuits 209 to 211 are output. 2> does not change.

Although an example of 3-bit received data DIN<0> to DIN<2> has been described above, the received data may be 2 bits or 4 bits or more.

As described above, the plurality of first flip-flop circuits 200 to 202 receive the plurality of reception data DIN<0> to DIN<2>, respectively, and the plurality of reception data DIN<0 based on the same clock signal CLK. > To DIN<2> are respectively latched, and a plurality of received data DF<0> to DF<2> are output, respectively.

The exclusive OR circuits 203 to 205, the NOR circuit 206, and the flip-flop circuit 207 are comparison circuits, and after a predetermined time has elapsed from the latch time (for example, time t5) of the plurality of first flip-flop circuits 200 to 202. At (for example, time t6), the reception data DF<0> to DF<2> latched by the plurality of first flip-flop circuits 200 to 202 and the plurality of first flip-flop circuits 200 to 202 are input, respectively. The received data DIN<0> to DIN<2> are compared with each other. The above-mentioned fixed time is the time from the rise to the fall of the clock signal CLK. The flip-flop circuit 207 outputs a high level when the received data of all bits match, and outputs a low level when the received data of all bits do not match.

The plurality of second flip-flop circuits 209 to 211 include reception data DF<0> to DF<2> in which the output signals of the comparison circuit are latched by the plurality of first flip-flop circuits 200 to 202, respectively. The reception data latched by the plurality of first flip-flop circuits 200 to 202 when the reception data DIN<0> to DIN<2> input to the first flip-flop circuits 200 to 202 respectively match each other. DF<0> to DF<2> are respectively latched and a plurality of received data DOUT<0> to DOUT<2> are output, respectively.

According to the present embodiment, the reception circuits 107 and 113 receive 3-bit reception data having the same data transition timing even when they receive 3-bit reception data DIN<0> to DIN<2> having different data transition timings. Data DOUT<0> to DOUT<2> can be output.

The reception circuits 107 and 113 can determine whether the reception data DIN<0> to DIN<2> are stable. After the first flip-flop circuits 200 to 202 have latched, the reception data DIN<0> to DIN<2> and the reception data DF<0> to DF<2 are passed after a predetermined time (half cycle of the clock signal CLK) has elapsed. , The received data DIN<0> to DIN<2> are in transition, and the received data DF<0> to DF<2> can be determined to be invalid data. On the contrary, if the received data DIN<0> to DIN<2> and the received data DF<0> to DF<2> respectively match, the received data DIN<0> to DIN<2> are stable data. Assuming that the second flip-flop circuits 209 to 211 latch the reception data DF<0> to DF<2>, respectively, the correct reception data DOUT<0> to DOUT<2> can be obtained.

If there is no receiving circuit, the transmitting circuits 110 and 111 are subjected to the timing constraint considering the skew due to transmission and the setup/hold time of the flip-flop circuit for the reception data DIN<0> to DIN<2> of all bits and the clock signal CLK. It is necessary to design the transmission timing of, and if the timing constraint cannot be satisfied, performance degradation such as lowering operating frequency and redesign man-hours are required.

Since the receiving circuits 107 and 113 of the present embodiment prevent the latching of the illegal received data during the data transition, the requirements for designing the transmitting circuits 110 and 111 are relaxed. In the present embodiment, the skew between the reception data DIN<0> to DIN<2> need only be suppressed within a half cycle of the clock signal CLK, and the skew between the reception data DIN<0> to DIN<2> and the clock signal CLK is required. No timing constraint occurs.

Further, in the present embodiment, the clock signals CLK of the receiving circuits 107 and 113 do not have to be synchronized with the clock signals of the transmitting circuits 110 and 111. That is, the receiving circuits 107 and 113 may internally generate the clock signal CLK without receiving the clock signal CLK from the transmitting circuits 110 and 111.

(Second embodiment)
FIG. 4 is a circuit diagram showing a configuration example of each of the receiving circuits 107 and 113 according to the second embodiment, and FIG. 5 is a timing chart showing an operation example of the receiving circuit of FIG. The receiving circuit (FIG. 4) of this embodiment is obtained by removing the AND circuit 208 from the receiving circuit (FIG. 2) of the first embodiment. Hereinafter, the difference between this embodiment and the first embodiment will be described.

The second flip-flop circuits 209 to 211 each have an enable terminal EN in addition to an input terminal, a clock terminal, and an output terminal. The signal WE output from the flip-flop circuit 207 is input to the enable terminals EN of the second flip-flop circuits 209 to 211. The clock signal CLK is input to the clock terminals of the second flip-flop circuits 209 to 211. The reception data DF<0> to DF<2> are input to the input terminals of the second flip-flop circuits 209 to 211, respectively. The output terminals of the second flip-flop circuits 209 to 211 output received data DOUT<0> to DOUT<2>, respectively.

When the signal WE is at a high level, the second flip-flop circuits 209 to 211 latch the reception data DF<0> to DF<2> respectively in synchronization with the rising edge of the clock signal CLK and receive the data. The data data DOUT<0> to DOUT<2> are output, respectively. Further, the second flip-flop circuits 209 to 211 do not latch the reception data DF<0> to DF<2> when the signal WE is at the low level.

At time t3, since the signal WE is at the high level, the second flip-flop circuits 209 to 211 synchronize with the rising edge of the clock signal CLK and receive data “1” DF<0> to DF<2>. Respectively, and outputs the reception data DOUT<0> to DOUT<2> of "1".

At time t5, the second flip-flop circuits 209 to 211 have the signal WE at the high level, so that the reception data DF<0> to DF<2> of "1" are synchronized with the rising edge of the clock signal WCLK. Respectively, and outputs the reception data DOUT<0> to DOUT<2> of "1".

At time t7, the second flip-flop circuits 209 to 211 do not latch because the signal WE is at low level.

At time t9, since the signal WE of the second flip-flop circuits 209 to 211 is at the high level, the reception data DF<0> to DF<2> of “0” are synchronized with the rising edge of the clock signal CLK. Respectively, and outputs the reception data DOUT<0> to DOUT<2> of "0", respectively.

The reception circuits 107 and 113 of the present embodiment can output the same reception data DOUT<0> to DOUT<2> to the reception circuits 107 and 113 of the first embodiment, and obtain the same effect. You can

According to the first and second embodiments, even when the data transition timings of the plurality of reception data DIN<0> to DIN<2> received by the plurality of first flip-flop circuits 200 to 202 are different, The data transition timings of the plurality of reception data DOUT<0> to DOUT<2> latched by the plurality of second flip-flop circuits 209 to 211 can be matched.

It should be noted that each of the above-described embodiments is merely an example of an embodiment for carrying out the present invention, and the technical scope of the present invention should not be limitedly interpreted by these. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

200-202 1st flip-flop circuits 203-205 Exclusive-OR circuit 206 NOR gate circuit 207 Flip-flop circuit 208 AND circuit 209-211 2nd flip-flop circuit

Claims (9)

A plurality of first holding circuits that respectively latch a plurality of received data whose data transition timing of at least one received data is different from that of other received data based on the same clock signal;
After a lapse of a certain time from the time point when the latching of the plurality of received data in the plurality of first holding circuits is completed, the first received data which is an output signal of the plurality of first holding circuits and the plurality of first A comparison circuit for respectively comparing the second reception data which is the input signal of the holding circuit of
A plurality of second holding circuits for respectively latching the first received data when the output signal of the comparison circuit indicates that the first received data and the second received data match. ,
The plurality of first holding circuits latch in synchronization with a first edge of the clock signal,
The reception circuit is characterized in that the comparison circuit compares in synchronization with a second edge of the clock signal, which is an edge subsequent to the first edge. A plurality of first holding circuits that respectively latch a plurality of received data whose data transition timing of at least one received data is different from that of other received data based on the same clock signal;
After a lapse of a certain time from the time point when the latching of the plurality of received data in the plurality of first holding circuits is completed, the first received data which is an output signal of the plurality of first holding circuits and the plurality of first A comparison circuit for respectively comparing the second reception data which is the input signal of the holding circuit of
A plurality of second holding circuits for respectively latching the first received data when the output signal of the comparison circuit indicates that the first received data and the second received data match. ,
The plurality of second holding circuits latch in synchronization with the same clock signal. The first edge is one of a rising edge and a falling edge of the same clock signal,
Said second edge, the receiving circuit according to claim 1, wherein the is the other edge of the rising and falling edges of the same clock signal. A plurality of first holding circuits that respectively latch a plurality of received data whose data transition timing of at least one received data is different from that of other received data based on the same clock signal;
After a lapse of a certain time from the time point when the latching of the plurality of received data in the plurality of first holding circuits is completed, the first received data which is an output signal of the plurality of first holding circuits and the plurality of first A comparison circuit for respectively comparing the second reception data which is the input signal of the holding circuit of
A plurality of second holding circuits for respectively latching the first received data when the output signal of the comparison circuit indicates that the first received data and the second received data match.
And a logical product circuit for outputting a logical product signal of the output signal and the clock signal of the comparator circuit,
The receiving circuit, wherein the plurality of second holding circuits latch in synchronization with an output signal of the AND circuit. A plurality of first holding circuits that respectively latch a plurality of received data whose data transition timing of at least one received data is different from that of other received data based on the same clock signal;
After a lapse of a certain time from the time point when the latching of the plurality of received data in the plurality of first holding circuits is completed, the first received data which is an output signal of the plurality of first holding circuits and the plurality of first A comparison circuit for respectively comparing the second reception data which is the input signal of the holding circuit of
A plurality of second holding circuits for respectively latching the first received data when the output signal of the comparison circuit indicates that the first received data and the second received data match. ,
Each of the plurality of second holding circuits has an enable terminal and a clock terminal,
An output signal of the comparison circuit is input to enable terminals of the plurality of second holding circuits,
The receiving circuit, wherein the clock signal is input to clock terminals of the plurality of second holding circuits. The first reception data is reception data after being latched by the plurality of first holding circuits,
The second received data receiving circuit according to any one of claims 1 to 5, characterized in that the received data before being latched by the plurality of first holding circuit. A receiving circuit,
An internal circuit that operates based on the data received by the receiving circuit;
Have
The receiving circuit is
A plurality of first holding circuits that respectively latch a plurality of received data whose data transition timing of at least one received data is different from that of other received data based on the same clock signal;
After a lapse of a certain time from the time point when the latching of the plurality of received data in the plurality of first holding circuits is completed, the first received data which is an output signal of the plurality of first holding circuits and the plurality of first A comparison circuit for respectively comparing the second reception data which is the input signal of the holding circuit of
A plurality of second holding circuits for respectively latching the first received data when the output signal of the comparison circuit indicates that the first received data and the second received data match. ,
The plurality of first holding circuits latch in synchronization with a first edge of the clock signal,
The semiconductor integrated circuit, wherein the comparison circuit performs comparison in synchronization with a second edge of the clock signal, which is an edge subsequent to the first edge. Furthermore, it has a transmission circuit for transmitting a plurality of data,
8. The semiconductor integrated circuit according to claim 7 , wherein the receiving circuit receives the plurality of data from the transmitting circuit. The first reception data is reception data after being latched by the plurality of first holding circuits,
9. The semiconductor integrated circuit according to claim 7, wherein the second reception data is reception data before being latched by the plurality of first holding circuits.

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