CN109254941B - FPGA-based serial signal clock synchronization method, serial-to-parallel conversion method and device - Google Patents
FPGA-based serial signal clock synchronization method, serial-to-parallel conversion method and device Download PDFInfo
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- CN109254941B CN109254941B CN201710568619.6A CN201710568619A CN109254941B CN 109254941 B CN109254941 B CN 109254941B CN 201710568619 A CN201710568619 A CN 201710568619A CN 109254941 B CN109254941 B CN 109254941B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
Abstract
The embodiment of the application discloses a serial signal clock synchronization method based on an FPGA, which comprises the following steps: under a high-frequency clock, oversampling a first serial signal input from the outside to obtain a first sampling signal; writing a first sampling signal when the count value of the cycle counter is an intermediate value into the FIFO memory by taking the high-frequency clock as a write clock; reading out the signal written into the FIFO memory from the FIFO memory by taking the local clock as a read clock to obtain a second serial signal synchronized to the local clock domain; wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter is the same as a multiple of the high frequency clock. According to the clock synchronization method in the scheme, edge jitter introduced by the serial signal in the transmission process when the external equipment and the FPGA are communicated can be effectively eliminated, risks caused by data registering at the edge are avoided, and then correct parallel signals are obtained after shift registering.
Description
Technical Field
The application relates to the field of communication based on an FPGA (field programmable gate array), in particular to a serial signal clock synchronization method based on the FPGA. In addition, the application also relates to a method for converting serial signals into parallel signals based on the FPGA, a serial signal clock synchronization device based on the FPGA and a serial-to-parallel conversion device.
Background
The acquisition card can communicate with an external device such as a camera and receive data such as pictures sent by the external device such as the camera. An FPGA (Field Programmable Gate Array) can be configured to implement the function of the acquisition card. The communication process of the FPGA and the camera comprises the steps that the FPGA sends configuration information to the camera, and the camera returns various state information to the FPGA. In the communication process, the configuration information and the state information are transmitted in the form of serial signals. After receiving the serial signal, the FPGA needs to synchronize it to the local clock domain accurately, and then convert it into parallel signal through shift register.
In the prior art, Serial communication is common, and a Serial signal is transmitted along with a channel associated clock, for example, a Serial Peripheral Interface (SPI). The channel associated clock and the serial signal are homologous, and the serial signal can be synchronized to a local clock domain only by using the channel associated clock as a write clock and writing data into an FIFO memory through an FIFO (First Input First Output, First in First out queue) at a receiving end, and then reading the data by using the local clock.
However, when external devices such as a camera communicate with the FPGA, there is no transmission with the channel clock, so a local clock having the same frequency as the clock at the serial signal transmitting end is usually generated on the FPGA, and the local clock is used to receive the serial signal transmitted from the outside. The serial signal may be subjected to various disturbances during transmission, which may cause jitter, such as early transitions, at the edges of the signal transitions. The local clock generated on the FPGA is not homologous to the clock at the serial signal transmitting end, so that data errors may be caused in the process of shift register of the serial signal.
Disclosure of Invention
The application provides a serial signal clock synchronization method and device based on an FPGA (field programmable gate array), which are used for solving the problem that when the FPGA receives a serial signal from external equipment, the FPGA easily gets wrong data due to the fact that the edge of signal jump shakes.
In a first aspect, the present application provides a serial signal clock synchronization method based on an FPGA, including:
under a high-frequency clock, oversampling a first serial signal input from the outside to obtain a first sampling signal;
writing a first sampling signal when the count value of the cycle counter is an intermediate value into the FIFO memory by taking the high-frequency clock as a write clock;
reading out the signal written into the FIFO memory from the FIFO memory by taking the local clock as a read clock to obtain a second serial signal synchronized to the local clock domain;
wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter is the same as a multiple of the high frequency clock.
With reference to the first aspect, in a first possible implementation manner of the first aspect, after the step of obtaining the first sampling signal, the method further includes:
and resetting the cycle counter if the first sampling signal jumps.
With reference to the first aspect, in a second possible implementation manner of the first aspect, before the step of resetting the cycle counter if the first sampling signal makes a transition, the method further includes:
performing edge detection on the first sampling signal under the high-frequency clock to obtain an edge detection signal;
and judging whether the first sampling signal jumps or not according to the edge detection signal.
With reference to the first aspect, in a third possible implementation manner of the first aspect, the step of writing the first sampling signal when the count value of the cycle counter is an intermediate value into the FIFO memory by using the high-frequency clock as a write clock includes:
if the count value of the cycle counter is an intermediate value, registering the first sampling signal under the high-frequency clock to obtain a third serial signal;
and writing the third serial signal into a FIFO memory by taking the high-frequency clock as a write clock.
With reference to the first aspect, in a fourth possible implementation manner of the first aspect, the oversampling, in a high-frequency clock, a first serial signal input from the outside to obtain a first sampling signal includes:
and under a high-frequency clock, delaying the first serial signal for two high-frequency clock periods for registering to obtain a first sampling signal.
In a second aspect, the present application provides a serial-to-parallel method based on an FPGA, including the following steps:
under a high-frequency clock, oversampling a first serial signal input from the outside to obtain a first sampling signal;
writing a first sampling signal when the count value of the cycle counter is an intermediate value into the FIFO memory by taking the high-frequency clock as a write clock;
reading out the signal written into the FIFO memory from the FIFO memory by taking the local clock as a read clock to obtain a second serial signal synchronized to the local clock domain;
under the local clock, the second serial signal is shifted and registered to obtain a parallel signal;
wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter is the same as a multiple of the high frequency clock.
With reference to the second aspect, in a first possible implementation manner of the second aspect, the step of obtaining a parallel signal by shift registering the second serial signal under the local clock includes:
detecting a positioning signal sequence in the second serial signal;
if the positioning signal sequence is detected, taking the next bit of the positioning signal sequence as a start bit;
and under a local clock, shifting and registering the second serial signal taking the start bit as a starting point to obtain a parallel signal.
In a third aspect, the present application further provides a serial signal clock synchronization apparatus based on an FPGA, including:
the over-sampling unit is used for over-sampling a first serial signal transmitted from the outside under a high-frequency clock to obtain a first sampling signal;
the clock synchronization unit is used for taking the high-frequency clock as a write clock and writing a first sampling signal when the count value of the cycle counter is an intermediate value into the FIFO memory; the FIFO memory is used for reading out the signals written into the FIFO memory by taking the local clock as the read clock, and obtaining second serial signals synchronized to the local clock domain;
wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter is the same as a multiple of the high frequency clock.
In a fourth aspect, the present application further provides a serial-parallel conversion apparatus based on an FPGA, including:
the over-sampling unit is used for over-sampling a first serial signal transmitted from the outside under a high-frequency clock to obtain a first sampling signal;
the clock synchronization unit is used for taking the high-frequency clock as a write clock and writing a first sampling signal when the count value of the cycle counter is an intermediate value into the FIFO memory; reading out the signal written into the FIFO memory from the FIFO memory by taking the local clock as a read clock to obtain a second serial signal synchronized to the local clock domain;
the shift register unit is used for shift registering the second serial signal under the local clock to obtain a parallel signal;
wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter is the same as a multiple of the high frequency clock.
According to the method in the embodiment, firstly, oversampling is carried out on a first serial signal under a high-frequency clock to obtain a first sampling signal, then, when the counting value of a cycle counter takes an intermediate value, clock domain crossing FIFO is carried out on the first sampling signal under the high-frequency clock, so that the first serial signal is correctly synchronized to a local clock domain with the same frequency, edge jitter introduced in the transmission process of the serial signal when communication is carried out between external equipment and an FPGA can be effectively eliminated, risks caused by data registering at the edge are avoided, and then correct parallel signals are obtained through shift registering. Further, the counter is calibrated every time an edge transition occurs in the first sampling signal, so that error accumulation caused by edge jitter can be avoided, and the first serial signal can be correctly synchronized to the local clock domain.
Drawings
In order to more clearly explain the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained according to the drawings without any creative effort.
Fig. 1 is a schematic flowchart of a first embodiment of the serial signal clock synchronization method based on FPGA according to the present application;
fig. 2 is a schematic flowchart of a step S200 in the first embodiment of the serial signal clock synchronization method based on FPGA according to the present application;
FIG. 3 is a schematic flowchart of a second embodiment of the FPGA-based serial signal clock synchronization method according to the present application;
fig. 4 is a schematic flowchart of a third embodiment of the serial signal clock synchronization method based on FPGA according to the present application;
fig. 5 is a schematic flowchart of step S500 in a third embodiment of the serial signal clock synchronization method based on FPGA according to the present application;
fig. 6 is a schematic diagram illustrating 6 times oversampling of first serial data according to a fourth embodiment of the FPGA-based serial signal clock synchronization method of the present application;
FIG. 7 is a schematic diagram illustrating a partial signal loss caused by an early transition of a first serial signal in a fourth embodiment of the FPGA-based serial signal clock synchronization method according to the present application;
fig. 8 is a schematic diagram of a fourth embodiment of the serial signal clock synchronization method based on FPGA for correctly synchronizing the first serial signal to the local clock domain according to the present application;
FIG. 9 is a schematic structural diagram of one embodiment of the serial signal clock synchronizing device based on FPGA according to the present application;
FIG. 10 is a schematic structural diagram of another embodiment of the serial signal clock synchronizing device based on FPGA according to the present application;
fig. 11 is a schematic structural diagram of one embodiment of the FPGA-based serial-parallel apparatus according to the present application.
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a schematic flowchart of a serial signal clock synchronization method based on an FPGA according to a first embodiment of the present application, where the method may include the following steps:
s100, under a high-frequency clock, oversampling a first serial signal transmitted from the outside to obtain a first sampling signal;
s200, writing a first sampling signal when the count value of the cycle counter is an intermediate value into an FIFO memory by taking the high-frequency clock as a write clock;
s300, reading the signal written into the FIFO memory from the FIFO memory by taking the local clock as a read clock to obtain a second serial signal synchronized to the local clock domain;
wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter is the same as a multiple of the high frequency clock.
In the field of communications, the sampling frequency is higher than twice the highest frequency of the signal, and such sampling is referred to as oversampling. In the step of S100, the multiple of oversampling may be 3 times or more.
In step S100, the first serial signal is oversampled under the high frequency clock to obtain a first sampling signal, that is, the first serial signal is repeatedly sampled T times, and each bit of the first sampling signal includes T identical corresponding bits of the first serial signal. Specifically, the step of S100 may include: and under a high-frequency clock, delaying the first serial signal for two high-frequency clock periods for registering to obtain a first sampling signal.
The first serial signal is input from the exterior of the FPGA chip and comes from an asynchronous clock domain, so that two high-frequency clock domains are delayed for registering, namely two beats of register are usually called, the first beat synchronizes the first serial signal, the synchronized output can bring conflict of setup/hold time, and a metastable state is generated, so that one beat of register is performed again, and the influence brought by the metastable state is reduced.
In step S200, the count value of the loop counter is an intermediate value, and the intermediate value is any value except for the end values at both ends in the loop cycle. For example, if the cycle period T of the cycle counter is 6 and the cycle counter counts from 0 to 5, the end values at both ends are 0 and 5, respectively, and the middle value may be any one of 1,2,3, and 4. Preferably, when T is even, the T/2 th or (T/2+1) th count value in one cycle period is taken as the middle value, and when T is odd, the (T +1)/2 th count value in one cycle period is taken as the middle value. For example, if the cycle period T of the cycle counter is 6, and the cycle count is from 0 to 5, the intermediate value is preferably 2 or 3; the cycle period T of the cycle counter is 7, and the cycle count is from 0 to 6, and the intermediate value is preferably 3.
Fifo (First In First out) is an abbreviation of First In First out memory, which is a memory device that implements data First In First out.
In general, the step of writing the first sampling signal when the count value of the cycle counter is the intermediate value into the FIFO memory with the high frequency clock as the write clock in step S200 may include the steps of:
s210, if the count value of the cycle counter is an intermediate value, registering the first sampling signal under the high-frequency clock to obtain a third serial signal;
and S220, writing the third serial signal into a FIFO memory by taking the high-frequency clock as a write clock.
In step S210, under the high-frequency clock, when the count value is an intermediate value, the first sampling signal may be sampled once and registered, and each sampling lasts for one high-frequency clock cycle, so as to obtain a third serial signal. Then, in step S220, the third serial signal is written into the FIFO memory with the high frequency clock as the write clock. In this process, a write enable signal corresponding to the third serial signal is also generated, and the write enable signal lasts for only one clock cycle of the high frequency clock, so that the third serial signal is written into the FIFO memory.
Finally, in step S300, when the FIFO memory is not empty, the signal written into the FIFO memory is read out from the FIFO memory with the local clock as the read clock, thereby obtaining the second serial signal synchronized to the local clock domain.
According to the method in the embodiment, the first serial signal is firstly subjected to oversampling under a high-frequency clock to obtain the first sampling signal, then when the counting value of the cycle counter takes an intermediate value, the first sampling signal is registered under the high-frequency clock to obtain the third serial signal, and then the third serial signal is subjected to clock domain crossing FIFO, so that the external first serial signal is correctly synchronized to a local clock domain with the same frequency, the problem of edge jitter introduced in the transmission process of the serial signal can be effectively solved, and errors of finally obtained parallel data are avoided.
Referring to fig. 3, fig. 3 is a schematic flowchart of a serial signal clock synchronization method based on FPGA according to a second embodiment of the present application, where the method may include the following steps:
s100, under a high-frequency clock, oversampling a first serial signal transmitted from the outside to obtain a first sampling signal;
s400, if the first sampling signal jumps, resetting the cycle counter;
s200, writing a first sampling signal when the count value of the cycle counter is an intermediate value into an FIFO memory by taking the high-frequency clock as a write clock;
s300, reading the signal written into the FIFO memory from the FIFO memory by taking the local clock as a read clock to obtain a second serial signal synchronized to the local clock domain;
wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter is the same as a multiple of the high frequency clock.
The steps of S100, S200, and S300 may refer to the first embodiment.
If edge jitter such as early transition occurs continuously to accumulate errors, even if the clock synchronization method of the first embodiment is adopted, a part of bits may still be lost, so that the second serial signal synchronized to the local clock domain is in error. Therefore, in the step S400, by continuously performing reset calibration on the cycle counter, it is avoided that the cycle counter and the first serial signal are not synchronized due to the jitter of the edge of the first sampling signal, so that the influence of the edge advancing or delaying in one local clock period cannot be accumulated in the next local clock period, thereby avoiding error accumulation.
Specifically, the step of S400 may further include, before:
s401, performing edge detection on the first sampling signal under the high-frequency clock to obtain an edge detection signal;
s402, judging whether the first sampling signal jumps or not according to the edge detection signal.
In step S401, edge detection is to detect an input signal or detect a transition of an internal logic signal of the FPGA, that is, detection of a rising edge or a falling edge.
In the step S402, if the first sampling signal jumps, the loop counter is reset, and the count value thereof is reset to the initial value; if no jump occurs, the loop counter continues to count normally.
Referring to fig. 4, in a third embodiment, a method for converting serial signals to parallel signals based on an FPGA is provided, which includes:
s100, under a high-frequency clock, oversampling a first serial signal transmitted from the outside to obtain a first sampling signal;
s200, writing a first sampling signal when the count value of the cycle counter is an intermediate value into an FIFO memory by taking the high-frequency clock as a write clock;
s300, reading the signal written into the FIFO memory from the FIFO memory by taking the local clock as a read clock to obtain a second serial signal synchronized to the local clock domain;
s500, under the local clock, the second serial signal is shifted and registered to obtain a parallel signal;
wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter is the same as a multiple of the high frequency clock.
The steps S100 to S300 can refer to the first embodiment.
Referring to fig. 5, the step S500 may specifically include:
s510, detecting a positioning signal sequence in the second serial signal;
s520, if the positioning signal sequence is detected, taking the next bit of the positioning signal sequence as a start bit;
s530, under a local clock, the second serial signal with the start bit as the starting point is subjected to shift register to obtain a parallel signal.
The positioning signal sequence in step S510 is a preset signal sequence, which is well established between the external device such as a camera and the FPGA. Comparing the second serial signal with the appointed positioning signal sequence bit by bit, once the second serial signal is completely aligned with the appointed positioning signal sequence, namely the positioning signal sequence in the second serial signal is detected, taking the next bit of the positioning signal sequence in the second serial signal as an initial bit, and shifting and registering the second serial signal taking the initial bit as a starting point under a local clock, thereby obtaining the parallel signal. The serial-to-parallel method in this embodiment can be applied to receiving serial data of a non-standard protocol without using a general protocol for transmission.
Referring to fig. 6 to 8, in the fourth embodiment, the bit rate of the received first serial signal rx _ si is 20MHz, and it needs to be converted into a parallel signal with 10bit width.
The high frequency clock clk2 and the local clock clk1 may be generated by a phase locked loop on the FPGA, clk1 being 20MHz, and the 6 times multiplied high frequency clock clk2 being 120MHz, wherein the local clock is the same frequency as the clock of the transmitter of the first serial signal. A cycle counter cnt is generated at a high frequency clock clk2 with a cycle period of 6, counting from 0 to 5 cycles.
Referring to fig. 6, first, the first serial signal rx _ si is delayed by one high frequency clock cycle under the high frequency clock clk2 for registering, and rx _ si _ d1 is obtained; and then the rx _ si _ d1 is delayed by one high frequency clock cycle for register to obtain a first sampling signal rx _ si _ d 2. This completes the oversampling of the first serial signal, each bit being sampled 6 times.
At the same time as oversampling, the cycle counter starts cycle counting from 0 at the rising edge of the first sampling signal rx _ si _ d 2.
rx _ si in ideal transmission conditions each bit lasts for 6 clock cycles of the high frequency clock clk2, and the cycle counter cnt is also cycle counted at 6 cycles. Thus the start and end of each bit of rx _ si _ d2 contains 6 states of cnt ═ 012345.
Next, when the cycle counter cnt is 3, that is, the middle of each bit of rx _ si _ d2, rx _ si _ d2 when cnt is 3 is registered under clk2, and a third serial signal rx _ so is obtained.
Third, the third serial signal rx _ so is written into the FIFO memory with the high frequency clock as the write clock. In this process, a wr _ en corresponding to the third serial signal rx _ so is simultaneously generated as a write enable signal for the fifo memory, the wr _ en lasts for only one clk2 clock cycle,
finally, when the FIFO memory is not empty, the signal in the FIFO memory is read out with clk1 as the read clock, resulting in a second serial signal synchronized to the local clock domain.
By adopting the method, even if edge jitter occurs in the transmission process, for example, the edge jumps ahead, the signal written into the FIFO memory is rx _ si _ d2 when cnt is 3, and the edge jumps ahead has no influence on the signal written into the FIFO memory, so that the risk of data loss caused by registering at the signal edge is avoided, and data errors when serial signals are shifted, registered and converted into parallel signals are avoided.
In this embodiment, if rx _ si is subjected to edge jitter during transmission, for example, if an edge jumps ahead, then the cnt corresponding to the current bit in the first sampled signal rx _ si _ d2 is [ 01234 ], and the cnt corresponding to the next bit is [ 501234 ]. In this case of the early edge transition, if the early edge transition occurs only 1 or 2 times, there is no influence on the second serial signal synchronized to the local clock domain, but if the early edge transition occurs 3 times in total, as shown in fig. 7, then cnt of the current bit is [ 45012 ], cnt of the next bit is [ 345012 ], and since rx _ si _ d2 is registered only when cnt is 3, the current bit is dropped, and the final data is corrupted.
Referring to fig. 8, by detecting whether rx _ si _ d2 makes a transition, if a transition occurs, the cycle counter cnt is reset, so that the effect of the edge advance or the edge delay cannot be accumulated, even if an edge advance occurs, the cnt of the current bit is [ 01234 ], and then the cnt is reset to 0 due to the transition of rx _ si _ d2, and the cnt of the next bit is [ 012345 ], even if the transition occurs multiple times, the cnt counts from 0 each time, so that a bit is not lost, and further, data errors are avoided.
Referring to fig. 8, edge detection is performed on the first sampling signal under a high-frequency clock clk2, specifically, when an edge detection signal change is obtained through rx _ si _ d1 and rx _ si _ d2, and both rx _ si _ d1 and rx _ si _ d2 are high or low, the corresponding edge detection signal change is low; when one of rx _ si _ d1 and rx _ si _ d2 is high, and the other is low, the corresponding edge detection signal change is high. When the edge detection signal change changes from high to low, the first sampling signal rx _ si _ d2 transitions.
After the second serial signal synchronized to the local clock domain is obtained, the method can further comprise the step of shifting and registering the second serial signal and converting the second serial signal into a 10-bit parallel signal. Specifically, a 10-bit positioning signal sequence may be defined between the camera and the FPGA, for example, in this embodiment, the positioning signal sequence may be 10' b10_1000_ 0011. Comparing the second serial signal with the appointed positioning signal sequence bit by bit, once the second serial signal is completely aligned with the appointed positioning signal sequence, namely the positioning signal sequence in the second serial signal is detected, taking the next bit of the positioning signal sequence in the second serial signal as an initial bit, and under a local clock, shifting and registering the second serial signal taking the initial bit as a starting point, wherein one group of every ten bits are formed, so that the parallel signal is obtained.
Referring to fig. 9, in a fifth embodiment, an FPGA-based serial signal clock synchronization apparatus is provided, including:
an oversampling unit 10, configured to perform oversampling on a first serial signal input from the outside under a high-frequency clock, to obtain a first sampling signal;
a clock synchronization unit 20, configured to write a first sampling signal when the count value of the cyclic counter is an intermediate value into the FIFO memory by using the high-frequency clock as a write clock; the FIFO memory is used for reading out the signals written into the FIFO memory by taking the local clock as the read clock, and obtaining second serial signals synchronized to the local clock domain;
wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter is the same as a multiple of the high frequency clock.
Phase locked loops 60 outside the serial signal clock synchronization device are connected to the oversampling unit 10 and the clock synchronization unit 20, respectively, and the phase locked loops 60 are used to generate the local clock and the high frequency clock.
The cycle counter 70 outside the serial signal clock synchronization device is connected to the clock synchronization unit 70, and the cycle counter 70 is generated at a high frequency clock, and the cycle period T thereof is the same as the multiple of the high frequency clock with respect to the local clock.
According to the serial signal clock synchronization device, firstly, the oversampling unit 10 is used for oversampling a first serial signal to obtain a first sampling signal, then the clock synchronization unit 20 is used for obtaining the counting value of the cycle counter, and the clock domain crossing FIFO is used for the first sampling signal when the counting value is the middle value, so that the first serial signal is correctly synchronized to a local clock domain with the same frequency, the problem of edge jitter introduced by the serial signal in the transmission process is effectively eliminated, and errors of finally obtained parallel data are avoided.
Optionally, referring to fig. 10, the serial signal clock synchronization apparatus further includes a counter calibration unit 30 connected to the oversampling unit 10, and the counter calibration unit 30 is further connected to a cycle counter 70 outside the serial signal clock synchronization apparatus, and is configured to reset the cycle counter 70 when the first sampling signal transitions.
If edge jitter such as early transition occurs continuously to accumulate errors, even if the clock synchronization apparatus is used, a part of bits may still be lost, so that the second serial signal synchronized to the local clock domain is erroneous. Therefore, by adding the counter calibration unit 30, the repetition counter 70 is continuously reset and calibrated, so that the phenomenon that the repetition counter 70 is out of synchronization with the first serial signal due to the edge jitter of the first sampling signal is avoided, the influence of the edge advancing or delaying in one local clock period cannot be accumulated to the next local clock period, and the error accumulation is avoided.
Optionally, the serial signal clock synchronization apparatus further includes:
the edge detection unit is used for carrying out edge detection on the first sampling signal to obtain an edge detection signal;
and the jump judging unit is respectively connected with the edge detecting unit and the counter calibrating unit and is used for judging whether the first sampling signal jumps or not according to the edge detecting signal.
The edge detection unit is connected to the oversampling unit 10 and the transition determination unit, respectively, and the transition determination unit is connected to the counter calibration unit 30.
Optionally, the clock synchronization unit comprises:
the first register unit is used for registering the first sampling signal under the high-frequency clock to obtain a third serial signal when the count value is an intermediate value;
and the writing unit is used for writing the third serial signal into the FIFO memory by taking the high-frequency clock as a writing clock.
Optionally, the oversampling unit 10 includes: and the second register unit delays the first serial signal for two high-frequency clock periods to register under a high-frequency clock to obtain a first sampling signal.
Referring to fig. 11, in a sixth embodiment, an FPGA-based serial-parallel apparatus is provided, including:
an oversampling unit 10, configured to perform oversampling on a first serial signal input from the outside under a high-frequency clock, to obtain a first sampling signal;
a clock synchronization unit 20, configured to write a first sampling signal when the count value of the cyclic counter is an intermediate value into the FIFO memory by using the high-frequency clock as a write clock; reading out the signal written into the FIFO memory from the FIFO memory by taking the local clock as a read clock to obtain a second serial signal synchronized to the local clock domain;
a shift register unit 40, configured to shift register the second serial signal under the local clock to obtain a parallel signal;
wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter 70 is the same as a multiple of the high frequency clock.
Optionally, the shift register unit 40 includes:
a positioning signal detection unit for detecting a positioning signal sequence in the second serial signal;
a start bit confirmation unit configured to take a next bit of the positioning signal sequence as a start bit if the positioning signal sequence is detected;
and the shift register subunit is used for shift registering the second serial signal taking the start bit as a starting point under a local clock to obtain a parallel signal.
In specific implementation, the present invention further provides a computer storage medium, where the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments of the serial signal clock synchronization method provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be essentially or partially implemented in the form of a software product, which may be stored in a storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the embodiments or some parts of the embodiments.
The same and similar parts in the various embodiments in this specification may be referred to each other. The above-described embodiments of the present invention should not be construed as limiting the scope of the present invention.
Claims (14)
1. A serial signal clock synchronization method based on FPGA is characterized by comprising the following steps:
under a high-frequency clock, oversampling a first serial signal input from the outside to obtain a first sampling signal;
writing a first sampling signal when the count value of the cycle counter is an intermediate value into the FIFO memory by taking the high-frequency clock as a write clock;
reading out the signal written into the FIFO memory from the FIFO memory by taking the local clock as a read clock to obtain a second serial signal synchronized to the local clock domain;
wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter is the same as a multiple of the high frequency clock.
2. The method of claim 1, wherein the step of obtaining the first sampling signal is followed by the step of:
and resetting the cycle counter if the first sampling signal jumps.
3. The method of claim 2, wherein the step of resetting the cycle counter if the first sample signal transitions further comprises, prior to the step of resetting the cycle counter:
performing edge detection on the first sampling signal under the high-frequency clock to obtain an edge detection signal;
and judging whether the first sampling signal jumps or not according to the edge detection signal.
4. The method for clock synchronization of serial signals based on FPGA of claim 1, wherein said step of writing the first sampling signal when the count value of the cycle counter is the middle value into the FIFO memory using said high frequency clock as a write clock comprises:
if the count value of the cycle counter is an intermediate value, registering the first sampling signal under the high-frequency clock to obtain a third serial signal;
and writing the third serial signal into a FIFO memory by taking the high-frequency clock as a write clock.
5. The clock synchronization method for serial signals based on FPGA of claim 1, wherein said step of oversampling a first serial signal inputted from outside under a high frequency clock to obtain a first sampling signal comprises:
and under a high-frequency clock, delaying the first serial signal for two high-frequency clock periods for registering to obtain a first sampling signal.
6. A serial-to-parallel method based on FPGA is characterized by comprising the following steps:
under a high-frequency clock, oversampling a first serial signal input from the outside to obtain a first sampling signal;
writing a first sampling signal when the count value of the cycle counter is an intermediate value into the FIFO memory by taking the high-frequency clock as a write clock;
reading out the signal written into the FIFO memory from the FIFO memory by taking the local clock as a read clock to obtain a second serial signal synchronized to the local clock domain;
under the local clock, the second serial signal is shifted and registered to obtain a parallel signal;
wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter is the same as a multiple of the high frequency clock.
7. The FPGA-based serial-to-parallel method according to claim 6, wherein the step of shift registering the second serial signal under the local clock to obtain a parallel signal comprises:
detecting a positioning signal sequence in the second serial signal;
if the positioning signal sequence is detected, taking the next bit of the positioning signal sequence as a start bit;
and under a local clock, shifting and registering the second serial signal taking the start bit as a starting point to obtain a parallel signal.
8. A serial signal clock synchronization device based on FPGA is characterized by comprising:
the over-sampling unit is used for over-sampling a first serial signal transmitted from the outside under a high-frequency clock to obtain a first sampling signal;
the clock synchronization unit is used for taking the high-frequency clock as a write clock and writing a first sampling signal when the count value of the cycle counter is an intermediate value into the FIFO memory; the FIFO memory is used for reading out the signals written into the FIFO memory by taking the local clock as the read clock, and obtaining second serial signals synchronized to the local clock domain;
wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter is the same as a multiple of the high frequency clock.
9. The FPGA-based serial signal clock synchronization apparatus of claim 8, further comprising a counter calibration unit coupled to said oversampling unit, said counter calibration unit configured to reset said cycle counter when a transition occurs in said first sampling signal.
10. The FPGA-based serial signal clock synchronization apparatus of claim 9, further comprising:
the edge detection unit is used for carrying out edge detection on the first sampling signal to obtain an edge detection signal;
and the jump judging unit is respectively connected with the edge detecting unit and the counter calibrating unit and is used for judging whether the first sampling signal jumps or not according to the edge detecting signal.
11. The FPGA-based serial signal clock synchronization apparatus of claim 8, wherein said clock synchronization unit comprises:
the first register unit is used for registering the first sampling signal under the high-frequency clock to obtain a third serial signal when the count value is an intermediate value;
and the writing unit is used for writing the third serial signal into the FIFO memory by taking the high-frequency clock as a writing clock.
12. The FPGA-based serial signal clock synchronization apparatus of claim 8, wherein said oversampling unit comprises:
and the second register unit delays the first serial signal for two high-frequency clock periods to register under a high-frequency clock to obtain a first sampling signal.
13. A serial-parallel conversion device based on FPGA is characterized by comprising:
the over-sampling unit is used for over-sampling a first serial signal transmitted from the outside under a high-frequency clock to obtain a first sampling signal;
the clock synchronization unit is used for taking the high-frequency clock as a write clock and writing a first sampling signal when the count value of the cycle counter is an intermediate value into the FIFO memory; reading out the signal written into the FIFO memory from the FIFO memory by taking the local clock as a read clock to obtain a second serial signal synchronized to the local clock domain;
the shift register unit is used for shift registering the second serial signal under the local clock to obtain a parallel signal;
wherein the high frequency clock is at least three times the local clock; the cycle period T of the cycle counter is the same as a multiple of the high frequency clock.
14. The FPGA-based serial-parallel connection apparatus of claim 13, wherein said shift register unit comprises:
a positioning signal detection unit for detecting a positioning signal sequence in the second serial signal;
a start bit confirmation unit configured to take a next bit of the positioning signal sequence as a start bit if the positioning signal sequence is detected;
and the shift register subunit is used for shift registering the second serial signal taking the start bit as a starting point under a local clock to obtain a parallel signal.
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| CN111867183B (en) * | 2019-04-08 | 2022-11-22 | 华润微集成电路(无锡)有限公司 | LED drive circuit, power frequency square wave signal sampling circuit and method |
| CN112765073A (en) * | 2019-11-04 | 2021-05-07 | 中车株洲电力机车研究所有限公司 | Data sampling method, system, storage medium and computer equipment |
| US11003206B1 (en) | 2020-01-03 | 2021-05-11 | Rockwell Collins, Inc. | Field-programmable gate array precision input timing |
| CN111314019A (en) * | 2020-01-19 | 2020-06-19 | 浙江恒强科技股份有限公司 | Method for improving baud rate of parallel bus |
| CN113110821B (en) * | 2021-04-19 | 2022-02-01 | 中国电子科技集团公司第五十八研究所 | Delay configurable asynchronous FIFO circuit |
| CN114218139A (en) * | 2021-12-15 | 2022-03-22 | 北京航天控制仪器研究所 | Simulation turntable high-speed synchronous acquisition method based on real-time operating system and FPGA |
| CN114461473B (en) * | 2022-01-29 | 2023-03-31 | 北京奕斯伟计算技术股份有限公司 | Method for detecting time sequence of serializer, detection circuit and electronic device |
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