CN115656776A

CN115656776A - Delay deviation measuring method and device of digital channel and electronic device

Info

Publication number: CN115656776A
Application number: CN202211335219.8A
Authority: CN
Inventors: 王俊; 王立新; 杜昊
Original assignee: Hangzhou Changchuan Technology Co Ltd
Current assignee: Hangzhou Changchuan Technology Co Ltd
Priority date: 2021-10-28
Filing date: 2022-10-28
Publication date: 2023-01-31
Also published as: CN113985251A; CN220207786U

Abstract

The application relates to a delay deviation measuring method, a delay deviation measuring device and an electronic device of a digital channel, wherein the method comprises the following steps: synchronously sending a preset periodic waveform signal from the head ends of a first digital channel and a second digital channel to be detected; acquiring N clock signals, wherein the phase of the next clock signal in the N clock signals is delayed by a first preset clock period compared with the phase of the previous clock signal; sampling the tail end of the first digital channel to obtain at least P first sampling signals; sampling the tail end of the second digital channel to obtain at least Q second sampling signals; and determining a phase deviation value of the signals output by the two digital channel ends based on the at least P first sampling signals and the at least Q second sampling signals. By the method and the device, the problems of high measurement cost or complex measurement process and low fault tolerance rate in measurement of delay deviation among multiple channels in the related technology are solved, and the measurement cost and the measurement complexity are reduced in the process of measuring the delay deviation among the multiple channels.

Description

Delay deviation measuring method and device of digital channel and electronic device

Technical Field

The present disclosure relates to the field of calibration and verification, and in particular, to a method, an apparatus, and an electronic apparatus for measuring delay skew of a digital channel.

Background

ATE automatic test equipment, as a special equipment for detecting chip function and performance, has higher precision standard in the aspect of performance detection, and particularly has a Timing calibration technology with a digital resource version in ATE equipment, the calibration precision of the ATE automatic test equipment can directly influence the overall test precision and test capability of the equipment, and the calibration precision is generally a time deviation value among multiple channels.

The current method for measuring the deviation value between multiple channels is to measure by high-cost measuring equipment such as a high-speed oscilloscope and the like, to input a measured signal and a reference signal into special equipment at one time by using a mechanical arm and the like, and then to read a measuring result, or to measure by using a high-precision time measuring chip with a complex measuring process. It can be seen that the method for measuring the multi-channel inter-deviation value in the prior art has the problems of high measurement cost, complex measurement process and low fault tolerance rate, and is not suitable for measurement. Based on this, no effective solution is provided at present for the problems of high measurement cost, complex measurement process and low fault tolerance rate existing in the measurement of delay deviation among multiple channels in the current related technology.

Disclosure of Invention

The embodiment provides a method, a device and an electronic device for measuring delay deviation of a digital channel, so as to solve the problems of high measurement cost, complex measurement process and low fault tolerance rate in the measurement of delay deviation among multiple channels in the related art.

In a first aspect, a delay skew measurement method for a digital channel is provided in this embodiment, including: synchronously sending a preset periodic waveform signal from the head ends of a first digital channel and a second digital channel to be detected; acquiring N clock signals, wherein the phase of a later clock signal in the N clock signals is delayed by a first preset clock period compared with the phase of a former clock signal; based on rising edges of at least first P clock signals in the N clock signals, respectively sampling at the tail end of the first digital channel to obtain at least P first sampling signals, wherein the P-th first sampling signal in the at least P first sampling signals is an all-zero signal; based on rising edges of at least the first Q clock signals in the N clock signals, respectively sampling at the tail end of the second digital channel to obtain at least Q second sampling signals, wherein the Q-th second sampling signal in the at least Q second sampling signals is an all-zero signal; determining a phase offset value of signals output by the ends of the first digital channel and the second digital channel based on the at least P first sampling signals and the at least Q second sampling signals, wherein N, P and Q are all positive integers greater than or equal to 3.

In one embodiment, the preset periodic waveform signal has a pulse width greater than half a clock period, and the period of the periodic waveform is not less than three clock periods.

In another embodiment, the determining a phase deviation value of the signals output by the ends of the first digital channel and the second digital channel based on the at least P first sampled signals and the at least Q second sampled signals comprises:

determining a phase relation of signals output by the first digital channel and the second digital channel end based on an R-th first sampling signal in the at least P first sampling signals and an R-th second sampling signal in the at least Q second sampling signals, wherein R is a positive integer not greater than P and Q, and the R-th first sampling signal and the R-th second sampling signal are both non-all-zero signals; determining the number of first preset clock cycles of phase deviation of signals output by the first digital channel and the second digital channel end based on the number of non-all-zero signals in the at least P first sampling signals and the number of non-all-zero signals in the at least Q second sampling signals; and determining the phase deviation value of the signals output by the tail ends of the first digital channel and the second digital channel based on the phase relation of the signals output by the tail ends of the first digital channel and the second digital channel and the number of the first preset clock cycles.

In one embodiment, determining the phase relationship of the signals output at the ends of the first digital channel and the second digital channel based on the R-th first sampling signal of the at least P first sampling signals and the R-th second sampling signal of the at least Q second sampling signals comprises: determining that the phase of the signal output from the end of the first digital channel is one clock cycle earlier than the phase of the signal output from the end of the second digital channel in the case that the binary value obtained by shifting the binary value of the first R-th sampling signal by one bit to the right is the same as the binary value of the second R-th sampling signal; determining that the phase of the signal output from the end of the first digital channel is one clock cycle later than the phase of the signal output from the end of the second digital channel, in the case that the binary value obtained by shifting the binary value of the first R-th sampling signal by one bit to the left is the same as the binary value of the second R-th sampling signal; and under the condition that the binary value of the R-th first sampling signal is the same as that of the R-th second sampling signal, determining that the phase of the signal output by the end of the first digital channel and the phase of the signal output by the end of the second digital channel are in the same clock cycle.

In another embodiment, the binary values of the first R-th sampling signal are determined by the corresponding sampling values of all the sampling points in the first R-th sampling signal, and the binary values of the second R-th sampling signal are determined by the corresponding sampling values of all the sampling points in the second R-th sampling signal.

In one embodiment, the binary values of the R-th first sampling signal are determined by sampling values corresponding to continuous partial sampling points in the R-th first sampling signal, and the binary values of the R-th second sampling signal are determined by sampling values corresponding to continuous partial sampling points in the R-th second sampling signal; wherein the positions of consecutive partial sampling points in the R-th first sampling signal and consecutive partial sampling points in the R-th second sampling signal correspond to each other, and neither a binary value of the R-th first sampling signal nor a binary value of the R-th second sampling signal is equal to zero.

In another embodiment, determining the phase deviation value of the signals output by the ends of the first digital channel and the second digital channel based on the phase relationship of the signals output by the ends of the first digital channel and the second digital channel and the number of the first preset clock cycles comprises: the phase deviation value of the end output signals of the first digital channel and the second digital channel is equal to the product of the representative value of the phase relation of the signals output by the ends of the first digital channel and the second digital channel and the clock period, and is added with the product of the number of the first preset clock periods and the first preset clock period.

In one embodiment, if the phase relationship between the signals output by the first digital channel and the second digital channel is that the phase of the signal output by the first digital channel is earlier than the phase of the signal output by the second digital channel by one clock cycle, then the representative value of the phase relationship between the signals output by the first digital channel and the second digital channel is 1; if the phase relation of the signals output by the first digital channel and the second digital channel is that the phase of the signal output by the first digital channel is one clock cycle later than the phase of the signal output by the second digital channel, the representative value of the phase relation of the signals output by the first digital channel and the second digital channel is-1; if the phase relationship between the signals at the ends of the first digital channel and the second digital channel is that the phase of the signal output at the end of the first digital channel and the phase of the signal output at the end of the second digital channel are in the same clock cycle, then the representative value of the phase relationship between the signals output at the ends of the first digital channel and the second digital channel is 0.

In a second aspect, in this embodiment, there is provided a delay skew measuring apparatus for a digital channel, including:

the signal sending module to be tested: the system comprises a first digital channel to be tested, a second digital channel to be tested, a first signal processing module and a second signal processing module, wherein the first digital channel to be tested and the second digital channel to be tested are used for synchronously transmitting a preset periodic waveform signal from the head ends of the first digital channel and the second digital channel to be tested; a clock cycle acquisition module: the clock signal acquisition unit is used for acquiring N clock signals, wherein the phase of the latter clock signal in the N clock signals is delayed by a first preset clock period compared with the phase of the former clock signal; a first sampled signal sampling module: the digital signal processing circuit is used for obtaining at least P first sampling signals by sampling at the tail end of the first digital channel respectively based on the rising edges of at least the first P clock signals in the N clock signals, wherein the P-th first sampling signal in the at least P first sampling signals is an all-zero signal; a second sampled signal sampling module: the second digital channel is used for obtaining at least Q second sampling signals by sampling at the tail end of the second digital channel respectively based on the rising edges of at least the first Q clock signals in the N clock signals, wherein the Q-th second sampling signal in the at least Q second sampling signals is an all-zero signal; a deviation value calculation module: and the phase deviation value of the signals output by the tail ends of the first digital channel and the second digital channel is determined based on the at least P first sampling signals and the at least Q second sampling signals, wherein N, P and Q are all positive integers which are larger than equal to 3.

In a third aspect, in this embodiment, there is provided an electronic apparatus, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor executes the computer program to implement the delay skew measurement method for digital channels according to the first aspect.

Compared with the related art, in the delay deviation measurement method of the digital channel provided in this embodiment, the preset periodic waveform signal is synchronously sent from the head ends of the first digital channel and the second digital channel to be measured; acquiring N clock signals, wherein the phase of the latter clock signal in the N clock signals is delayed by a first preset clock period compared with the phase of the former clock signal; based on at least the first P clock signals in the N clock signals, respectively sampling at the tail end of the first digital channel to obtain at least P first sampling signals, wherein the at least P first sampling signals comprise at least one all-zero signal and at least one non-all-zero signal; respectively sampling at the tail end of the second digital channel to obtain at least Q second sampling signals based on at least the first Q clock signals in the N clock signals, wherein the at least Q second sampling signals comprise at least one all-zero signal and at least one non-all-zero signal; based on the at least P first sampling signals and the at least Q second sampling signals, the phase deviation value of the signals output by the tail ends of the first digital channel and the second digital channel is determined, wherein N, P and Q are positive integers, and P and Q are not more than N, so that the problems of high measurement cost, complex measurement process and low fault tolerance rate in measurement of delay deviation among multiple channels in the related technology are solved, and the reduction of measurement cost and measurement complexity in measurement of delay deviation among multiple channels are realized.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

fig. 1 is a flowchart of a delay skew measurement method of a digital channel according to an embodiment of the present application.

Fig. 2 is a schematic diagram of a sampling signal of a delay variation measuring method of a digital channel according to an embodiment of the present application.

Fig. 3 is a phase relationship representation of a delay skew measurement method for a digital channel according to an embodiment of the present application.

Fig. 4 is a schematic diagram of an overall measurement flow structure of a delay variation measurement apparatus of a digital channel according to an embodiment of the present application.

Fig. 5 is a schematic diagram of functional blocks of various parts of a delay variation measuring apparatus of a digital channel according to an embodiment of the present application.

Fig. 6 is a block diagram of a delay variation measuring apparatus of a digital channel according to an embodiment of the present application.

Detailed Description

For a clearer understanding of the objects, technical solutions and advantages of the present application, reference is made to the following description and accompanying drawings.

Unless defined otherwise, technical or scientific terms used herein shall have the same general meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The use of the terms "a" and "an" and "the" and similar referents in the context of this application do not denote a limitation of quantity, either in the singular or the plural. The terms "comprises," "comprising," "has," "having," and any variations thereof, as referred to in this application, are intended to cover non-exclusive inclusions; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to the listed steps or modules, but may include other steps or modules (elements) not listed or inherent to such process, method, article, or apparatus. Reference in this application to "connected," "coupled," and the like is not intended to be limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Reference to "a plurality" in this application means two or more. "and/or" describes an association relationship of associated objects, meaning that three relationships may exist, for example, "A and/or B" may mean: a exists alone, A and B exist simultaneously, and B exists alone. In general, the character "/" indicates a relationship in which the objects associated before and after are an "or". Reference in the present application to the terms "first," "second," "third," etc., merely distinguish between similar objects and do not denote a particular order or importance to the objects.

In this embodiment, a method for measuring delay skew of a digital channel is provided, and fig. 1 is a flowchart of a method for measuring delay skew of a digital channel according to an embodiment of the present application, and as shown in fig. 1, the flowchart includes the following steps:

step S201, a preset periodic waveform signal is synchronously transmitted from the head ends of the first digital channel and the second digital channel to be measured.

The purpose of this embodiment is to measure the delay skew between two digital channels, and based on this, it can be understood that if there is a delay skew between two digital channels, the two digital channels transmit the same signal, and the time when the signal sent at the head end of the channel is received at the tail end of the channel is different. Therefore, in this embodiment, a preset periodic waveform signal is sent synchronously at the head ends of the first digital channel and the second digital channel, the waveform of the preset periodic waveform signal in this embodiment is periodically changed, and in addition, in addition to the periodic change, the period length and the wavelength of the periodic waveform signal can also be set according to the specific embodiment, and it is only necessary to ensure that the signals sent to the first digital channel and the second digital channel are periodic signals.

In step S202, N clock signals are obtained, and a phase of a subsequent clock signal of the N clock signals is delayed by a first preset clock period compared with a phase of a previous clock signal.

It will be appreciated that in the previous step, by transmitting a predetermined periodic waveform signal to the head ends of the first digital channel and the second digital channel, the predetermined periodic signal is then output at the tail end of the digital channels, and an offset value is then derived based on the signal received from the tail end. However, when a signal is received, because a unit of the deviation value is small, a deviation conclusion between the periodic waveform signal and the last clock signal cannot be directly obtained, based on which, in this embodiment, the periodic waveform signal is sampled by the clock signal, and a signal difference that is easier to calculate is obtained by sampling the clock signal, in this embodiment, N clock signals are obtained first, and every two adjacent clock signals in the N clock signals have a delay relationship, in this embodiment, a value of the delay may be set arbitrarily, and the first preset clock period may be 1/N clock period, or may be a delay period length that is set arbitrarily, only by ensuring that the period length of the first preset clock period is smaller than 1 standard clock period, based on the delayed clock signal, the delay between channels may be obtained by sampling the periodic signal more accurately without requiring a very small clock signal, therefore, in this embodiment, N clock signals are obtained, and a delay between every two adjacent clock signals in the N clock signals is the first preset clock period, and in addition, a delay between the 1 st clock signal and the last clock signal is not more than 1 clock period.

Step S203, based on the rising edge of at least the first P clock signals in the N clock signals, obtaining at least P first sampling signals by sampling at the end of the first digital channel, respectively, where the pth first sampling signal in the at least P first sampling signals is an all-zero signal.

In this embodiment, the N clock signals obtained by the above embodiment are used to sample the preset periodic waveform signal received by the end of the first digital channel from the head end of the first digital channel, and in this embodiment, the preset periodic waveform signal is sampled by the rising edge of the clock signal, it can be understood that, when sampling is performed on the end of the first digital channel, one first sampling signal is obtained by each sampling, N first sampling signals can be sampled by the N clock signals, and when at least one all-zero signal and at least one non-all-zero signal exist in the first sampling signal, the calculation of the phase offset value can be performed, so that, after sampling is performed on the end of the first digital channel by the first P clock signals, at least the P-th signal of the obtained at least P first sampling signals is always an all-zero signal, and thus, sampling can be completed. It can be understood that the first sampling signal includes a plurality of sampling data, the sampling data includes zero-value sampling data and non-zero-value sampling data, when the clock signal is on a rising edge, if the periodic waveform signal is at a high level, the sampling data is a non-zero value, if the periodic waveform signal is at a non-high level, the sampling data is a zero value, if all the sampling data in the sampling signal are zero values, the sampling signal is an all-zero signal, and if there are non-zero values in the sampling data in the sampling signal, the sampling signal is a non-all-zero signal.

Step S204, based on rising edges of at least the first Q clock signals in the N clock signals, obtaining at least Q second sampling signals by sampling at the end of the second digital channel, where the at least Q second sampling signals include at least one all-zero signal and at least one non-all-zero signal, and a qth second sampling signal in the at least Q second sampling signals is an all-zero signal.

As in step S203, the end of the second digital channel is sampled by at least the first Q clock signals of the N clock signals, where the Q second sampling signals obtained by the first Q clock signals at least include an all-zero signal and at least one non-all-zero signal, so as to ensure that the delay skew measurement can be performed by the second sampling signals.

Step S205, determining a phase deviation value of signals output from the ends of the first digital channel and the second digital channel based on the at least P first sampling signals and the at least Q second sampling signals, where N, P, and Q are positive integers greater than or equal to 3.

In this embodiment, the comparison between the two channel sampling signals is performed through at least P first sampling signals and at least Q second sampling signals, further, the phase relationship between the two channels is determined through the comparison result, and then the phase deviation value is calculated through the number of non-all-zero signals and all-zero signals in the two signals, so as to obtain the phase deviation value between the two channels.

Through the steps, the preset periodic waveform signals are sent to the head ends of the first digital channel and the second digital channel, then a plurality of adjacent clock signals with the same delay are obtained, signal sampling is carried out on the tail ends of the first digital channel and the second digital channel, a first sampling signal and a second sampling signal are obtained, then the phase deviation value of the first digital channel and the second digital channel is calculated based on the first sampling signal and the second sampling signal, the problems that in the related technology, the measurement cost is high, the measurement process is complex, and the fault tolerance rate is low in the measurement of delay deviation among multiple channels are solved, and the measurement cost and the measurement complexity degree are reduced when the delay deviation among multiple channels is measured.

In one embodiment, the pulse width of the preset periodic waveform signal is greater than half a clock period, and the period of the periodic waveform is not less than three clock periods.

As shown in fig. 2, in this embodiment, in order to ensure normal sampling of the signal, the pulse width of the periodic waveform needs to be set to be greater than half of the clock period, and based on this, a plurality of clock periods are prevented from acquiring a high level of the same waveform signal in the sampling process, so as to ensure that the preset periodic waveform signal is subjected to signal sampling at the end of the digital channel through the clock signal. In addition, in this embodiment, the premise that the phase relationship between the two channels is determined by the first sampling signal and the second sampling signal is that the sampling signal at least includes three sets of sampling data, and the number of the sampling data is determined by the ratio of the period of the periodic waveform to the clock period. Therefore, the accuracy of sampling the signal and the accuracy of judging the phase relation can be improved.

In another embodiment, said determining a phase deviation value of signals output by the ends of said first digital channel and said second digital channel based on said at least P first sampled signals and said at least Q second sampled signals comprises: determining a phase relation of signals output by the first digital channel and the second digital channel end based on an R-th first sampling signal in the at least P first sampling signals and an R-th second sampling signal in the at least Q second sampling signals, wherein R is a positive integer not greater than P and Q, and the R-th first sampling signal and the R-th second sampling signal are both non-all-zero signals; determining the number of first preset clock cycles of phase deviation of signals output by the first digital channel and the second digital channel end based on the number of non-all-zero signals in the at least P first sampling signals and the number of non-all-zero signals in the at least Q second sampling signals; and determining a phase deviation value of the signals output by the tail ends of the first digital channel and the second digital channel based on the phase relation of the signals output by the tail ends of the first digital channel and the second digital channel and the number of the first preset clock cycles.

It can be understood that, in this embodiment, the manner of obtaining the phase deviation value through the at least P first sampling signals and the at least Q second sampling signals obtained through sampling is as follows: firstly, determining the phase relationship of signals output by the tail ends of a first digital channel and a second digital channel based on a first sampling signal and a second sampling signal which are obtained by delaying the same clock signal, namely at least an R-th first sampling signal in P first sampling signals and an R-th second sampling signal in at least Q second sampling signals; then, after confirming the phase relationship between the first sampling signal and the second sampling signal, determining the time length of the phase deviation based on the number of non-all-zero signals in at least P first sampling signals, namely the number of non-all-zero signals before the first all-zero signal appears and the number of non-all-zero signals in at least Q second sampling signals when the first sampling signals are obtained, and obtaining the phase deviation value of the signals output by the tail ends of the first digital channel and the second digital channel based on the phase relationship and the time length and the signal period unit in the current signal through calculation. The phase deviation value calculated based on the method improves the efficiency of obtaining the phase deviation value and reduces the calculation cost.

In one embodiment, determining the phase relationship of the signals output at the ends of the first digital channel and the second digital channel based on the R-th first sampling signal of the at least P first sampling signals and the R-th second sampling signal of the at least Q second sampling signals comprises: determining that the phase of the signal output from the end of the first digital channel is one clock cycle earlier than the phase of the signal output from the end of the second digital channel in the case that the binary value obtained by shifting the binary value of the R-th first sampling signal by one bit to the right is the same as the binary value of the R-th second sampling signal; determining that the phase of the signal output from the end of the first digital channel is one clock cycle later than the phase of the signal output from the end of the second digital channel, in the case that the binary value obtained by shifting the binary value of the first R-th sampling signal by one bit to the left is the same as the binary value of the second R-th sampling signal; and under the condition that the binary value of the R-th first sampling signal is the same as that of the R-th second sampling signal, determining that the phase of the signal output by the end of the first digital channel and the phase of the signal output by the end of the second digital channel are in the same clock cycle.

In this embodiment, as shown in fig. 3, the phase relationship table is determined by the binary value shift relationship of the sampling signals, and when the binary value of the R-th first sampling signal is shifted to the right by one bit, i.e. delayed by one clock cycle, in this case, the first sampling signal is the same as the second sampling signal, i.e. the phase of the signal output at the end of the first digital channel is considered to be one clock cycle earlier than the phase of the signal output at the end of the second digital channel; similarly, if the binary value of the first sampling signal is shifted to the left by one bit, that is, by one clock cycle, based on this, if the shifted first sampling signal is the same as the corresponding second sampling signal, the phase of the signal output from the end of the first digital channel can be considered to be one clock cycle later than the phase of the signal output from the end of the second digital channel; if the phase shift is not required, then the phase of the signal output at the end of the first digital channel and the phase of the signal output at the end of the second digital channel are considered to be the same, i.e., in the same cycle. Based on the judgment method, when the phase relation between the channels is determined through the sampling signals, the judgment efficiency is improved.

In another embodiment, the binary values of the R-th first sampling signal are determined from the sample values corresponding to all of the sample points in the R-th first sampling signal, and the binary values of the R-th second sampling signal are determined from the sample values corresponding to all of the sample points in the R-th second sampling signal.

It will be appreciated that the binary value of the first sampled signal is determined by the corresponding sampled values of all sampled points. That is, when the preset periodic waveform signal received by the first digital channel terminal is sampled by the clock signal, a series of sampling values are obtained, wherein each sampling value is obtained from a corresponding sampling point; in this embodiment, the state of the corresponding periodic waveform signal may be determined at each rising edge of the clock signal, if the sampling value is a non-zero value, the sampling value is a high level, and if the sampling value is a zero value, a plurality of binary values in the first sampling signal may be obtained based on the non-zero value, and based on the binary values, the sampling result of the periodic waveform signal based on the clock signal may be effectively expressed. The sampling result is more obvious, the phase judgment and the deviation calculation are easier to carry out, and the efficiency of calculating the phase deviation is improved.

In one embodiment, the binary values of the R-th first sampling signal are determined by the sampling values corresponding to the consecutive partial sampling points in the R-th first sampling signal, and the binary values of the R-th second sampling signal are determined by the sampling values corresponding to the consecutive partial sampling points in the R-th second sampling signal; wherein the positions of consecutive partial sampling points in the R-th first sampling signal and consecutive partial sampling points in the R-th second sampling signal correspond to each other, and neither a binary value of the R-th first sampling signal nor a binary value of the R-th second sampling signal is equal to zero.

In the embodiment, the binary value of the first sampling signal is determined by sampling values corresponding to continuous partial sampling points in the first sampling signal; it can be understood that, in the present embodiment, each sampling is performed by sampling the periodic waveform signal through the clock signal, therefore, the continuous sampling point corresponds to the fixed sampling point of each period in the clock signal, the periodic waveform signal is sampled through the fixed sampling point, and the sampling value is obtained according to the sampling result. For example, at each rising edge of the clock signal, the periodic waveform signal is sampled, and if the sampling result is high, the sampling value is 1, and if the sampling result is low, the sampling value is 0, so that the sampling at the end of the first digital channel and the sampling at the end of the second digital channel are in the same sampling manner. In addition, since the phase relationship cannot be judged by two all-zero sampling signals, the first R-th sampling signal and the second sampling signal for judging the phase relationship need to be non-all-zero sampling signals, and based on the result, the judgment of the phase relationship can be guaranteed to be completed.

In another embodiment, determining the phase deviation value of the signals output by the ends of the first digital channel and the second digital channel based on the phase relationship of the signals output by the ends of the first digital channel and the second digital channel and the number of the first preset clock cycles comprises: and the phase deviation value of the output signals at the tail ends of the first digital channel and the second digital channel is equal to the product of the representative value of the phase relation of the signals output at the tail ends of the first digital channel and the second digital channel and the clock period, and is added with the product of the number of the first preset clock periods and the first preset clock period.

In this embodiment, the calculation is performed based on the total clock phase difference, that is, the calculation is performed based on the phase relationship and the size of the clock cycle, and then the specific deviation value is calculated by the product of the number of the first preset clock cycles and the first preset clock cycle, it can be understood that the number of the first preset clock cycles may be replaced by a negative number, that is, when the number of the non-all-zero signals in the first sampling signal is smaller than the number of the non-all-zero signals in the second sampling signal, the number of the first preset clock cycles is a negative number; then, a specific value of the phase deviation value is determined by the number of the phase differences within the first preset clock period, and it can be understood that the greater the number of the phase differences within the first preset clock period is, the greater the deviation value is, the greater the first preset clock period is, the greater the deviation value is. Based on the method, the size of the phase deviation value can be calculated more accurately, and calculation errors are reduced.

In one embodiment, if the phase relationship between the signals output by the first digital channel and the second digital channel is that the phase of the signal output by the first digital channel is earlier than the phase of the signal output by the second digital channel by one clock cycle, then the representative value of the phase relationship between the signals output by the first digital channel and the second digital channel is 1; if the phase relationship between the signals output by the ends of the first digital channel and the second digital channel is that the phase of the signal output by the end of the first digital channel is one clock cycle later than the phase of the signal output by the end of the second digital channel, then the representative value of the phase relationship between the signals output by the ends of the first digital channel and the second digital channel is-1, and if the phase relationship between the signals output by the ends of the first digital channel and the second digital channel is that the phase of the signal output by the end of the first digital channel and the phase of the signal output by the end of the second digital channel are in the same clock cycle, then the representative value of the phase relationship between the signals output by the ends of the first digital channel and the second digital channel is 0.

It is easy to understand that if the phase of the signal output from the end of the first digital channel is one clock cycle earlier than the phase of the signal output from the end of the second digital channel, the deviation value of the first digital channel from the second digital channel should be calculated on the basis of 1 clock cycle, based on which the representative value of the phase is 1; similarly, if the phase of the signal output at the end of the first digital channel is one clock cycle later than the phase of the signal output at the end of the second digital channel, then the offset value for the first digital channel and the second digital channel should be calculated on a-1 clock cycle basis; if the phase of the signal output by the end of the first digital channel and the phase of the signal output by the end of the second digital channel are in the same clock cycle, the deviation value is 0 clock cycle, and on the basis, the specific deviation value is calculated through the number of the first preset clock cycles and the first preset clock cycles, so that accurate calculation of the final deviation value is guaranteed.

In this embodiment, as shown in fig. 4, the delay skew measurement process of a specific digital channel is mainly performed by the measurement device CHK _ TCT, which is used for measuring the delay skew of a signal received by the POGO connector and transmitted by a driver in Pin electronics between a plurality of channels (TC [255 ] 0) at the same time, and the signal received by the POGO connector is measured in parallel by CHK _ TCT, and the skew values between the remaining channels and T0 are calculated with T0 as a reference.

In one embodiment, as shown in fig. 5, the implementation apparatus of the delay deviation measurement method for a digital channel is designed for automatically measuring a mutual time difference between 256 signals output by a digital board in ATE equipment and arriving at a connector, and basically comprises the following components, where an external interface may be an SPI interface responsible for communication with a host, or other communication interfaces responsible for communication with the host, and a TC [ 255; the main components of the parts are described as follows: (1) the measurement unit takes the FPGA as a core device and is responsible for sampling and algorithm processing of a measured signal and communication with a host; (2) the clock PLL chip outputs a sampling clock with adjustable frequency, defaults to 200MHz and has extremely low clock jitter performance; (3) the delay line chip is used for delaying the clock phase output by the PLL chip and then providing the clock phase to the FPGA as a sampling clock, the delay step length of the chip is 10ps, namely the measurement resolution, and the maximum delay step length is 1023 steps; (4) the Flash chip stores the FPGA loading file; (5) the Flash chip stores the time correlation calculation result; (6) the crystal oscillator is used as an FPGA system clock and is used for realizing management channels such as SPI, I2C and the like of each channel; (7) and the DAC chip outputs an adjustable voltage signal as the decision level of the I/O pin of the FPGA. The method is realized as follows: the measuring method is realized in an FPGA of a Measure Unit, the internal logic is shown in the following figure, a measured signal is introduced into a chip through an I/O pin and then enters an IODELAY module, and the module has the main functions of adjusting the routing delay from the chip pin to a trigger FF and the delay difference from a Sample Clock to different triggers and avoiding introducing extra delay errors; and the signals sampled and output by the trigger are calculated and processed by the algorithm logic unit to obtain a final deviation value. The basic principle of the measurement algorithm is to compare the delay difference between the channels by measuring the position deviation between the edge of the signal and the rising edge of the clock, taking fig. 2 as an example: (1) a Pattern Generator is used for sending a periodic waveform of a specific code Pattern, the specific requirements are that the pulse width needs to be more than half of a clock period and less than one clock period, the signal period needs at least 3 clock periods, and the specific period can be determined according to the maximum deviation of a measured signal; (2) 0, 1, 2, 3 and 4 are different phase sampling clocks of FPGA in the Measure Unit, the clock phase adjustment is realized by utilizing a DelayLine chip, 0 in the lower graph is a sampling clock at the initial moment, the DelayLine chip sets the delay time to be 0ps at the moment, 1 sets the sampling clock after the delay time is 10ps for the DelayLine chip, and the delay of 10ps is gradually increased by sequentially analogizing 2, 3 and 4; (3) sequentially using 0, 1, 2, 3 and 4 clocks for sampling until all channels have data converted from non-0 to all-0 and stop, and obtaining a plurality of sampling signals; (4) calculating according to the sampling result, firstly, judging the phase relation among channels through the first three-bit codes of the same sampling data, then adding the difference of the sampling times to obtain the time difference among the channels, and the phase relation table is shown in figure 3; (5) with TC0 as a reference, the sampling code of TC255 at the 0 th sampling is 001, TC0 is 100, which means that TC255 precedes TC0 by one clock cycle, and the sampling times are more than TC0, so that the final deviation value is: t255= T0-5ns (clock period) +1 × 10ps.

It should be noted that the steps illustrated in the above-described flow diagrams or in the flow diagrams of the figures may be performed in a computer system, such as a set of computer-executable instructions, and that, although a logical order is illustrated in the flow diagrams, in some cases, the steps illustrated or described may be performed in an order different than here.

In this embodiment, a delay deviation measurement apparatus of a digital channel is further provided, and the apparatus is used to implement the foregoing embodiments and preferred embodiments, and the description already made is not repeated. The terms "module," "unit," "sub-unit," and the like as used below may implement a combination of software and/or hardware of predetermined functions. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware or a combination of software and hardware is also possible and contemplated.

Fig. 6 is a block diagram of a delay variation measuring apparatus of a digital channel according to an embodiment of the present application, as shown in fig. 3, the apparatus including: the device comprises a signal to be tested sending module 10, a clock period acquiring module 20, a first sampling signal sampling module 30, a second sampling signal sampling module 40 and a deviation value calculating module 50.

The signal sending module to be tested 10: the device is used for synchronously sending a preset periodic waveform signal from the head ends of a first digital channel and a second digital channel to be tested.

The clock cycle acquisition module 20: the method comprises obtaining N clock signals, wherein the phase of the next clock signal in the N clock signals is delayed by a first preset clock period compared with the phase of the previous clock signal.

The clock cycle acquisition module 20: and the pulse width of the preset periodic waveform signal is more than half clock period, and the period of the periodic waveform is not less than three clock periods.

The first sampling signal sampling module 30: and the sampling circuit is used for sampling at the tail end of the first digital channel respectively to obtain at least P first sampling signals based on the rising edges of at least the first P clock signals in the N clock signals, wherein the No. P first sampling signals in the at least P first sampling signals are all-zero signals.

The second sampling signal sampling module 40: and the second sampling circuit is used for sampling at the tail end of the second digital channel respectively based on the rising edges of at least the first Q clock signals in the N clock signals to obtain at least Q second sampling signals, wherein the Q-th second sampling signal in the at least Q second sampling signals is an all-zero signal.

Deviation value calculation block 50: and the phase deviation value of the signals output by the tail ends of the first digital channel and the second digital channel is determined based on the at least P first sampling signals and the at least Q second sampling signals, wherein N, P and Q are all positive integers which are larger than equal to 3.

Deviation value calculation block 50: the phase relation between the signals output by the first digital channel and the tail end of the second digital channel is determined based on the R first sampling signal in the at least P first sampling signals and the R second sampling signal in the at least Q second sampling signals, wherein R is a positive integer not greater than P and Q, and the R first sampling signal and the R second sampling signal are both non-all-zero signals; determining the number of first preset clock cycles of phase deviation of signals output by the first digital channel and the second digital channel end based on the number of non-all-zero signals in the at least P first sampling signals and the number of non-all-zero signals in the at least Q second sampling signals; and determining the phase deviation value of the signals output by the tail ends of the first digital channel and the second digital channel based on the phase relation of the signals output by the tail ends of the first digital channel and the second digital channel and the number of the first preset clock cycles.

Deviation value calculation block 50: further comprising determining that the phase of the signal output from the end of the first digital channel is one clock cycle earlier than the phase of the signal output from the end of the second digital channel, in case that a binary value obtained by shifting the binary value of the first R-th sampling signal by one bit to the right is the same as the binary value of the second R-th sampling signal; determining that the phase of the signal output from the end of the first digital channel is one clock cycle later than the phase of the signal output from the end of the second digital channel, in the case that the binary value obtained by shifting the binary value of the first R-th sampling signal by one bit to the left is the same as the binary value of the second R-th sampling signal; and under the condition that the binary value of the R-th first sampling signal is the same as that of the R-th second sampling signal, determining that the phase of the signal output by the end of the first digital channel and the phase of the signal output by the end of the second digital channel are in the same clock cycle.

Deviation value calculation block 50: the binary value of the R first sampling signal is determined by sampling values corresponding to all sampling points in the R first sampling signal, and the binary value of the R second sampling signal is determined by sampling values corresponding to all sampling points in the R second sampling signal.

Deviation value calculation block 50: the binary value of the R-th first sampling signal is determined by the sampling values corresponding to the continuous partial sampling points in the R-th first sampling signal, and the binary value of the R-th second sampling signal is determined by the sampling values corresponding to the continuous partial sampling points in the R-th second sampling signal; wherein the positions of consecutive partial sampling points in the R-th first sampling signal and consecutive partial sampling points in the R-th second sampling signal correspond to each other, and neither a binary value of the R-th first sampling signal nor a binary value of the R-th second sampling signal is equal to zero.

Deviation value calculation block 50: the phase deviation value of the output signals at the tail ends of the first digital channel and the second digital channel is equal to the product of the representative value of the phase relation of the signals output at the tail ends of the first digital channel and the second digital channel and the clock period, and the product of the number of the first preset clock periods and the first preset clock period is added.

Deviation value calculation block 50: if the phase relation of the signals output by the first digital channel and the second digital channel is that the phase of the signal output by the first digital channel is earlier than that of the signal output by the second digital channel by one clock cycle, the representative value of the phase relation of the signals output by the first digital channel and the second digital channel is 1; if the phase relation of the signals output by the first digital channel and the second digital channel is that the phase of the signal output by the first digital channel is one clock cycle later than the phase of the signal output by the second digital channel, the representative value of the phase relation of the signals output by the first digital channel and the second digital channel is-1; if the phase relationship between the signals at the ends of the first digital channel and the second digital channel is that the phase of the signal output at the end of the first digital channel and the phase of the signal output at the end of the second digital channel are in the same clock cycle, then the representative value of the phase relationship between the signals output at the ends of the first digital channel and the second digital channel is 0.

The above modules may be functional modules or program modules, and may be implemented by software or hardware. For a module implemented by hardware, the modules may be located in the same processor; or the modules can be respectively positioned in different processors in any combination.

There is also provided in this embodiment an electronic device comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the steps of any of the method embodiments described above.

Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:

s1, synchronously sending a preset periodic waveform signal from head ends of a first digital channel and a second digital channel to be tested.

S2, N clock signals are obtained, and the phase of the latter clock signal is delayed by a first preset clock period compared with the phase of the former clock signal in the N clock signals.

And S3, respectively sampling at the tail end of the first digital channel to obtain at least P first sampling signals based on the rising edges of at least the first P clock signals in the N clock signals, wherein the No. P first sampling signals in the at least P first sampling signals are all-zero signals.

And S4, respectively sampling at the tail end of the second digital channel to obtain at least Q second sampling signals based on the rising edges of at least the first Q clock signals in the N clock signals, wherein the Q-th second sampling signal in the at least Q second sampling signals is an all-zero signal.

And S5, determining phase deviation values of signals output by the tail ends of the first digital channel and the second digital channel based on the at least P first sampling signals and the at least Q second sampling signals, wherein N, P and Q are all positive integers greater than equal 3.

It should be noted that, for specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and optional implementations, and details are not described again in this embodiment.

In addition, in combination with the delay variation measuring method of the digital channel provided in the foregoing embodiment, a storage medium may also be provided to implement this embodiment. The storage medium has a computer program stored thereon; the computer program, when executed by a processor, implements a delay skew measurement method of any of the digital channels in the above embodiments.

It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be derived by a person skilled in the art from the examples provided herein without inventive step, shall fall within the scope of protection of the present application.

It is obvious that the drawings are only examples or embodiments of the present application, and it is obvious to those skilled in the art that the present application can be applied to other similar cases according to the drawings without creative efforts. Moreover, it should be appreciated that such a development effort might be complex and lengthy, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure, and is not intended to limit the present disclosure to the particular forms disclosed herein.

The term "embodiment" is used herein to mean that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly or implicitly understood by one of ordinary skill in the art that the embodiments described in this application may be combined with other embodiments without conflict.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the patent protection. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method for delay skew measurement in a digital channel, comprising:

synchronously sending a preset periodic waveform signal from the head ends of a first digital channel and a second digital channel to be detected;

acquiring N clock signals, wherein the phase of the latter clock signal in the N clock signals is delayed by a first preset clock period compared with the phase of the former clock signal;

based on the rising edges of at least the first P clock signals in the N clock signals, respectively sampling at the tail end of the first digital channel to obtain at least P first sampling signals, wherein the P-th first sampling signal in the at least P first sampling signals is an all-zero signal;

based on rising edges of at least first Q clock signals in the N clock signals, respectively sampling at the tail end of the second digital channel to obtain at least Q second sampling signals, wherein the Q-th second sampling signal in the at least Q second sampling signals is an all-zero signal;

and determining the phase deviation value of the signals output by the tail ends of the first digital channel and the second digital channel based on the at least P first sampling signals and the at least Q second sampling signals, wherein N, P and Q are all positive integers which are more than or equal to 3.

2. The method of claim 1, wherein the pulse width of the predetermined periodic waveform signal is greater than half a clock period, and the period of the periodic waveform signal is not less than three clock periods.

3. The method of claim 2, wherein the determining the phase deviation values of the signals output from the ends of the first digital channel and the second digital channel based on the at least P first sampled signals and the at least Q second sampled signals comprises:

determining a phase relationship of signals output by the first digital channel and the second digital channel on the basis of an Rth first sampling signal of the at least P first sampling signals and an Rth second sampling signal of the at least Q second sampling signals, wherein R is a positive integer not greater than P and Q, and the Rth first sampling signal and the Rth second sampling signal are all non-all-zero signals;

determining the number of first preset clock cycles of phase deviation of signals output by the first digital channel and the second digital channel end based on the number of non-all-zero signals in the at least P first sampling signals and the number of non-all-zero signals in the at least Q second sampling signals;

and determining the phase deviation value of the signals output by the tail ends of the first digital channel and the second digital channel based on the phase relation of the signals output by the tail ends of the first digital channel and the second digital channel and the number of the first preset clock cycles.

4. The method of claim 3, wherein determining the phase relationship of the signals output at the ends of the first and second digital channels based on the Rth of the at least P first sampled signals and the Rth of the at least Q second sampled signals comprises:

determining that the phase of the signal output from the end of the first digital channel is one clock cycle earlier than the phase of the signal output from the end of the second digital channel in the case that the binary value obtained by shifting the binary value of the first R-th sampling signal by one bit to the right is the same as the binary value of the second R-th sampling signal;

determining that the phase of the signal output by the end of the first digital channel is one clock cycle later than the phase of the signal output by the end of the second digital channel in the case that the binary value obtained by shifting the binary value of the R-th first sampling signal by one bit to the left is the same as the binary value of the R-th second sampling signal;

and under the condition that the binary value of the R-th first sampling signal is the same as that of the R-th second sampling signal, determining that the phase of the signal output by the end of the first digital channel and the phase of the signal output by the end of the second digital channel are in the same clock cycle.

5. The method according to claim 4, wherein the binary values of the R-th first sampling signal are determined by the corresponding sampling values of all the sampling points in the R-th first sampling signal, and the binary values of the R-th second sampling signal are determined by the corresponding sampling values of all the sampling points in the R-th second sampling signal.

6. The delay skew measurement method of a digital channel according to claim 5,

the binary value of the R-th first sampling signal is determined by the sampling values corresponding to the continuous partial sampling points in the R-th first sampling signal, and the binary value of the R-th second sampling signal is determined by the sampling values corresponding to the continuous partial sampling points in the R-th second sampling signal;

wherein the positions of consecutive partial sampling points in the R-th first sampling signal and consecutive partial sampling points in the R-th second sampling signal correspond to each other, and neither a binary value of the R-th first sampling signal nor a binary value of the R-th second sampling signal is equal to zero.

7. The method of claim 6, wherein determining the phase deviation values of the signals output by the ends of the first and second digital channels based on the phase relationship of the signals output by the ends of the first and second digital channels and the number of the first predetermined clock cycles comprises:

and the phase deviation value of the output signals at the tail ends of the first digital channel and the second digital channel is equal to the product of the representative value of the phase relation of the signals output at the tail ends of the first digital channel and the second digital channel and the clock period, and is added with the product of the number of the first preset clock periods and the first preset clock period.

8. The delay skew measurement method of a digital channel according to claim 7,

if the phase relationship of the signals output by the first digital channel and the second digital channel is that the phase of the signal output by the first digital channel is earlier than the phase of the signal output by the second digital channel by one clock cycle, the representative value of the phase relationship of the signals output by the first digital channel and the second digital channel is 1;

if the phase relation of the signals output by the first digital channel and the second digital channel is that the phase of the signal output by the first digital channel is later than that of the signal output by the second digital channel by one clock cycle, the representative value of the phase relation of the signals output by the first digital channel and the second digital channel is-1;

if the phase relationship between the signals at the ends of the first digital channel and the second digital channel is that the phase of the signal output at the end of the first digital channel and the phase of the signal output at the end of the second digital channel are in the same clock cycle, then the representative value of the phase relationship between the signals output at the ends of the first digital channel and the second digital channel is 0.

9. A delay skew measuring apparatus for a digital channel, comprising:

the signal sending module to be tested: the system comprises a first digital channel to be tested, a second digital channel to be tested, a first digital signal processing module, a second digital signal processing module and a second digital signal processing module, wherein the first digital channel and the second digital channel to be tested are used for synchronously sending a preset periodic waveform signal from head ends of the first digital channel and the second digital channel to be tested;

a clock cycle acquisition module: the clock signal acquisition unit is used for acquiring N clock signals, and the phase of the latter clock signal in the N clock signals is delayed by a first preset clock period compared with the phase of the former clock signal;

a first sampled signal sampling module: the digital signal processing circuit is used for obtaining at least P first sampling signals by sampling at the tail end of the first digital channel respectively based on the rising edges of at least the first P clock signals in the N clock signals, wherein the P-th first sampling signal in the at least P first sampling signals is an all-zero signal;

the second sampling signal sampling module: the second sampling circuit is used for sampling at the tail end of the second digital channel to obtain at least Q second sampling signals respectively based on the rising edge of at least the first Q clock signals in the N clock signals, wherein the Q second sampling signal in the at least Q second sampling signals is an all-zero signal;

a deviation value calculation module: and the phase deviation value of the signals output by the tail ends of the first digital channel and the second digital channel is determined based on the at least P first sampling signals and the at least Q second sampling signals, wherein N, P and Q are all positive integers which are larger than equal to 3.

10. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and the processor is configured to execute the computer program to perform the delay skew measurement method of any of claims 1 to 8.