CN113630296A - Automatic LVDS transmission delay window testing method and system - Google Patents
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Abstract
The invention relates to an automatic testing method and system for an LVDS transmission delay window, which is applied to a server side and comprises the following steps: s11, acquiring initial value data transmitted by a user on the LVDS data line; s12, obtaining final data corresponding to the delay value, and comparing the final data with the initial value data to obtain an optimal delay value; and S13, receiving the optimal delay value, and switching to a normal LVDS transmission mode. According to the invention, the initial value data of the LVDS is obtained, the final data corresponding to the delay value is compared with the initial value data to obtain the optimal delay value, and the LVDS transmission mode is switched under the condition of the optimal delay value, so that the LVDS data is correctly received.
Description
Technical Field
The invention relates to the technical field of high-speed LVDS data transmission in a digital transceiving system, in particular to an automatic testing method and system for an LVDS transmission delay window.
Background
In most current high-speed circuit designs, LVDS is often chosen as the interface between the data converter and the FPGA. The differential transmission characteristic of the LVDS can effectively inhibit common-mode noise and increase the anti-interference capability. With the increase of data rate, the time window for multi-bit data synchronous reception becomes smaller, and how to ensure the correct reception of multi-channel data becomes a design difficulty. In order to reduce the difficulty, at present, an ADC device generally adopts a serial manner, and uses fewer data lines to complete transmission of multi-bit sampling data.
The sampling data in the digital receiving and transmitting system is transmitted through a plurality of pairs of LVDS differential lines, is simultaneously latched at a receiving end, and is recovered after serial-parallel conversion and data rearrangement. Typically, the ADC chip will output a high-speed data synchronization clock and a frame clock for data latching, serial-to-parallel conversion, and decoding. The receiving end latches the data on all the signal lines at the same time, and in order to ensure that the receiving end can correctly obtain the data, the delay of each transmission line is required to be the same as much as possible. To ensure consistent transmission line delays, equal length constraints on all data lines and frame clock routing in the PCB are required. Due to the precision limitation of the plate making and welding processes, the delay of the data lines on the circuit board still has differences, and at the moment, the signal delay needs to be adjusted in the FPGA to ensure the integrity of the time sequence.
Because the delay of the data line is different between each circuit board, the delay of the data line on the circuit board is different at different temperatures and under different use environments, the method of manually adjusting the delay is not practical when the circuit board is powered on for use every time, and data cannot be correctly received.
The invention patent application with the application number of 'CN 202011065254.3' discloses a multi-path LVDS data processing device and a method, wherein an introduced external synchronous clock is changed into a sampling clock with dynamically configurable phase of multi-path LVDS data; acquiring multi-path low voltage differential signal LVDS data according to a sampling clock, and synchronizing the multi-path LVDS data; the synchronized multi-path LVDS data are transmitted, processed and buffered, the synchronous clock phase in the whole period can be dynamically configured to obtain the optimal phase value, the scheme acquires multi-path signals through the sampling clock, and the delay of data lines between each circuit board is different, so that the data of the scheme cannot be correctly received.
Disclosure of Invention
The invention aims to provide an automatic testing method and system for an LVDS transmission delay window, so as to solve the problem that LVDS data cannot be correctly received during transmission.
The invention solves the technical problems through the following technical means: an automatic LVDS transmission delay window testing method is applied to a server side and comprises the following steps:
s11, acquiring initial value data transmitted by a user on the LVDS data line;
s12, obtaining final data corresponding to the delay value, and comparing the final data with the initial value data to obtain an optimal delay value, specifically including:
s121, obtaining a delay window by adjusting the delay of a data synchronization clock in an IODELAY module in the FPGA, wherein the xth delay value is x in N delay values contained in the delay window, and the system acquires final data corresponding to the x value at the moment;
s122, sequentially judging whether the final data is consistent with the initial value data, wherein each bit of data in the initial value data is sequentially changed in an alternating mode, each delay window comprises N delay values, the sequentially corresponding data transmission conditions are counted by using N-bit binary numbers and sequentially correspond to the 0 th bit, the 1 st bit and the 2 nd bit … (N-1) th bit, N is a positive integer, in the N delay values, sequentially corresponding to the x-th bit according to the delay value, judging whether the final data is consistent with the initial value data, if so, setting the x-th bit to be 0, and if not, setting the x-th bit to be 1, and x is a positive integer;
and S13, receiving the optimal delay value, and switching to a normal LVDS transmission mode.
According to the invention, the initial value data of the LVDS is obtained, the final data corresponding to the delay value is compared with the initial value data to obtain the optimal delay value, the LVDS transmission mode is automatically switched under the condition of the optimal delay value, the accurate receiving of the LVDS data is realized, the problem that the data cannot be normally received due to the delay difference of LVDS transmission data lines in a circuit board is solved, and the debugging and testing time of the circuit board is reduced.
As a further improved technical solution, in step S11, the server selects the LVDS automatic test mode by default when powering on.
As a further improved technical solution, in step S121, a delay window is obtained by adjusting the delay of the data synchronization clock through an IODELAY module in the FPGA.
As a further improved technical solution, in step S13, an optimal delay value is detected, and the system automatically fills the optimal delay value into the system.
As a further improved technical scheme, the method is suitable for AD chip testing.
As a further improved solution, each delay value represents a delay time of 78ps, and the delay time is a delay value of 78 ps.
The invention also provides an automatic LVDS transmission delay window testing system, which is applied to a server side and comprises:
the initial value module is used for acquiring initial value data transmitted by a user on the LVDS data line;
the delay value module is used for acquiring final data corresponding to the delay value and comparing the final data with the initial value data to acquire an optimal delay value, and specifically comprises the following units:
the delay window unit is used for adjusting the delay of the data synchronization clock through the FPGA to obtain a delay window, wherein the xth delay value is x in N delay values contained in the delay window, and the system acquires final data corresponding to the x value at the moment;
the judging unit is used for sequentially judging whether the final data is consistent with the initial value data, each bit of data in the initial value data is sequentially and alternately changed, each delay window comprises N delay values, the sequentially corresponding data transmission conditions are counted by N-bit binary numbers and sequentially comprise the 0 th bit, the 1 st bit and the 2 nd bit … (N-1 st bit), N is a positive integer, in the N delay values, the x is sequentially corresponding to the x according to the delay value, whether the final data is consistent with the initial value data is judged, if so, the x is set to be 0, and if not, the x is set to be 1 and the x is a positive integer;
and the switching module is used for optimizing the delay value and switching to a normal LVDS transmission mode.
As a further improved technical scheme, in the initial value module, the server defaults to select the LVDS automatic test mode when the power is on.
As a further improved technical solution, in the switching module, the optimal delay value is detected, and the system automatically fills the optimal delay value into the system.
As a further improved technical solution, in the delay window unit, the delay of the data synchronization clock is adjusted by the IODELAY module in the FPGA to obtain a delay window, each delay value represents that the delay time is 78ps, and the delay time is 78 ps.
The invention has the advantages that:
1. according to the invention, the initial value data of the LVDS is obtained, the final data corresponding to the delay value is compared with the initial value data to obtain the optimal delay value, and the LVDS transmission mode is switched under the condition of the optimal delay value, so that the LVDS data is correctly received.
2. The invention realizes the automatic test of the LVDS transmission delay window, selects the optimal delay value and realizes the correct receiving of multi-channel LVDS data; meanwhile, the transmission delay window is subjected to power-on automatic test, the delay window can be automatically captured in different use environments, an optimal delay value is found, and the problem that data cannot be correctly received due to the delay difference of data lines of different circuit boards at different temperatures and in different use environments is solved.
3. In the invention, each bit of data in the initial value data is sequentially changed alternately, and the error of the alternately changed data is easy to find, so that the influence of different delays on the correctness of the received final data can be identified better.
Drawings
Fig. 1 is a block diagram illustrating a flow of an automatic LVDS transmission delay window testing method according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of an LVDS transmission delay window automatic test system according to an embodiment of the present invention.
Fig. 3 is a flowchart of an automatic delay window testing method for LVDS transmission according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 1 and fig. 3, fig. 1 is a schematic flow block diagram of an LVDS transmission delay window automatic test method according to an embodiment of the present invention, and fig. 3 is a flow diagram of a delay window automatic test method according to an embodiment of the present invention, where the method is applied to a server side and includes the following steps:
s11, acquiring initial value data transmitted by a user on the LVDS data line;
the method comprises the steps of firstly powering on, selecting an LVDS automatic test mode by default by a server, and obtaining an initial value by the server, wherein the initial value is obtained by self definition on an LVDS data line.
S12, obtaining final data corresponding to the delay value, and comparing the final data with the initial value data to obtain an optimal delay value;
s121, adjusting the delay of the data synchronization clock through the FPGA to obtain a delay window, wherein the delay value of the xth delay value is x in N delay values contained in the delay window, and at the moment, the system acquires final data corresponding to the x value;
and S122, sequentially judging whether the final data is consistent with the initial value data or not, and counting the corresponding judgment result by using an N-bit binary number. If the delay value x is consistent, the x-th bit corresponding to the delay value x is set to be 0, and if the delay value x is inconsistent, the x-th bit is set to be 1.
Specifically, in the step, a delay window is obtained by adjusting the delay of the data synchronization clock through an IODELAY module in the FPGA, each delay window includes N delay values, and the data transmission conditions corresponding in sequence are counted by using N-bit binary numbers. The data are sequentially the 0 th bit, the 1 st bit and the 2 nd bit … (the N is a positive integer), in the N delay values, the x-th bit is corresponding to the x-th bit according to the delay value x, whether the final data and the initial value data are consistent or not is judged, if so, the x-th bit is set to be 0, and if not, the x-th bit is set to be 1.
Wherein N is any positive integer, N is 32 in the scheme of the embodiment of the present disclosure, and x is also a positive integer not greater than N.
Furthermore, each delay value represents a delay time of 78ps, and the delay time is a delay value of 78ps, for example:
if the delay value is 0, it represents a delay time of 0ps, if the delay value is 1, it represents a delay time of 78ps, and if the delay value is 2, it represents a delay time of 156 ps.
It should be noted that the initial value data is data that is transmitted at the beginning of LVDS data, in order to ensure accuracy, each bit of data in the initial value data is sequentially and alternately changed, and the alternately changed data is easy to be found out by error, which can better identify the influence of different delays on whether the received final data is correct or not, for example, when the first bit in the initial value data is 0, the second bit is 1.
The final data is data finally acquired by the LVDS transmission system.
For a more convenient understanding of the present embodiment, the following description is given by way of example.
In the scheme of the embodiment of the disclosure, the data transmission condition is counted by 0 and 1, wherein 0 represents that the final data is consistent with the initial value data, and 1 represents that the final data is inconsistent with the initial value data. And counting the data transmission conditions corresponding to the 32 delay values by using 32-bit binary numbers. That is, if the delay value is 0, it is determined whether the final data and the initial value data match, and if they match, 0 is indicated at the corresponding position, and if they do not match, 1 is indicated at the corresponding position.
For example:
the delay value is 0, whether the final data and the initial value data are consistent or not is judged, if so, the 0 th bit mark is 0, and if not, the 0 th bit mark is 1;
the delay value is 1, whether the final data and the initial value data are consistent or not is judged, if so, the 1 st bit is labeled with 0, and if not, the 1 st bit is labeled with 1;
the delay value is 2, whether the final data and the initial value data are consistent or not is judged, if so, the 2 nd bit mark is 0, and if not, the 2 nd bit mark is 1;
and sequentially detecting whether the final data corresponding to each delay value is consistent with the initial value data from 0 to 31 according to the scheme, marking the final data with 0 and 1, and finally marking out 32-bit numbers.
And finding the window with the maximum continuous label 0, and then finding the intermediate value of the window, wherein the delay value corresponding to the intermediate value is the optimal value. The window marked 001111110111111100000001 shows that the most consecutive 0's have the first bit to the seventh bit, and the window has the optimal delay value of 4.
And S13, receiving the optimal delay value, and switching to a normal LVDS transmission mode.
And when the optimal delay value is detected, the system automatically fills the optimal delay value into the system, namely the automatic test of the LVDS delay window and the selection of the optimal value of the LVDS delay are completed.
It should be noted that the scheme of the embodiment of the present disclosure is applicable to all LVDS transmission delay window tests, and is also applicable to an AD chip but not limited to the AD chip.
Example 2
Referring to fig. 2, fig. 2 is a schematic structural diagram of an LVDS transmission delay window automatic testing system according to an embodiment of the present invention, where the system is mainly applied to a server side, and includes:
the initial value module is used for acquiring initial value data transmitted by a user on the LVDS data line;
the method comprises the steps of firstly powering on, selecting an LVDS automatic test mode by default by a server, and obtaining an initial value by the server, wherein the initial value is obtained by self definition on an LVDS data line.
The delay value module is used for acquiring final data corresponding to the delay value and comparing the final data with the initial value data to acquire an optimal delay value; and is also used for:
s121, adjusting the delay of the data synchronization clock through the FPGA to obtain a delay window, wherein the delay value of the xth delay value is x in N delay values contained in the delay window, and at the moment, the system acquires final data corresponding to the x value;
and S122, sequentially judging whether the final data is consistent with the initial value data or not, and counting by using an N-bit binary number corresponding to the judgment result. If the delay value is consistent with the x, the x-th bit corresponding to the delay value x is set to be 0, if the delay value is not consistent with the x, the x-th bit is set to be 1, and x is a positive integer.
Specifically, in the step, a delay window is obtained by adjusting the delay of the data synchronization clock through an IODELAY module in the FPGA, each delay window includes N delay values, and the data transmission conditions corresponding in sequence are counted by using N-bit binary numbers. The data are sequentially the 0 th bit, the 1 st bit and the 2 nd bit … (the N is a positive integer), in the N delay values, the x-th bit is corresponding to the x-th bit according to the delay value x, whether the final data and the initial value data are consistent or not is judged, if so, the x-th bit is set to be 0, and if not, the x-th bit is set to be 1.
Wherein N is any positive integer, N is 32 in the scheme of the embodiment of the present disclosure, and x is also a positive integer not greater than N.
Furthermore, each delay value represents a delay time of 78ps, and the delay time is a delay value of 78ps, for example:
if the delay value is 0, it represents a delay time of 0ps, if the delay value is 1, it represents a delay time of 78ps, and if the delay value is 2, it represents a delay time of 156 ps.
It should be noted that the initial value data is data that is transmitted at the beginning of LVDS data, in order to ensure accuracy, each bit of data in the initial value data is sequentially and alternately changed, and the alternately changed data is easy to be found out by error, which can better identify the influence of different delays on whether the received final data is correct or not, for example, when the first bit in the initial value data is 0, the second bit is 1.
The final data is data finally acquired by the LVDS transmission system.
For a more convenient understanding of the present embodiment, the following description is given by way of example.
In the scheme of the embodiment of the disclosure, the data transmission condition is counted by 0 and 1, wherein 0 represents that the final data is consistent with the initial value data, and 1 represents that the final data is inconsistent with the initial value data. And counting the data transmission conditions corresponding to the 32 delay values by using 32-bit binary numbers. That is, if the delay value is 0, it is determined whether the final data and the initial value data match, and if they match, 0 is indicated at the corresponding position, and if they do not match, 1 is indicated at the corresponding position.
For example:
the delay value is 0, whether the final data and the initial value data are consistent or not is judged, if so, the 0 th bit mark is 0, and if not, the 0 th bit mark is 1;
the delay value is 1, whether the final data and the initial value data are consistent or not is judged, if so, the 1 st bit is labeled with 0, and if not, the 1 st bit is labeled with 1;
the delay value is 2, whether the final data and the initial value data are consistent or not is judged, if so, the 2 nd bit mark is 0, and if not, the 2 nd bit mark is 1;
and sequentially detecting whether the final data corresponding to each delay value is consistent with the initial value data from 0 to 31 according to the scheme, marking the final data with 0 and 1, and finally marking out 32-bit numbers.
And finding the window with the maximum continuous label 0, and then finding the intermediate value of the window, wherein the delay value corresponding to the intermediate value is the optimal value. The window marked 001111110111111100000001 shows that the most consecutive 0's have the first bit to the seventh bit, and the window has the optimal delay value of 4.
And the switching module is used for optimizing the delay value and switching to a normal LVDS transmission mode.
And when the optimal delay value is detected, the system automatically fills the optimal delay value into the system, namely the automatic test of the LVDS delay window and the selection of the optimal value of the LVDS delay are completed.
It should be noted that the scheme of the embodiment of the present disclosure is applicable to all LVDS transmission delay window tests, and is also applicable to an AD chip but not limited to the AD chip.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. An automatic LVDS transmission delay window testing method is applied to a server side and is characterized by comprising the following steps:
s11, acquiring initial value data transmitted by a user on the LVDS data line;
s12, obtaining final data corresponding to the delay value, and comparing the final data with the initial value data to obtain an optimal delay value, specifically including:
s121, adjusting the delay of the data synchronization clock through the FPGA to obtain a delay window, wherein the xth delay value is x in N delay values contained in the delay window, and at the moment, the system acquires final data corresponding to the x value;
s122, sequentially judging whether the final data is consistent with the initial value data, wherein each bit of data in the initial value data is sequentially changed in an alternating mode, each delay window comprises N delay values, the sequentially corresponding data transmission conditions are counted by using N-bit binary numbers and sequentially correspond to the 0 th bit, the 1 st bit and the 2 nd bit … (N-1) th bit, N is a positive integer, in the N delay values, sequentially corresponding to the x-th bit according to the delay value, judging whether the final data is consistent with the initial value data, if so, setting the x-th bit to be 0, and if not, setting the x-th bit to be 1, and x is a positive integer;
and S13, receiving the optimal delay value, and switching to a normal LVDS transmission mode.
2. The LVDS transmission delay window automatic test method according to claim 1, wherein in step S11, the server selects the LVDS automatic test mode by default at power-up.
3. The LVDS transmission delay window automatic test method according to claim 2, wherein in step S121, the delay window is obtained by adjusting a delay of the data synchronization clock through an IODELAY module in the FPGA.
4. The LVDS transmission delay window automatic test method according to claim 1, wherein in the step S13, an optimal delay value is detected, and the system automatically fills the optimal delay value into the system.
5. The LVDS transmission delay window automatic test method according to claim 1, wherein the method is adapted to AD chip testing.
6. The LVDS transmission delay window automatic test method of claim 7, wherein each delay value represents a delay time of 78ps, and the delay time is a delay value x 78 ps.
7. An automatic LVDS transmission delay window testing system is applied to a server side and is characterized by comprising:
the initial value module is used for acquiring initial value data transmitted by a user on the LVDS data line;
the delay value module is used for acquiring final data corresponding to the delay value and comparing the final data with the initial value data to acquire an optimal delay value, and specifically comprises the following units:
the delay window unit is used for adjusting the delay of the data synchronization clock through the FPGA to obtain a delay window, wherein the xth delay value is x in N delay values contained in the delay window, and the system acquires final data corresponding to the x value at the moment;
the judging unit is used for sequentially judging whether the final data is consistent with the initial value data, each bit of data in the initial value data is sequentially and alternately changed, each delay window comprises N delay values, the sequentially corresponding data transmission conditions are counted by N-bit binary numbers and sequentially comprise the 0 th bit, the 1 st bit and the 2 nd bit … (N-1 st bit), N is a positive integer, in the N delay values, the x is sequentially corresponding to the x according to the delay value, whether the final data is consistent with the initial value data is judged, if so, the x is set to be 0, and if not, the x is set to be 1 and the x is a positive integer;
and the switching module is used for optimizing the delay value and switching to a normal LVDS transmission mode.
8. The LVDS transmission delay window automatic test system of claim 7, wherein in the initial value module, the server defaults to select the LVDS automatic test mode when being powered on.
9. The LVDS transmission delay window automatic test system of claim 7, wherein in the switching module, an optimal delay value is detected, and the system automatically fills the optimal delay value into the system.
10. The LVDS transmission delay window automatic test system according to claim 7, wherein the delay window unit adjusts a delay of the data synchronization clock by an IODELAY module in the FPGA to obtain the delay window, each delay value representing a delay time of 78ps and the delay time being a delay value x 78 ps.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114896186A (en) * | 2022-05-23 | 2022-08-12 | 北京计算机技术及应用研究所 | FPGA and external bus data interaction method based on pre-training |
| CN117389817A (en) * | 2023-12-11 | 2024-01-12 | 杭州海康威视数字技术股份有限公司 | Data transmission system and delay value automatic acquisition method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102890663A (en) * | 2011-07-21 | 2013-01-23 | 中兴通讯股份有限公司 | Data transmitting method and time delay module |
| CN106959934A (en) * | 2017-02-21 | 2017-07-18 | 深圳市紫光同创电子有限公司 | Low-voltage differential signal receiving interface and low-voltage differential signal method of reseptance |
-
2021
- 2021-08-31 CN CN202111013651.0A patent/CN113630296A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102890663A (en) * | 2011-07-21 | 2013-01-23 | 中兴通讯股份有限公司 | Data transmitting method and time delay module |
| CN106959934A (en) * | 2017-02-21 | 2017-07-18 | 深圳市紫光同创电子有限公司 | Low-voltage differential signal receiving interface and low-voltage differential signal method of reseptance |
Non-Patent Citations (1)
| Title |
|---|
| 龚华达等: "基于FPGA的高速多路LVDS差分总线组传输技术", 《光通信技术》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114896186A (en) * | 2022-05-23 | 2022-08-12 | 北京计算机技术及应用研究所 | FPGA and external bus data interaction method based on pre-training |
| CN114896186B (en) * | 2022-05-23 | 2023-09-26 | 北京计算机技术及应用研究所 | Pre-training-based FPGA and external bus data interaction method |
| CN117389817A (en) * | 2023-12-11 | 2024-01-12 | 杭州海康威视数字技术股份有限公司 | Data transmission system and delay value automatic acquisition method |
| CN117389817B (en) * | 2023-12-11 | 2024-04-02 | 杭州海康威视数字技术股份有限公司 | Data transmission system and delay value automatic acquisition method |
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Application publication date: 20211109 |