CN114896186A - FPGA and external bus data interaction method based on pre-training - Google Patents

Abstract

The invention relates to a pre-training-based FPGA and external bus data interaction method, and belongs to the technical field of information. The invention considers the influence of the FPGA on the transmission delay of the chip circuit under different working temperatures, layout and wiring and other environmental conditions, and carries out parallel search on the optimal delay parameter of the current bus based on the iterative use of a coarse lookup table and a fine lookup table. Compared with a conventional FPGA and external bus data interaction method, the pre-training-based FPGA and external bus data interaction mechanism improves the communication reliability of the FPGA and the external bus and reduces the error rate of the FPGA and the external bus. Meanwhile, the method has good adaptability, can generally adapt to buses with different interface rates, and quickly and accurately searches the optimal delay value of the current bus by self-adaptive selection of a rough and fine search table.

Description

FPGA and external bus data interaction method based on pre-training

Technical Field

The invention belongs to the technical field of information, and particularly relates to a pre-training-based FPGA and external bus data interaction method.

Background

With the rapid development of high-performance embedded systems, the interaction speed between the FPGA and the bus is also continuously increased. High speed bus technology inherently has higher transfer rates, better signal integrity, and is more conducive to miniaturized designs. Therefore, the method is widely applied to the aspects of signal acquisition, high-speed transmission, video monitoring and the like.

Under the ideal condition, when the FPGA carries out data interaction with an external bus, the data is sampled by a certain clock change edge, and the clock change edge is just in the middle of the data. However, when the actual FPGA interacts with an external data bus at a high speed, factors such as layout and wiring of the FPGA, working temperature and the like can cause different changes in delay of a chip circuit, so that a timing margin of the FPGA is reduced, and a deviation between a clock and data is caused in many cases.

At present, research aiming at improving the synchronization problem in the interaction process of the FPGA and the external bus mainly focuses on three aspects:

in hardware aspect, most of the existing methods for improving the data interaction quality between the FPGA and the external bus in engineering adopt equal-length processing during wiring on a PCB, so that the same time delay of different signals before entering the FPGA is ensured. However, high-speed data transmission often has high requirements on hardware, both chip interfaces and PCB wiring affect data transmission quality, and the method has poor portability, flexibility and adaptive capacity, and each set of different hardware needs to be subjected to corresponding layout and wiring again, which consumes manpower and material resources and increases production cost.

In the aspect of FPGA time sequence: embedded high-speed serial bus technology published in 2017: based on FPGA implementation and application, in Zhang Feng from page 63 to page 64, timing optimization by using OFFSET constraint, MAXSKEW constraint and the like in FPGA is mentioned. The method can restrict the relative phase relation between the sampling clock in the FPGA and the data, and the sampling clock is just in the middle of the data. However, the constraint value in this method does not have the capability of adaptive adjustment and needs to be calculated reasonably. Unreasonable constraint values may cause the FPGA to increase the PAR (Place and Route) time length, and even cause PAR failure.

The logic aspect of the FPGA: in the 'low-delay high-speed interface implementation method based on FPGA primitive' published by Nianzhixin, Wangjiang and the like from pages 99 to 101 in 'microcomputer application' of No. 5, volume 37 in 2021, a method for building a PHY interface capable of dynamically changing output delay by using FPGA primitives such as IOBUF, IODELAY and the like is provided. The IODELAY is used to adjust the timing problem caused by different hardware trace delays. The method effectively reduces interface delay, has good effect on the application requiring small delay and tense time sequence, and has a certain degree of self-adaptability. However, the adaptive modulation capability is limited, only the dynamic delay modulation within a small range can be realized, and the synchronization problem of buses with different rates in the communication process cannot be considered.

In summary, none of the existing methods completely solves the synchronization problem of the buses with different rates in the process of communicating with the FPGA.

Disclosure of Invention

Technical problem to be solved

The invention aims to solve the technical problem of how to provide a pre-training-based FPGA and external bus data interaction method so as to solve the synchronization problem of buses with different rates in the process of communicating with an FPGA.

(II) technical scheme

In order to solve the technical problem, the invention provides a pre-training-based FPGA and external bus data interaction method, which comprises the following steps:

step 1, two lookup tables related to delay parameters are stored in an FPGA in advance, wherein one lookup table is a rough lookup table and is used for rough search in a low-speed bus in advance, the other lookup table is a fine lookup table and is used for searching the optimal delay of the high-speed bus, or the other lookup table is used for further detailed search on the basis of the rough search in the low-speed bus, the search step is delta, and the search steps of the rough lookup table and the fine lookup table are different;

step 2, under the initial condition that time delay is not carried out, namely the time delay parameter n is 0, firstly enabling the FPGA and an external bus to carry out transmission of a section of known training sequence, and observing the interaction condition of the known training sequence; if the communication error state is in the beginning, turning to the step 3; if the communication is in the normal communication state, turning to the step 4;

and 3, when the communication between the FPGA and the external bus is in an error state, adopting a search strategy 1: setting a lookup range of a lookup table as [ -clk, clk ], wherein clk is an interface operating frequency, starting from the middle position of the lookup table, namely, a delay parameter n is 0, dividing the lookup table into two paths of parallel search in the front direction and the rear direction of the lookup table simultaneously, namely, searching the delay parameter in the sequence of n ═ Δ, n ═ 2 Δ, and n ═ 2 Δ.. the delay parameter; when a delay parameter is searched, corresponding delay is carried out on data or a clock;

when one path detects normal interactive data, the path stops searching, records the delay parameter in the current lookup table as D1; the other path starts to search from the tail end of the lookup table in the direction of D1, stops after finding the time delay which just can be interacted normally, records the time delay parameter in the current lookup table and records as D2; d1 and D2 are distances between the front and back boundary positions of the data and the current sampling clock edge;

if the current communication bus is a high-speed bus, the search strategy 1 adopts a fine-checking table to directly determine the optimal delay parameter; if the current communication bus is a low-speed bus, the search strategy 1 adopts a rough lookup table, the boundary position of the data needs to be accurately confirmed by further utilizing a fine lookup table, and the step 5 is carried out;

and 4, when the communication between the FPGA and the external bus is in a normal state, adopting a search strategy 2: setting a lookup range of a lookup table as [ -clk, clk ], starting from a middle position of the lookup table, namely when a delay parameter is n ═ 0, dividing the lookup table into two paths, and simultaneously searching the two paths in parallel in the front direction and the rear direction of the lookup table, namely searching the delay parameters in the sequence of n ═ Δ, n ═ 2 Δ, and n ═ 2 Δ.. once a delay parameter is searched, and correspondingly delaying data or a clock each time when a delay parameter is searched;

when one path detects that the interaction between the FPGA and the external bus is wrong, the path stops searching, records the delay parameter in the current lookup table and records the delay parameter as D1; the other path is searched continuously, the other path is stopped after the delay with the interaction error is found out, and the delay parameter in the current lookup table is recorded as D2;

if the current communication bus is a high-speed bus, the search strategy 2 adopts a detailed lookup table to directly determine the optimal delay value; if the current communication bus is a low-speed bus, the search strategy 2 adopts a rough lookup table, the boundary position of the data needs to be accurately confirmed by further utilizing a fine lookup table, and the step 5 is carried out;

and 5, when the coarse lookup table confirms that D1 is a data boundary position, adopting a search strategy 3: setting the search range of the fine search table as [ D1-5ns, D1+5ns ], dividing the search range from D1 into two paths, and simultaneously searching in parallel in the front direction and the rear direction of the search table, namely searching the delay parameters in the sequence of n ═ D1+ delta, n ═ D1-delta, n ═ D1+2 delta, and n ═ D1-2 delta.; when a delay parameter is searched, corresponding delay is carried out on data or a clock;

when the change of the data interaction condition is detected, stopping two-way searching, recording the delay parameter in the current lookup table as d 1;

when the coarse lookup table confirms that D2 is another boundary location of the data, search strategy 3 is also employed: setting the search range of the fine search table as [ D2-5ns, D2+5ns ], dividing the search range from D2 into two paths, and simultaneously searching in parallel in the front direction and the rear direction of the search table, namely searching the delay parameters in the sequence of n ═ D2+ delta, n ═ D2-delta, n ═ D2+2 delta, and n ═ D2-2 delta.; when a delay parameter is searched, corresponding delay is carried out on data or a clock;

when the change of the data interaction condition is detected, stopping two-way searching, recording the delay parameter in the current lookup table as d 2;

calculating the optimal delay value of the bus according to d1 and d 2;

and 6, after the optimal delay value is determined, the FPGA carries out corresponding delay on the data or the clock according to the optimal delay value, and then carries out transmission of subsequent effective data.

Furthermore, the low-speed bus is a bus with the interface working frequency not more than 100MHz, and the high-speed bus is a bus with the interface working frequency more than 100 MHz.

Further, the search step of the rough lookup table is Δ ═ 5ns, and the search step of the fine lookup table is Δ ═ 78 ps.

Further, when the fine lookup is carried out in the low-speed bus, the lookup range of the fine lookup table is [ D-5ns, D +5ns ], wherein D is the rough lookup result of the rough lookup table; when the optimal delay search is performed in the high-speed bus, the search range of the scrutiny table is [ -clk, clk ].

Furthermore, the FPGA carries out corresponding time delay on data and a clock according to the currently searched time delay parameter n, wherein n is a real number, and observes the data interaction condition; the specific delay operation is as follows: when the delay parameter is that the positive number n is larger than 0, delaying the clock backward by n ns or ps; when the delay parameter is negative n < 0, then the data is delayed back by | n | ns or ps.

Further, in step S2, if the external bus is a parallel bus, directly comparing whether the received data is consistent with the known training sequence, and if there are more than 4 consecutive bytes consistent with the training sequence, it is determined that the communication between the current FPGA and the external parallel bus is in a normal state, otherwise, it is in an error state; if the external bus is a serial bus, performing serial-parallel conversion immediately after receiving data, comparing the converted received data with a known training sequence to observe whether the received data is consistent with the known training sequence, and if the received data is consistent with the known training sequence, determining that the communication between the FPGA and the external serial bus is in a normal state, otherwise, determining that the communication is in an error state.

Further, in step S3, if the current communication bus is a high-speed bus, the search strategy 1 uses a fine search table, and after the data boundary values D1 and D2 are obtained by searching, a delay value delay _ h between the optimal sampling position at the intermediate position of the data and the current sampling clock edge is calculated by using the fine search table, and the delay value delay _ h is recorded as an optimal delay value;

|D2|＞|D1|＞0,|delay_h|＞0

if the current communication bus is a low-speed bus, the search strategy 1 adopts a rough lookup table, and after the data boundary values D1 and D2 are obtained through searching, the boundary position of the data needs to be accurately confirmed by further using a fine lookup table, and the process goes to step 5.

Further, in the step S4,

if the current communication bus is a high-speed bus, the search strategy 2 adopts a fine-search table, and after the data boundary values D1 and D2 are obtained through searching, the delay value delay _ h between the optimal sampling position at the data intermediate position and the current sampling point is calculated by using the fine-search table and is recorded as the optimal delay value;

|D2|≥|D1|＞0,delay_h∈R

if the current communication bus is a low-speed bus, the search strategy 2 adopts a rough lookup table, and after the data boundary values D1 and D2 are obtained through searching, the boundary position of the data needs to be accurately confirmed by further using a fine lookup table, and the process goes to step 5.

Further, in the step S5, the interaction status changes to that the interaction state changes from normal to error, or from error to normal; the method for calculating the optimal delay value of the bus according to d1 and d2 comprises the following steps:

calculating a delay value delay _ l between the optimal sampling position at the data intermediate position and the current sampling point, and recording the delay value delay _ l as the optimal delay value of the bus;

|d2|≥|d1|＞0,delay_l∈R。

further, the delay operation in step S6 is as follows:

when the current optimal delay value is a positive number, namely delay is greater than 0, the clock is delayed backward by delay ns or ps;

when the current optimal delay value is negative, i.e. delay < 0, the data is delayed backwards by | delay | ns or ps.

(III) advantageous effects

The invention provides a pre-training-based FPGA and external bus data interaction method, which considers the influence of the FPGA on the transmission delay of a chip circuit under different working temperatures, layout and wiring and other environmental conditions, and carries out parallel search on the optimal delay parameter of the current bus based on iterative use of a coarse lookup table and a fine lookup table. Compared with a conventional FPGA and external bus data interaction method, the pre-training-based FPGA and external bus data interaction mechanism improves the communication reliability of the FPGA and the external bus and reduces the error rate of the FPGA and the external bus. Meanwhile, the method has good adaptability, can generally adapt to buses with different interface rates, and quickly and accurately searches the optimal delay value of the current bus by self-adaptive selection of a rough and fine search table.

Drawings

FIG. 1 is a schematic diagram illustrating a pre-trained FPGA-based external bus data interaction process according to the present invention;

FIG. 2 is a schematic diagram of the delay adjustment of the high-speed bus in the case of an initial communication error according to the present invention;

FIG. 3 is a schematic diagram of the delay adjustment of the high-speed bus under the normal condition of initial communication according to the present invention;

FIG. 4 is a schematic diagram of the delay adjustment of the low-speed bus in the case of an initial communication error according to the present invention;

FIG. 5 is a schematic diagram of a fine lookup table search for a low speed bus in the case of an initial communication error according to the present invention;

FIG. 6 is a schematic diagram of the delay adjustment of the low-speed bus under the normal condition of the initial communication according to the present invention;

FIG. 7 is a schematic diagram of the fine lookup table search of the low-speed bus under normal initial communication conditions.

Detailed Description

In order to make the objects, contents and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.

In view of this, the present invention provides a pre-training-based FPGA and external bus data interaction mechanism. On the basis of a conventional method, pre-training based on a known sequence is added, and before the FPGA interacts with the external bus for effective data, a section of known training sequence is transmitted to obtain an optimal delay value which can normally and stably interact data and can ensure the maximum time sequence allowance, so that the error rate is reduced, and the communication reliability is improved.

The invention provides a pre-training-based FPGA and external bus data interaction method, which comprises the following steps:

step 1, two lookup tables related to delay parameters are stored in an FPGA in advance, wherein one lookup table is a rough lookup table and is used for rough search in a low-speed bus in advance, the other lookup table is a fine lookup table and is used for searching the optimal delay of the high-speed bus, or the other lookup table is used for further detailed search on the basis of the rough search in the low-speed bus, the search step is delta, and the search steps of the rough lookup table and the fine lookup table are different;

step 2, under the initial condition that time delay is not carried out, namely the time delay parameter n is 0, firstly enabling the FPGA and an external bus to carry out transmission of a section of known training sequence, and observing the interaction condition of the known training sequence; if the communication error state is in the beginning, turning to the step 3; if the communication is in the normal communication state, turning to the step 4;

and 3, when the communication between the FPGA and the external bus is in an error state, adopting a search strategy 1: setting a lookup range of a lookup table as [ -clk, clk ], wherein clk is an interface operating frequency, starting from the middle position of the lookup table, namely a delay parameter n is 0, dividing the lookup table into two paths of parallel search in the front direction and the rear direction of the lookup table simultaneously, namely searching the delay parameter in the sequence of n ═ Δ, n ═ 2 Δ, and n ═ 2 Δ.; when a delay parameter is searched, corresponding delay is carried out on data or a clock;

when one path detects normal interactive data, the path stops searching, records the delay parameter in the current lookup table as D1; the other path starts to search from the tail end of the lookup table in the direction of D1, stops after finding the time delay which just can be interacted normally, records the time delay parameter in the current lookup table and records as D2; d1 and D2 are distances between the front and back boundary positions of the data and the current sampling clock edge;

if the current communication bus is a high-speed bus, the search strategy 1 adopts a fine-checking table to directly determine the optimal delay parameter; if the current communication bus is a low-speed bus, the search strategy 1 adopts a rough lookup table, the boundary position of the data needs to be accurately confirmed by further utilizing a fine lookup table, and the step 5 is carried out;

and 4, when the communication between the FPGA and the external bus is in a normal state, adopting a search strategy 2: setting a lookup range of a lookup table as [ -clk, clk ], starting from a middle position of the lookup table, namely a delay parameter n is 0, dividing the lookup table into two paths, and simultaneously searching the two paths in parallel in the front direction and the rear direction of the lookup table, namely searching the delay parameters in the sequence of n being equal to delta, n being equal to-delta, n being equal to 2 delta, and n being equal to-2 delta.

When one path detects that the interaction between the FPGA and the external bus is wrong, the path stops searching, records the delay parameter in the current lookup table and records the delay parameter as D1; the other path is searched continuously, the other path is stopped after the delay with the interaction error is found out, and the delay parameter in the current lookup table is recorded as D2;

if the current communication bus is a high-speed bus, the search strategy 2 adopts a detailed lookup table to directly determine the optimal delay value; if the current communication bus is a low-speed bus, the search strategy 2 adopts a rough lookup table, the boundary position of the data needs to be accurately confirmed by further utilizing a fine lookup table, and the step 5 is carried out;

and 5, when the coarse lookup table confirms that D1 is a data boundary position, adopting a search strategy 3: setting the search range of the fine search table as [ D1-5ns, D1+5ns ], dividing the search range from D1 into two paths, and simultaneously searching in parallel in the front direction and the rear direction of the search table, namely searching the delay parameters in the sequence of n ═ D1+ delta, n ═ D1-delta, n ═ D1+2 delta, and n ═ D1-2 delta.; when a delay parameter is searched, corresponding delay is carried out on data or a clock;

when the change of the data interaction condition is detected, stopping two-way searching, recording the delay parameter in the current lookup table as d 1;

when the coarse lookup table confirms that D2 is another boundary location of the data, search strategy 3 is also employed: setting the search range of the fine search table as [ D2-5ns, D2+5ns ], dividing the search range from D2 into two paths, and simultaneously searching in parallel in the front direction and the rear direction of the search table, namely searching the delay parameters in the sequence of n ═ D2+ delta, n ═ D2-delta, n ═ D2+2 delta, and n ═ D2-2 delta.; when a delay parameter is searched, corresponding delay is carried out on data or a clock;

when the change of the data interaction condition is detected, stopping two-way searching, recording the delay parameter in the current lookup table as d 2;

calculating the optimal delay value of the bus according to d1 and d 2;

step 6, after the optimal delay value is determined, the FPGA carries out corresponding delay on the data or the clock according to the optimal delay value, and then carries out transmission of subsequent effective data

Example 1:

with reference to fig. 1, the specific implementation steps of the proposed interworking mechanism are explained as follows:

step 1, two lookup tables related to delay parameters are stored in an FPGA in advance.

One of the lookup tables is a rough lookup table used for performing rough search in advance in a bus (hereinafter referred to as a "low-speed bus") having an interface operating frequency of not more than 100 MHz. The search step of the coarse lookup table is 5ns (delta-5 ns), and the search range is [ -clk, clk ] (clk is the interface operating frequency);

the other lookup table is a fine lookup table used for further fine lookup on the basis of rough search in a low-speed bus or directly performing search of optimal delay in a bus with an interface working frequency greater than 100MHz (hereinafter referred to as a high-speed bus). The fine lookup table search steps are 78ps (Δ ═ 78ps), and the search range varies with the type of current interface bus: when the fine search is carried out in the low-speed bus, the search range of the fine search table is [ D-5ns, D +5ns ], wherein D is the rough search result of the rough search table; when the optimum delay search is performed in the high-speed bus, the search range of the scrutiny table is [ -clk, clk ] (clk is the interface working frequency).

And the FPGA carries out corresponding time delay on data and a clock according to the currently searched time delay parameter n (n is a real number), and observes the data interaction condition. The specific delay operation is as follows:

when the delay parameter is positive (n > 0), the clock is delayed backward nns or ps;

when the delay parameter is negative (n < 0), the data is delayed back by | n | ns or ps.

And 2, under the initial condition of not delaying (the delay parameter n is 0), firstly enabling the FPGA and an external bus to transmit a section of known training sequence and observing the interaction condition of the known training sequence.

If the external bus is a parallel bus, directly comparing whether the received data is consistent with the known training sequence. If more than 4 continuous bytes are consistent with the training sequence, the communication between the FPGA and the external parallel bus is determined to be in a normal state, otherwise, the communication is in an error state;

if the external bus is a serial bus, serial-to-parallel conversion is carried out immediately after the data is received, and the converted received data is compared with a known training sequence to observe whether the received data is consistent with the known training sequence. More than 4 continuous bytes (32 bits) are consistent with the training sequence, namely the communication between the FPGA and the external serial bus is determined to be in a normal state, otherwise, the communication is in an error state.

If the communication error state (the error rate is higher) is in the beginning, the step 3 is carried out; if the communication is in a normal communication state (the error rate is low), turning to the step 4;

and 3, when the communication between the FPGA and the external bus is in an error state, adopting a search strategy 1: the method comprises the steps of setting a lookup range of a lookup table as [ -clk, clk ] (clk is an interface operating frequency), starting from a middle position of the lookup table (delay parameter n is 0), dividing the lookup table into two paths, and simultaneously searching in parallel in the front direction and the rear direction of the lookup table, namely searching for the delay parameter in the sequence of n being Δ, n being- Δ, n being 2 Δ, n being-2 Δ. Whenever a delay parameter is searched, the data or clock is delayed correspondingly according to the method defined in step 1.

When one way detects that normal interactive data can be obtained, the way stops searching, records the delay parameter in the current lookup table, and records the delay parameter as D1. And the other path starts to search from the tail end of the lookup table in the direction of D1, stops after finding the delay which just can be interacted normally, records the delay parameter in the current lookup table and records the delay parameter as D2. D1 and D2 are the distances of the two boundary positions before and after the data with respect to the current sampling clock edge.

And further determining the optimal delay parameters according to the interface working frequency of the current communication bus.

High speed bus

If the current communication bus is a high-speed bus, that is, the interface operating frequency is greater than 100MHz, the search strategy 1 uses a fine search table, and after the data boundary values D1 and D2 are obtained through searching, a delay value delay _ h between the optimal sampling position at the data middle position and the current sampling clock edge is calculated by using the fine search table and recorded as the optimal delay value. The overall delay adjustment diagram is shown in fig. 2.

|D2|＞|D1|＞0,|delay_h|＞0

Low speed bus

If the current communication bus is a low-speed bus, that is, the interface operating frequency is less than or equal to 100MHz, the search strategy 1 adopts a rough lookup table, and after the data boundary values D1 and D2 are obtained through searching, the boundary position of the data needs to be accurately confirmed by further using a fine lookup table, and the process goes to step 5;

and 4, when the communication between the FPGA and the external bus is in a normal state, adopting a search strategy 2: the method comprises the steps of setting a lookup range of a lookup table as [ -clk, clk ] (clk is an interface operating frequency), starting from a middle position (the delay parameter is 0), dividing the lookup range into two paths, and simultaneously searching in parallel in the front direction and the rear direction of the lookup table, namely searching the delay parameter in the sequence of n ═ delta, n ═ 2 delta. Whenever a delay parameter is searched, the data or clock is delayed accordingly.

When one path detects that the interaction between the FPGA and the external bus has an error, the path stops searching, records the delay parameter in the current lookup table, and records the delay parameter as D1. And the other path is searched continuously, the other path is stopped after the delay which happens to have the interaction error is found, and the delay parameter in the current lookup table is recorded as D2.

And further determining the optimal delay parameters according to the interface working frequency of the current communication bus.

High speed bus

If the current communication bus is a high-speed bus, that is, the interface operating frequency is greater than 100MHz, the search strategy 2 uses a fine search table, and after the data boundary values D1 and D2 are obtained through searching, the delay value delay _ h between the optimal sampling position at the data intermediate position and the current sampling point is calculated by using the fine search table, and the delay value delay _ h is recorded as the optimal delay value. The overall delay adjustment diagram is shown in fig. 3.

|D2|≥|D1|＞0,delay_h∈R

Low speed bus

If the current communication bus is a low-speed bus, that is, the interface operating frequency is less than or equal to 100MHz, the search strategy 2 adopts a rough lookup table, and after the data boundary values D1 and D2 are obtained through searching, the boundary position of the data needs to be accurately confirmed by further using a fine lookup table, and the process goes to step 5;

step 5, in the case of a low speed bus, the coarse lookup table has been used to locate the two front and back boundary positions of the data near D1 and D2, respectively. The data boundaries are then further pinpointed using a fine look-up table.

When the coarse lookup table confirms that D1 is a data boundary location, search strategy 3 is used: the search range of the fine lookup table is set to [ D1-5ns, D1+5ns ], the search is divided into two paths from D1, and the two paths are simultaneously searched in the front direction and the rear direction of the lookup table in parallel, namely, the delay parameters are searched in the sequence of n ═ D1+ Δ, n ═ D1- Δ, n ═ D1+2 Δ, and n ═ D1-2 Δ. Whenever a delay parameter is searched, the data or clock is delayed accordingly.

When the data interaction condition is detected to be changed (the interaction state is changed from normal to error or from error to normal), both searches are stopped, and the delay parameter in the current lookup table is recorded as d 1.

Similarly, when the coarse lookup table identifies D2 as another boundary location of the data, search strategy 3 is also employed: the search range of the fine lookup table is set to [ D2-5ns, D2+5ns ], the search is divided into two paths from D2, and the two paths are simultaneously searched in the front direction and the rear direction of the lookup table in parallel, namely, the delay parameters are searched in the sequence of n ═ D2+ Δ, n ═ D2- Δ, n ═ D2+2 Δ, and n ═ D2-2 Δ. Whenever a delay parameter is searched, the data or clock is delayed accordingly.

When the change of the data interaction condition is detected (the interaction state is changed from normal to error or from error to normal), stopping two-way searching, recording the delay parameter in the current lookup table, and recording the delay parameter as d 2;

and calculating a delay value delay _ l between the optimal sampling position at the data middle position and the current sampling point, and recording the delay value delay _ l as the optimal delay value of the bus. The overall delay adjustment is schematically illustrated in fig. 4 to 7.

|d2|≥|d1|＞0,delay_l∈R

And 6, after the optimal delay value is determined, the FPGA carries out corresponding delay on the data or the clock according to the optimal delay value, and then carries out transmission of subsequent effective data. The specific delay operation is as follows:

when the current optimal delay value is positive (delay is more than 0), the clock is delayed backward by delay ns or ps;

when the current optimal delay value is negative (delay < 0), the data is delayed back by | delay | ns or ps.

The invention considers the influence of the FPGA on the transmission delay of the chip circuit under different working temperatures, layout and wiring and other environmental conditions, and carries out parallel search on the optimal delay parameter of the current bus based on the iterative use of a coarse lookup table and a fine lookup table. Compared with a conventional FPGA and external bus data interaction method, the pre-training-based FPGA and external bus data interaction mechanism improves the communication reliability of the FPGA and the external bus and reduces the error rate of the FPGA and the external bus. Meanwhile, the method has good adaptability, can generally adapt to buses with different interface rates, and quickly and accurately searches the optimal delay value of the current bus by self-adaptive selection of a rough and fine search table.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims (10)

1. A pre-training-based FPGA and external bus data interaction method is characterized by comprising the following steps:

step 1, two lookup tables related to delay parameters are stored in an FPGA in advance, wherein one lookup table is a rough lookup table and is used for rough search in a low-speed bus in advance, the other lookup table is a fine lookup table and is used for searching the optimal delay of the high-speed bus, or the other lookup table is used for further detailed search on the basis of the rough search in the low-speed bus, the search step is delta, and the search steps of the rough lookup table and the fine lookup table are different;

step 2, under the initial condition that time delay is not carried out, namely the time delay parameter n is 0, firstly enabling the FPGA and an external bus to carry out transmission of a section of known training sequence, and observing the interaction condition of the known training sequence; if the communication error state is in the beginning, turning to the step 3; if the communication is in the normal communication state, turning to the step 4;

and 3, when the communication between the FPGA and the external bus is in an error state, adopting a search strategy 1: setting a lookup range of a lookup table as [ -clk, clk ], wherein clk is an interface operating frequency, starting from the middle position of the lookup table, namely, a delay parameter n is 0, dividing the lookup table into two paths of parallel search in the front direction and the rear direction of the lookup table simultaneously, namely, searching the delay parameter in the sequence of n ═ Δ, n ═ 2 Δ, and n ═ 2 Δ.. the delay parameter; when a delay parameter is searched, corresponding delay is carried out on data or a clock;

when one path detects normal interactive data, the path stops searching, records the delay parameter in the current lookup table as D1; the other path starts to search from the tail end of the lookup table in the direction of D1, stops after finding the time delay which just can be interacted normally, records the time delay parameter in the current lookup table and records as D2; d1 and D2 are distances between the front and back boundary positions of the data and the current sampling clock edge;

if the current communication bus is a high-speed bus, the search strategy 1 adopts a fine-checking table to directly determine the optimal delay parameter; if the current communication bus is a low-speed bus, the search strategy 1 adopts a rough lookup table, the boundary position of the data needs to be accurately confirmed by further utilizing a fine lookup table, and the step 5 is carried out;

and 4, when the communication between the FPGA and the external bus is in a normal state, adopting a search strategy 2: setting a lookup range of a lookup table as [ -clk, clk ], starting from a middle position of the lookup table, namely a delay parameter n is 0, dividing the lookup table into two paths, and simultaneously searching the two paths in parallel in the front direction and the rear direction of the lookup table, namely searching the delay parameters in the sequence of n being equal to delta, n being equal to-delta, n being equal to 2 delta, and n being equal to-2 delta.

When one path detects that the interaction between the FPGA and the external bus is wrong, the path stops searching, records the delay parameter in the current lookup table and records the delay parameter as D1; the other path is searched continuously, the other path is stopped after the delay with the interaction error is found out, and the delay parameter in the current lookup table is recorded as D2;

if the current communication bus is a high-speed bus, the search strategy 2 adopts a detailed lookup table to directly determine the optimal delay value; if the current communication bus is a low-speed bus, the search strategy 2 adopts a rough lookup table, the boundary position of the data needs to be accurately confirmed by further utilizing a fine lookup table, and the step 5 is carried out;

and 5, when the coarse lookup table confirms that D1 is a data boundary position, adopting a search strategy 3: setting the search range of the fine search table as [ D1-5ns, D1+5ns ], dividing the search range from D1 into two paths, and simultaneously searching in parallel in the front direction and the rear direction of the search table, namely searching the delay parameters in the sequence of n ═ D1+ delta, n ═ D1-delta, n ═ D1+2 delta, and n ═ D1-2 delta.; when a delay parameter is searched, corresponding delay is carried out on data or a clock;

when the change of the data interaction condition is detected, stopping two-way searching, recording the delay parameter in the current lookup table as d 1;

when the coarse lookup table confirms that D2 is another boundary location of the data, search strategy 3 is also employed: setting the search range of the fine search table as [ D2-5ns, D2+5ns ], dividing the search range from D2 into two paths, and simultaneously searching in parallel in the front direction and the rear direction of the search table, namely searching the delay parameters in the sequence of n ═ D2+ delta, n ═ D2-delta, n ═ D2+2 delta, and n ═ D2-2 delta.; when a delay parameter is searched, corresponding delay is carried out on data or a clock;

when the change of the data interaction condition is detected, stopping two-way searching, recording the delay parameter in the current lookup table as d 2;

calculating the optimal delay value of the bus according to d1 and d 2;

and 6, after the optimal delay value is determined, the FPGA carries out corresponding delay on the data or the clock according to the optimal delay value, and then carries out transmission of subsequent effective data.

2. The method of claim 1, wherein the low-speed bus is a bus with an interface operating frequency of not more than 100MHz, and the high-speed bus is a bus with an interface operating frequency of more than 100 MHz.

3. The method of claim 1, wherein the search step of the coarse lookup table is Δ -5ns, and the search step of the fine lookup table is Δ -78 ps.

4. The method according to claim 1, wherein when performing the fine lookup in the low-speed bus, the lookup range of the fine lookup table is [ D-5ns, D +5ns ], where D is the coarse lookup result of the coarse lookup table; when the optimal delay search is performed in the high-speed bus, the search range of the scrutiny table is [ -clk, clk ].

5. The method for interacting the data between the FPGA and the external bus based on the pre-training as claimed in any one of claims 1 to 4, wherein the FPGA carries out corresponding time delay on the data and the clock according to the currently searched time delay parameter n, wherein n is a real number, and observes the data interaction condition; the specific delay operation is as follows: when the delay parameter is that the positive number n is larger than 0, the clock is delayed backward nns or ps; when the delay parameter is negative n < 0, then the data is delayed back by | n | ns or ps.

6. The method according to claim 5, wherein in step S2, if the external bus is a parallel bus, directly comparing whether the received data is consistent with the known training sequence, and if there are more than 4 consecutive bytes consistent with the training sequence, it is determined that the current communication between the FPGA and the external parallel bus is in a normal state, otherwise, it is in an error state; if the external bus is a serial bus, performing serial-parallel conversion immediately after receiving data, comparing the converted received data with a known training sequence to observe whether the received data is consistent with the known training sequence, and if the received data is consistent with the known training sequence, determining that the communication between the FPGA and the external serial bus is in a normal state, otherwise, determining that the communication is in an error state.

7. The method according to claim 6, wherein in step S3, if the current communication bus is a high-speed bus, the search strategy 1 uses a fine search table, and after the data boundary values D1 and D2 are obtained by searching, a delay value delay _ h between the optimal sampling position at the data middle position and the current sampling clock edge is calculated and recorded as the optimal delay value;

if the current communication bus is a low-speed bus, the search strategy 1 adopts a rough lookup table, and after the data boundary values D1 and D2 are obtained through searching, the boundary position of the data needs to be accurately confirmed by further using a fine lookup table, and the process goes to step 5.

8. The method according to claim 6, wherein in step S4,

if the current communication bus is a high-speed bus, the search strategy 2 adopts a fine-search table, and after the data boundary values D1 and D2 are obtained through searching, the delay value delay _ h between the optimal sampling position at the data intermediate position and the current sampling point is calculated by using the fine-search table and is recorded as the optimal delay value;

if the current communication bus is a low-speed bus, the search strategy 2 adopts a rough lookup table, and after the data boundary values D1 and D2 are obtained through searching, the boundary position of the data needs to be accurately confirmed by further using a fine lookup table, and the process goes to step 5.

9. The method according to claim 7 or 8, wherein in step S5, the interaction status changes from normal to error or from error to normal; the method for calculating the optimal delay value of the bus according to d1 and d2 comprises the following steps:

calculating a delay value delay _ l between the optimal sampling position at the data intermediate position and the current sampling point, and recording the delay value delay _ l as the optimal delay value of the bus;

10. the method for interacting data between the FPGA and the external bus based on pre-training as claimed in claim 9, wherein the delay operation in step S6 is as follows:

when the current optimal delay value is a positive number, namely delay is greater than 0, the clock is delayed backward by delayns or ps;

when the current optimal delay value is negative, i.e. delay < 0, the data is delayed backwards by | delay | ns or ps.

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