CN110162503A - High-speed data synchronous circuit and method of data synchronization - Google Patents
High-speed data synchronous circuit and method of data synchronization Download PDFInfo
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- CN110162503A CN110162503A CN201910435442.1A CN201910435442A CN110162503A CN 110162503 A CN110162503 A CN 110162503A CN 201910435442 A CN201910435442 A CN 201910435442A CN 110162503 A CN110162503 A CN 110162503A
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- 238000000034 method Methods 0.000 title claims abstract description 9
- 238000006243 chemical reaction Methods 0.000 claims abstract description 20
- 230000005540 biological transmission Effects 0.000 claims abstract description 8
- 238000004321 preservation Methods 0.000 claims description 5
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000013256 coordination polymer Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a kind of high-speed data synchronous circuit and method of data synchronization, wherein synchronous circuit includes: to realize that serial transmission turns the serial-parallel conversion circuit of parallel transmission using analog circuit；Connect the serial-parallel conversion circuit, and the phase-adjusting circuit adjusted using digital circuit data and clock phase.Under conditions of dynamically not adjusting clock delay unit, by increasing and decreasing data terminal delay cell, to calculate the final delay unit of data, realizes the good phases of data and clock, solve the stationary problem of MIPI RX high-speed data with the delay of very little.
Description
Technical field
The present invention relates to data synchronization technology fields.
Background technique
MIPI (Mobile Industry Processor Interface) is used as a kind of high-speed interface, when data frequency is more than 1.5Gbps, MIPI association
View requirement can have the adjustment of data and clock skew.The simultaneous techniques of existing high-speed data is typically all by adjusting separately number
It is realized according to the mode of the delay cell with clock, when adjusted when clock delay cell, internal circuit requires one
The clock for not following clock delay unit is used as the operation of internal sequential logic.Which adds clock complexities.
Summary of the invention
High-speed data synchronous circuit and corresponding number are provided it is an object of the invention to overcome the deficiencies of existing technologies
According to synchronous method, solves the stationary problem of MIPI RX (receiver) high-speed data with the delay of very little.
Realizing the technical solution of above-mentioned purpose is:
High-speed data synchronous circuit of the invention, comprising:
Realize that serial transmission turns the serial-parallel conversion circuit of parallel transmission using analog circuit；And
Connect the serial-parallel conversion circuit, and the phase adjustment electricity adjusted using digital circuit data and clock phase
Road；
Wherein, the phase-adjusting circuit is provided with
Data transfer for postponing adjustable data postpones output end to the data of the serial-parallel conversion circuit；And
For the data transfer for the clock delay fixed to be given to the clock delay output end of the serial-parallel conversion circuit.
Preferably, the serial-parallel conversion circuit is provided with
The differential input end of clock；
The differential input end of data；
For exporting 8 frequency-dividing clocks of differential input clock to 8 frequency-dividing clock output ends of the phase-adjusting circuit；
And
For will go here and there turn and signal export to the phase-adjusting circuit string turn and signal output end.
The method of data synchronization such as above-mentioned high-speed data synchronous circuit of the invention, comprising:
The numerical value that data postpone output end and the output of clock delay output end is set to median 7'h40,
Save the value that current going here and there turns the string turn and signal of simultaneously signal output end output；
Since median 7'h40, it is continuously increased the value of data delay output end output, when string turns and the value of signal is from guarantor
When the value deposited starts variation, the increased value of value institute for saving the output end output of data delay at this time is Tac；
Since median 7'h40, the value of data delay output end output is constantly reduced, when string turns and the value of signal is from guarantor
The value deposited start variation when, save at this time data delay output end output value reduction value be Tbd；
Work as Tac >=Tbd, be arranged: data postpone value=7'h40- (Tac-Tbd)/2 of output end output；
As Tac < Tbd, setting: data postpone value=7'h40+ (Tbd-Tac)/2 of output end output.
The beneficial effects of the present invention are: the present invention is postponed by fixed clock delay cell, and increase with data are reduced
The mode of unit finds an ideal phase, come guarantee data to clock settling time and retention time, in this way, just using
The delay of very little solves the stationary problem of MIPI RX high-speed data.
Detailed description of the invention
Fig. 1 is the schematic diagram of high-speed data synchronous circuit of the invention；
Fig. 2 is the relation schematic diagram in the present invention at internal data sampled point between data DATA and clock CLK；
Fig. 3 is the schematic diagram of the increased value of DLL_DATA_NUM and the value of reduction in the present invention.
Specific embodiment
The present invention will be further described with reference to the accompanying drawings.
Referring to Fig. 1, high-speed data synchronous circuit of the invention, including serial-parallel conversion circuit 1 and phase-adjusting circuit 2.
Serial-parallel conversion circuit 1 realizes that serial transmission turns parallel transmission using analog circuit.Specifically, serial-parallel conversion circuit is set
Be equipped with: the differential input end of clock, the differential input end of data, 8 frequency-dividing clock output ends, string turns and signal output end.Fig. 1
In, RX_CP/RX_CN indicates that the Differential Input of high-frequency clock, RX_DP/RX_DN indicate the Differential Input of high number data, data
Frequency is 2.5Gbps, and CLK_HS is 8 frequency-dividing clocks of the Differential Input RX_CP/RX_CN of clock, and DATA_HS is the string of 8bit
Turn simultaneously signal, CLK_HS, DATA_HS are transferred to phase-adjusting circuit 2.
Phase-adjusting circuit 2 connects serial-parallel conversion circuit 1, and is adjusted using digital circuit data and clock phase.
Phase-adjusting circuit 2 is provided with data delay output end, clock delay output end.In Fig. 1, DLL_DATA_NUM, DLL_CLK_
NUM respectively indicates internal sample delay control, and DLL_DATA_NUM is the numerical value of the data delay of setting；DLL_CLK_NUM is set
The numerical value for the clock delay set, DLL_DATA_NUM, DLL_CLK_NUM are transferred to serial-parallel conversion circuit 1.Data postpone output end
Data transfer for postponing adjustable data is to serial-parallel conversion circuit 1.Clock delay output end is used for the clock that will be fixed
The data transfer of delay is to serial-parallel conversion circuit 1.
When DLL_DATA_NUM and DLL_CLK_NUM are disposed as 7'b0 (DLL_CLK_NUM and DLL_DATA_NUM difference
It is controlled with 7 bit registers, when 7'b0 indicates 0) 7 bit registers are all, clock and data all do not postpone, and at this point, clock
Edge default be in data middle position.Such as Fig. 2, indicate at internal data sampled point between data DATA and clock CLK
Relationship.
Serial-parallel conversion circuit 1 is realized using AFE (analog circuit realization part).Phase-adjusting circuit 2 is (inclined using SKEW
Difference) it realizes.
The method of data synchronization such as above-mentioned high-speed data synchronous circuit of the invention, including the following steps:
One, data are postponed numerical value DLL_DATA_NUM, DLL_CLK_NUM of output end and the output of clock delay output end
Being set to median 7'h40, (7'h0 indicates that 7 bit register highest orders are 1, other are that 0), thus can guarantee doing
The value DLL_CLK_NUM of clock CLK is no longer adjusted when phase adjustment, because the operation needs in internal state machine are stable
CLK, then by increasing or decreasing the delay DLL_DATA_NUM of data terminal, to find between data DATA and clock CLK
Relationship finally can just be placed on the edge of clock the middle position of data.
Two, as shown in Figure 3.Save the value DATA_HS that current going here and there turns the string turn and signal of simultaneously signal output end output
[7].Since median 7'h40, it is continuously increased the value DLL_DATA_NUM of data delay output end output, when string turns simultaneously signal
Value DATA_HS [7] when changing since the value of preservation, saving the increased value of DLL_DATA_NUM institute at this time is Tac.
Three, since median 7'h40, the value DLL_DATA_NUM of data delay output end output is constantly reduced, string is worked as
Turn and when the value DATA_HS [7] of signal change since the value of preservation, preservation at this time DLL_DATA_NUM the value of reduction be
Tbd。
Work as Tac >=Tbd, is arranged: DLL_DATA_NUM=7'h40- (Tac-Tbd)/2；
When Tac < Tbd, setting: DLL_DATA_NUM=7'h40+ (Tbd-Tac)/2.
Finally, corresponding DLL_DATA_NUM is arranged, terminate adjustment.
Above embodiments are used for illustrative purposes only, rather than limitation of the present invention, the technology people in relation to technical field
Member, without departing from the spirit and scope of the present invention, can also make various transformation or modification, therefore all equivalent
Technical solution also should belong to scope of the invention, should be limited by each claim.
Claims (3)
1. a kind of high-speed data synchronous circuit characterized by comprising
Realize that serial transmission turns the serial-parallel conversion circuit of parallel transmission using analog circuit；And
Connect the serial-parallel conversion circuit, and the phase-adjusting circuit adjusted using digital circuit data and clock phase；
Wherein, the phase-adjusting circuit is provided with
Data transfer for postponing adjustable data postpones output end to the data of the serial-parallel conversion circuit；And
For the data transfer for the clock delay fixed to be given to the clock delay output end of the serial-parallel conversion circuit.
2. high-speed data synchronous circuit according to claim 1, which is characterized in that the serial-parallel conversion circuit is provided with
The differential input end of clock；
The differential input end of data；
For exporting 8 frequency-dividing clocks of differential input clock to 8 frequency-dividing clock output ends of the phase-adjusting circuit；And
For will go here and there turn and signal export to the phase-adjusting circuit string turn and signal output end.
3. a kind of method of data synchronization of high-speed data synchronous circuit as claimed in claim 2 characterized by comprising
The numerical value that data postpone output end and the output of clock delay output end is set to median 7'h40,
Save the value that current going here and there turns the string turn and signal of simultaneously signal output end output；
Since median 7'h40, it is continuously increased the value of data delay output end output, when string turns and the value of signal is from preservation
When value starts variation, the increased value of value institute for saving the output end output of data delay at this time is Tac；
Since median 7'h40, the value of data delay output end output is constantly reduced, when string turns and the value of signal is from preservation
Value start variation when, save at this time data delay output end output value reduction value be Tbd；
Work as Tac >=Tbd, be arranged: data postpone value=7'h40- (Tac-Tbd)/2 of output end output；
As Tac < Tbd, setting: data postpone value=7'h40+ (Tbd-Tac)/2 of output end output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910435442.1A CN110162503B (en) | 2019-05-23 | 2019-05-23 | High-speed data synchronization circuit and data synchronization method |
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| CN201910435442.1A CN110162503B (en) | 2019-05-23 | 2019-05-23 | High-speed data synchronization circuit and data synchronization method |
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| CN110162503A true CN110162503A (en) | 2019-08-23 |
| CN110162503B CN110162503B (en) | 2024-03-22 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112327693A (en) * | 2020-11-02 | 2021-02-05 | 南京理工大学 | Multichannel data synchronization circuit based on FPGA |
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| US20110304369A1 (en) * | 2010-06-11 | 2011-12-15 | Nec Laboratories America, Inc. | Method for source synchronous high-speed signal synchronization |
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| CN101232360A (en) * | 2007-01-23 | 2008-07-30 | 华为技术有限公司 | Data receiving apparatus and method |
| CN101848334A (en) * | 2009-01-30 | 2010-09-29 | 株式会社尼康 | Phase adjusting apparatus and video camera |
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| US20110304369A1 (en) * | 2010-06-11 | 2011-12-15 | Nec Laboratories America, Inc. | Method for source synchronous high-speed signal synchronization |
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| CN112327693A (en) * | 2020-11-02 | 2021-02-05 | 南京理工大学 | Multichannel data synchronization circuit based on FPGA |
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