CN209570934U - High-speed data synchronous circuit - Google Patents

Abstract

The utility model discloses a kind of high-speed data synchronous circuits, comprising: realizes that serial transmission turns the serial-parallel conversion circuit of parallel transmission using analog circuit；Connect the serial-parallel conversion circuit, and the phase-adjusting circuit adjusted using digital circuit data and clock phase.Under conditions of dynamically not adjusting clock delay unit, by increasing and decreasing data terminal delay cell, to calculate the final delay unit of data, realizes the good phases of data and clock, solve the stationary problem of MIPI RX high-speed data with the delay of very little.

Description

High-speed data synchronous circuit

Technical field

The utility model relates to data synchronization technology fields.

Background technique

MIPI (Mobile Industry Processor Interface) is used as a kind of high-speed interface, when data frequency is more than 1.5Gbps, MIPI association View requirement can have the adjustment of data and clock skew.The simultaneous techniques of existing high-speed data is typically all by adjusting separately number It is realized according to the mode of the delay cell with clock, when adjusted when clock delay cell, internal circuit requires one The clock for not following clock delay unit is used as the operation of internal sequential logic.Which adds clock complexities.

Utility model content

High-speed data synchronous circuit is provided the purpose of the utility model is to overcome the defect of the prior art, with very little Delay solves the stationary problem of MIPI RX (receiver) high-speed data.

Realizing the technical solution of above-mentioned purpose is:

The high-speed data synchronous circuit of the utility model, comprising:

Realize that serial transmission turns the serial-parallel conversion circuit of parallel transmission using analog circuit；And

Connect the serial-parallel conversion circuit, and the phase adjustment electricity adjusted using digital circuit data and clock phase Road；

Wherein, the phase-adjusting circuit is provided with

Data transfer for postponing adjustable data postpones output end to the data of the serial-parallel conversion circuit；And

For the data transfer for the clock delay fixed to be given to the clock delay output end of the serial-parallel conversion circuit.

Preferably, the serial-parallel conversion circuit is provided with

The differential input end of clock；

The differential input end of data；

For exporting 8 frequency-dividing clocks of differential input clock to 8 frequency-dividing clock output ends of the phase-adjusting circuit； And

For will go here and there turn and signal export to the phase-adjusting circuit string turn and signal output end.

The beneficial effects of the utility model are: the utility model passes through fixed clock delay cell, and increase and reduction The mode of data delaying unit finds an ideal phase, come guarantee data to clock settling time and retention time, In this way, just solving the stationary problem of MIPI RX high-speed data with the delay of very little.

Detailed description of the invention

Fig. 1 is the schematic diagram of the high-speed data synchronous circuit of the utility model；

Fig. 2 is the relation schematic diagram in the utility model at internal data sampled point between data DATA and clock CLK；

Fig. 3 is the schematic diagram of the increased value of DLL_DATA_NUM and the value of reduction in the utility model.

Specific embodiment

Below in conjunction with attached drawing, the utility model is described in further detail.

Referring to Fig. 1, the high-speed data synchronous circuit of the utility model, including serial-parallel conversion circuit 1 and phase adjustment electricity Road 2.

Serial-parallel conversion circuit 1 realizes that serial transmission turns parallel transmission using analog circuit.Specifically, serial-parallel conversion circuit is set Be equipped with: the differential input end of clock, the differential input end of data, 8 frequency-dividing clock output ends, string turns and signal output end.Fig. 1 In, RX_CP/RX_CN indicates that the Differential Input of high-frequency clock, RX_DP/RX_DN indicate the Differential Input of high number data, data Frequency is 2.5Gbps, and CLK_HS is 8 frequency-dividing clocks of the Differential Input RX_CP/RX_CN of clock, and DATA_HS is the string of 8bit Turn simultaneously signal, CLK_HS, DATA_HS are transferred to phase-adjusting circuit 2.

Phase-adjusting circuit 2 connects serial-parallel conversion circuit 1, and is adjusted using digital circuit data and clock phase. Phase-adjusting circuit 2 is provided with data delay output end, clock delay output end.In Fig. 1, DLL_DATA_NUM, DLL_CLK_ NUM respectively indicates internal sample delay control, and DLL_DATA_NUM is the numerical value of the data delay of setting；DLL_CLK_NUM is set The numerical value for the clock delay set, DLL_DATA_NUM, DLL_CLK_NUM are transferred to serial-parallel conversion circuit 1.Data postpone output end Data transfer for postponing adjustable data is to serial-parallel conversion circuit 1.Clock delay output end is used for the clock that will be fixed The data transfer of delay is to serial-parallel conversion circuit 1.

When DLL_DATA_NUM and DLL_CLK_NUM are disposed as 7'b0 (DLL_CLK_NUM and DLL_DATA_NUM difference It is controlled with 7 bit registers, when 7'b0 indicates 0) 7 bit registers are all, clock and data all do not postpone, and at this point, clock Edge default be in data middle position.Such as Fig. 2, indicate at internal data sampled point between data DATA and clock CLK Relationship.

Serial-parallel conversion circuit 1 is realized using AFE (analog circuit realization part).Phase-adjusting circuit 2 is (inclined using SKEW Difference) it realizes.

The utility model as above-mentioned high-speed data synchronous circuit method of data synchronization, including the following steps:

One, data are postponed numerical value DLL_DATA_NUM, DLL_CLK_NUM of output end and the output of clock delay output end Being set to median 7'h40, (7'h0 indicates that 7 bit register highest orders are 1, other are that 0), thus can guarantee doing The value DLL_CLK_NUM of clock CLK is no longer adjusted when phase adjustment, because the operation needs in internal state machine are stable CLK, then by increasing or decreasing the delay DLL_DATA_NUM of data terminal, to find between data DATA and clock CLK Relationship finally can just be placed on the edge of clock the middle position of data.

Two, as shown in Figure 3.Save the value DATA_HS that current going here and there turns the string turn and signal of simultaneously signal output end output [7].Since median 7'h40, it is continuously increased the value DLL_DATA_NUM of data delay output end output, when string turns simultaneously signal Value DATA_HS [7] when changing since the value of preservation, saving the increased value of DLL_DATA_NUM institute at this time is Tac.

Three, since median 7'h40, the value DLL_DATA_NUM of data delay output end output is constantly reduced, string is worked as Turn and when the value DATA_HS [7] of signal change since the value of preservation, preservation at this time DLL_DATA_NUM the value of reduction be Tbd。

Work as Tac >=Tbd, is arranged: DLL_DATA_NUM=7'h40- (Tac-Tbd)/2；

When Tac < Tbd, setting: DLL_DATA_NUM=7'h40+ (Tbd-Tac)/2.

Finally, corresponding DLL_DATA_NUM is arranged, terminate adjustment.

Above embodiments are only for illustration of the utility model, rather than limitations of the present invention, related technical field Technical staff can also make various transformation or modification in the case where not departing from the spirit and scope of the utility model, because This all equivalent technical solution also should belong to the scope of the utility model, should be limited by each claim.

Claims (2)

1. a kind of high-speed data synchronous circuit characterized by comprising

Realize that serial transmission turns the serial-parallel conversion circuit of parallel transmission using analog circuit；And

Connect the serial-parallel conversion circuit, and the phase-adjusting circuit adjusted using digital circuit data and clock phase；

Wherein, the phase-adjusting circuit is provided with

Data transfer for postponing adjustable data postpones output end to the data of the serial-parallel conversion circuit；And

For the data transfer for the clock delay fixed to be given to the clock delay output end of the serial-parallel conversion circuit.

2. high-speed data synchronous circuit according to claim 1, which is characterized in that the serial-parallel conversion circuit is provided with

The differential input end of clock；

The differential input end of data；

For exporting 8 frequency-dividing clocks of differential input clock to 8 frequency-dividing clock output ends of the phase-adjusting circuit；And

For will go here and there turn and signal export to the phase-adjusting circuit string turn and signal output end.