CN104821808A - Phase interpolator - Google Patents
Phase interpolator Download PDFInfo
- Publication number
- CN104821808A CN104821808A CN201510260684.3A CN201510260684A CN104821808A CN 104821808 A CN104821808 A CN 104821808A CN 201510260684 A CN201510260684 A CN 201510260684A CN 104821808 A CN104821808 A CN 104821808A
- Authority
- CN
- China
- Prior art keywords
- clock
- code
- selecting
- clock signal
- clock selecting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention provides a phase interpolator, which comprises a clock selection decoder, a clock selection judging circuit, a first clock selection circuit, a second clock selection circuit, and a phase interpolation circuit, wherein the clock selection decoder is used for decoding an interpolation control code to obtain original group and preliminary group clock selection codes, wherein each clock selection code in the preliminary group clock selection codes changes in a half sampling clock cycle earlier than a clock selection code in the original group clock selection codes; when the clock selection code in the preliminary group clock selection codes changes, the clock selection judging circuit selectively outputs the preliminary group clock selection code, or otherwise, the original group clock selection code is selectively outputted; the first clock selection circuit outputs a first or a third clock signal according to the group of clock selection codes outputted by the clock selection judging circuit; the second clock selection circuit outputs a second or a fourth clock signal according to the group of clock selection codes outputted by the clock selection judging circuit; and the phase interpolation circuit carries out interpolation on clock signals outputted by the first clock selection circuit and the second clock selection circuit and outputs a clock signal after clock selection circuit. Burrs generated during the clock switching process can be avoided.
Description
[technical field]
The present invention relates to phase interpolator technical field, particularly a kind of novel phase interpolator, it can avoid the impact that the burr that produces in clock handoff procedure outputs signal phase interpolator, and it greatly can improve performance and the stability of system.
[background technology]
Phase interpolator (phase interpolator) cycle is identical and phase place is different two periodic input signal S1 and S2 can mix the output number of a generation marginal same period of phase place in proportion.As shown in Figure 1, described phase interpolator 100 it comprise the first clock selection circuit 110, second clock selection circuit 120 and phase-interpolation circuit 130.
The first input end input phase of the first clock selection circuit 110 is first clock signal clk 0 of 0, second input input phase is the 3rd clock signal clk 180 of 180, and it selects the first clock signal clk 0 and the 3rd clock signal clk 180 to export as clock signal S1 according to control signal Sel1.The first input end input phase of second clock selection circuit 120 is the second clock signal CLK90 of 90, second input input phase is the 3rd clock signal clk 270 of 270, and it selects second clock signal CLK90 and the 4th clock signal clk 180 to export as clock signal S2 according to control signal Sel2.First clock signal, second clock signal, the 3rd clock signal are identical with the cycle of the 4th clock signal, and phase place is different.
The first input end of described phase-interpolation circuit 130 receives described clock signal S1, and the second input receives described clock signal S2, and clock signal S1 and S2 is mixed into the clock signal Sout of phase place between S1 and S2 according to weight control signal w by it.
The computing formula of the phase place of the clock signal Sout that interpolation exports is as follows:
Wherein θ
soutfor the phase place of clock signal Sout, θ
s1for the phase place of clock signal S1, θ
s2for the phase place of clock signal S2, the value of w is from 0 to W.Can find out, by controlling described weight control signal w, the phase place of the clock signal Sout after interpolation can be from θ
s1to θ
s2arbitrary phase place.
Fig. 2 obtains the phase place schematic diagram of a clock signal Sout after illustrating two input clock signal S1 and S2 interpolation.
Shown in composition graphs 3, if when wishing that interpolation obtains the clock signal of phase place between 0 degree to 90 degree, the first clock selection circuit 110 gating first clock signal clk 0, second clock selection circuit 120 gating second clock signal CLK90.If when wishing that interpolation obtains the clock signal of phase place between 90 degree to 180 degree, first clock selection circuit 110 gating the 3rd clock signal clk 180, second clock selection circuit 120 gating second clock signal CLK90, now the first clock selection circuit 110 have switched the clock signal once inputted, and switches to the 3rd clock signal clk 180 by the first clock signal clk 0.If when wishing that interpolation obtains the clock signal of phase place between 180 degree to 270 degree, first clock selection circuit 110 gating the 3rd clock signal clk 180, second clock selection circuit 120 gating the 4th clock signal clk 270, now second clock selection circuit 120 have switched the clock signal once inputted, and switches to the 4th clock signal clk 270 by second clock signal CLK90.If when wishing that interpolation obtains the clock signal of phase place between 270 degree to 0 degree, first clock selection circuit 110 gating first clock signal clk 0, second clock selection circuit 120 gating the 4th clock signal clk 270, now the first clock selection circuit 110 have switched the clock signal inputted, switches to the first clock signal clk 0 by the 3rd clock signal clk 180.
Clock signal after described phase interpolator causes the interpolation exported possibly in the handoff procedure of the clock signal of input produces burr.As shown in Figure 4, when the 3rd clock signal clk 180 is switched to the first clock signal clk 0, the clock signal after interpolation can produce burr at switching point place.Usually burr can be produced in the clock handoff procedure of existing phase interpolator.Due to the impact that the burr that clock cannot be avoided to switch generation outputs signal phase interpolator, it will seriously damage the quality of phase-interpolation.In the application of clock and data recovery loop, it seriously can reduce the performance of clock and data recovery loop, may make loop losing lock (unlock) in extreme situations.
Therefore, be necessary to propose a kind of novel phase interpolator, to overcome the problems referred to above.
[summary of the invention]
The object of the present invention is to provide a kind of novel phase interpolator, it can avoid the impact that the burr that produces in clock handoff procedure outputs signal phase interpolator, and it greatly can improve performance and the stability of system.
In order to solve the problem, the invention provides a kind of phase interpolator, it comprises: clock selecting decoder, carry out decoding for utilizing the interpolation control code of sampling clock to input obtain original set clock selecting code and organize clock selecting code in advance, often organize in clock selecting code and include multiple clock selecting code, the clock selecting code wherein organized in advance in clock selecting code shifts to an earlier date half sampling clock cycle change compared with the clock selecting code in original set clock selecting code respectively; Clock selecting decision circuitry, it is selected to export organize clock selecting code in advance when organizing the change of the clock selecting code in clock selecting code in advance, otherwise, select to export original set clock selecting code; Selecting phasing decoder, carries out decoding for utilizing the interpolation control code of sampling clock to input and obtains Selecting phasing code; First clock selection circuit, it has first input end, the second input and output, first input end receives the first clock signal, second input receives the 3rd clock signal, and the first clock selection circuit selectively exports the first clock signal or the 3rd clock signal according to one group of clock selecting code that clock selecting decision circuitry exports; Second clock selection circuit, it has the 3rd input, four-input terminal and output, 3rd input receives second clock signal, four-input terminal receives the 4th clock signal, and second clock selection circuit selectively exports second clock signal or the 4th clock signal according to one group of clock selecting code that clock selecting decision circuitry exports; Phase-interpolation circuit, its first input end is connected with the output of the first clock selection circuit, its second input is connected with the output of second clock selection circuit, its control end is connected with the output of Selecting phasing decoder, it carries out interpolation according to Selecting phasing code to the clock signal that two inputs input, and exports the clock signal after interpolation.
Further, often organize in clock selecting code and included the first clock selecting code, second clock option code, 3rd clock selecting code and the 4th clock selecting code, wherein organize the first clock selecting code in clock selecting code in advance, second clock option code, 3rd clock selecting code and the 4th clock selecting code are respectively compared with the first clock selecting code in original set clock selecting code, second clock option code, 3rd clock selecting code and the 4th clock selecting code shift to an earlier date half sampling clock cycle change, first clock selection circuit has the first control end and the second control end, the first clock selecting code in one group of clock selecting code that its first control end receive clock selects decision circuitry to export, the 3rd clock selecting code in one group of clock selecting code that its second control end receive clock selects decision circuitry to export, it is effective at the first clock selecting code, and when the 3rd clock selecting code is invalid, export the first clock signal, it is invalid at the first clock selecting code, and when the 3rd clock selecting code is effective, export the 3rd clock signal, second clock selection circuit has the 3rd control end and the 4th control end, second clock option code in one group of clock selecting code that its 3rd control end receive clock selects decision circuitry to export, the 4th clock selecting code in one group of clock selecting code that its 4th control end receive clock selects decision circuitry to export, it is effective in second clock option code, and when the 4th clock selecting code is invalid, export second clock signal, it is invalid in second clock option code, and when the 4th clock selecting code is effective, export the 4th clock signal.
Further, described clock selecting decision circuitry, to be become effectively and the 3rd clock selecting code is invalid from effectively becoming from invalid organizing the first clock selecting code in clock selecting code in advance, or second clock option code from invalid become effectively and the 4th clock selecting code from when effectively becoming invalid, select to export and organize clock selecting code in advance, otherwise, select to export original set clock selecting code; Or, described clock selecting decision circuitry, become effectively from effectively becoming invalid and the 3rd clock selecting code from invalid organizing the first clock selecting code in clock selecting code in advance, or second clock option code from effectively become invalid and the 4th clock selecting code from invalid become effective time, select to export and organize clock selecting code in advance, otherwise, select to export original set clock selecting code.
Further, the phase of the first clock signal and the 3rd clock signal 180 degree, the phase of second clock signal and the 4th clock signal 180 degree, the phase of the first clock signal and second clock signal 90 degree, the phase of the 3rd clock signal and the 4th clock signal 90 degree.
Further, described Selecting phasing code comprises the first weight code and the second weight code, first weight code is the interpolation weights of the clock signal that the first clock selection circuit exports, second weight code is the interpolation weights of the clock signal that second clock selection circuit exports, phase-interpolation circuit carries out interpolation according to the first weight code and the second weight code to the clock signal that two inputs input, and export the clock signal after interpolation, the second weight code be the first weight code and for steady state value.
Further, Selecting phasing decoder comprises Selecting phasing decoding circuit and Selecting phasing sample circuit, the interpolation control code of described Selecting phasing decoding circuit to input is carried out decoding and is obtained serial initial phase option code, and Selecting phasing sample circuit utilizes sampling clock to sample the first weight code and the second weight code that obtain walking abreast to serial initial phase option code.
Further, described Selecting phasing sample circuit is multiple parallel d type flip flops.
Further, described clock selecting decoder comprises clock selecting decoding circuit, first clock selecting sample circuit and second clock select sample circuit, the interpolation control code of described Selecting phasing decoding circuit to input is carried out decoding and is obtained serial initial clock option code, first clock selecting sample circuit utilizes sampling clock to sample the original set clock selecting code obtaining walking abreast to serial initial clock option code, second clock selects sample circuit to utilize the inversion signal of sampling clock to sample the clock selecting of the group in advance code obtaining walking abreast to serial initial clock option code.
Further, the first clock selecting sample circuit is four parallel d type flip flops, and second clock selection sample circuit is four parallel d type flip flops.
Further, during the change of the clock selecting code in original set clock selecting code, Selecting phasing code synchronously changes.
Compared with prior art, phase interpolator of the present invention, when clock switches, group clock selecting code is in advance utilized to carry out clock switching controls, when not carrying out clock and switching, utilize original set clock selecting code to carry out clock selecting control, and the clock selecting code organized in advance in clock selecting code shift to an earlier date half sampling clock cycle change compared with the clock selecting code in original set clock selecting code respectively, can avoid the impact that the burr produced in clock handoff procedure outputs signal phase interpolator like this.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is the functional block diagram of traditional phase interpolator;
Fig. 2 obtains the phase place schematic diagram of a clock signal Sout after illustrating two input clock signal S1 and S2 interpolation;
Fig. 3 is the quadrant operation logic schematic diagram of phase interpolator;
Fig. 4 is the burr generation example of the clock signal in clock handoff procedure after interpolation;
Fig. 5 is the phase interpolator structured flowchart in one embodiment in the present invention;
Fig. 6 is the clock selecting decoding circuit circuit diagram in one embodiment in the present invention;
Fig. 7 is the Selecting phasing decoding circuit circuit diagram in one embodiment in the present invention;
Fig. 8 is clock selection circuit in the present invention and phase-interpolation circuit circuit diagram in one embodiment;
Fig. 9 is the example of clock selecting decoder and phase control decoder conversion table.
[embodiment]
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.Unless stated otherwise, connection herein, be connected, word that the expression that connects is electrically connected all represents and is directly or indirectly electrical connected.
The present invention proposes a kind of novel phase interpolator, it can avoid the impact that the burr that produces in clock handoff procedure outputs signal phase interpolator, and it greatly can improve performance and the stability of system.
Fig. 5 is phase interpolator 200 structured flowchart in one embodiment in the present invention.As shown in Figure 5, described phase interpolator 200 comprises clock selecting decoder 210, clock selecting decision circuitry 220, Selecting phasing decoder 230, first clock selection circuit 240, second clock selection circuit 250 and phase-interpolation circuit 260.
Described clock selecting decoder 210 obtains original set clock selecting code clk_sel for utilizing the interpolation control code clk_ctrl of sampling clock CLK to input to carry out decoding and organizes clock selecting code clk_sel_pre in advance.Often organize in clock selecting code and include multiple clock selecting code, the clock selecting code wherein organized in advance in clock selecting code clk_sel_pre shifts to an earlier date half sampling clock cycle change compared with the clock selecting code in original set clock selecting code clk_sel respectively.Described interpolation control code clk_ctrl can be provided by peripheral control unit, and this peripheral control unit can control the clock signal Sout that this phase interpolator exports the phase place expected.When applying, this peripheral control unit wishes that described phase interpolator exports the clock signal of x phase place, and so this peripheral control unit then sends interpolation control code corresponding to this x phase place, obtains the clock signal of x phase place to make described phase interpolator interpolation.
Described clock selecting decision circuitry 220 is when organizing the change of the clock selecting code in clock selecting code clk_sel_pre in advance, select to export and organize clock selecting code clk_sel_pre in advance as selected group of clock selecting code clk_sel_m, otherwise, select to export original set clock selecting code clk_sel as selected group of clock selecting code clk_sel_m.Selecting phasing decoder 230 obtains Selecting phasing code ph_sel for utilizing the interpolation control code clk_ctrl of sampling clock CLK to input to carry out decoding.First clock selection circuit 240 has first input end, the second input and output, and first input end receives the first clock signal clk 0, second input and receives the 3rd clock signal clk 180.One group of clock selecting code clk_sel_m that first clock selection circuit 240 exports according to clock selecting decision circuitry 220 selectively exports the first clock signal clk 0 or the 3rd clock signal clk 180.Second clock selection circuit 250 has the 3rd input, four-input terminal and output, and the 3rd input receives second clock signal CLK90, and four-input terminal receives the 4th clock signal clk 270.One group of clock selecting code clk_sel_m that second clock selection circuit 250 exports according to clock selecting decision circuitry 220 selectively exports second clock signal CLK90 or the 4th clock signal clk 270.
Phase-interpolation circuit 260, its first input end is connected with the output of the first clock selection circuit 240, its second input is connected with the output of second clock selection circuit 250, its control end is connected with the output of Selecting phasing decoder 230, it carries out interpolation according to Selecting phasing code ph_sel to the clock signal that two inputs input, and exports the clock signal Sout after interpolation.
In one embodiment, the phase of the first clock signal clk 0 and the 3rd clock signal clk 180 180 degree, the phase of second clock signal CLK90 and the 4th clock signal clk 270 180 degree, the phase of the first clock signal clk 0 and second clock signal CLK90 90 degree, the phase of the 3rd clock signal clk 180 and the 4th clock signal clk 270 90 degree, the phase place of the first clock signal clk 0 is 0.Like this, phase-interpolation circuit 260 can obtain the clock signal of arbitrary phase.
In one embodiment, organize in advance in clock selecting code clk_sel_pre and include the first clock selecting code clk0_sel_pre, second clock option code clk90_sel_pre, the 3rd clock selecting code clk180_sel_pre and the 4th clock selecting code clk270_sel_pre, in original set clock selecting code clk_sel, include the first clock selecting code clk0_sel, second clock option code clk90_sel, the 3rd clock selecting code clk180_sel and the 4th clock selecting code clk270_sel.Organize the first clock selecting code clk0_sel_pre in clock selecting code clk_sel_pre in advance, second clock option code clk90_sel_pre, 3rd clock selecting code clk180_sel_pre and the 4th clock selecting code clk270_sel_pre comparatively includes the first clock selecting code clk0_sel in original set clock selecting code respectively, second clock option code clk90_sel, 3rd clock selecting code clk180_sel and the 4th clock selecting code clk270_sel shifts to an earlier date half sampling clock cycle change.
First clock selection circuit 240 has the first control end and the second control end, the first clock selecting code clk0_sel_m in one group of clock selecting code clk_sel_m that its first control end receive clock selects decision circuitry 220 to export, the 3rd clock selecting code clk180_sel_m in one group of clock selecting code that its second control end receive clock selects decision circuitry 220 to export.First clock selection circuit 240 is effective at the first clock selecting code clk0_sel_m, and when the 3rd clock selecting code clk180_sel_m is invalid, export the first clock signal clk 0, it is invalid at the first clock selecting code clk0_sel_m, and when the 3rd clock selecting code clk180_sel_m is effective, export the 3rd clock signal clk 180.
Second clock selection circuit 250 has the 3rd control end and the 4th control end, the 4th clock selecting code clk270_sel_m in second clock option code clk90_sel_m in one group of clock selecting code clk_sel_m that its 3rd control end receive clock selects decision circuitry 220 to export, one group of clock selecting code clk_sel_m that the 4th control end receive clock selects decision circuitry 220 to export.Second clock selection circuit 250 is effective at second clock option code clk90_sel_m, and when the 4th clock selecting code clk270_sel_m is invalid, export second clock signal CLK90, it is invalid at second clock option code clk90_sel_m, and when the 4th clock selecting code clk270_sel_m is effective, export the 4th clock signal clk 270.
In the embodiment had, organize in advance the first clock selecting code clk0_sel_pre in clock selecting code clk_sel_pre from invalid become effectively and the 3rd clock selecting code clk180_sel_pre from when effectively becoming invalid, if or adopting original clock option code clk_sel to control the first clock selection circuit 240 carries out clock switching, then the clock signal Sout after interpolation can be caused to produce burr in clock switching place.Organize in advance the second clock option code clk90_sel_pre in clock selecting code clk_sel_pre from invalid become effectively and the 4th clock selecting code clk270_sel_pre from when effectively becoming invalid, if or adopting original clock option code clk_sel to control second clock selection circuit 250 carries out clock switching, then the clock signal Sout after interpolation can be caused to produce burr in clock switching place.
Therefore, in order to overcome this problem, described clock selecting decision circuitry 220, to be become effectively and the 3rd clock selecting code clk180_sel_pre is invalid from effectively becoming from invalid organizing the first clock selecting code clk0_sel_pre in clock selecting code clk_sel_pre in advance, or second clock option code clk90_sel_pre from invalid become effectively and the 4th clock selecting code clk270_sel_pre from when effectively becoming invalid, select to export and organize clock selecting code clk_sel_pre in advance, in other cases, all select to export original set clock selecting code clk_sel.Like this, when the 3rd clock signal clk 180 is switched to the first clock signal clk 0 by needs, half period completes switching in the first clock selection circuit 240 in advance, too in advance in the change half period of Selecting phasing code, same, when the 4th clock signal clk 270 is switched to second clock signal CLK90 by needs, half period completes switching in second clock selection circuit 250 in advance, too in advance in the change half period of Selecting phasing code, thus can avoid producing burr in clock handoff procedure.
In another embodiment, organize in advance the first clock selecting code clk0_sel_pre in clock selecting code clk_sel_pre from effectively become invalid and the 3rd clock selecting code clk180_sel_pre from invalid become effective time, if or adopting original clock option code clk_sel to control the first clock selection circuit 240 carries out clock switching, then the clock signal Sout after interpolation can be caused to produce burr in clock switching place.Organize in advance the second clock option code clk90_sel_pre in clock selecting code clk_sel_pre from effectively become invalid and the 4th clock selecting code clk270_sel_pre from invalid become effective time, if or adopting original clock option code clk_sel to control second clock selection circuit 250 carries out clock switching, then the clock signal Sout after interpolation can be caused to produce burr in clock switching place.
Therefore, in order to overcome this problem, described clock selecting decision circuitry 220, become effectively from effectively becoming invalid and the 3rd clock selecting code clk180_sel_pre from invalid organizing the first clock selecting code clk0_sel_pre in clock selecting code clk_sel_pre in advance, or second clock option code clk90_sel_pre from effectively become invalid and the 4th clock selecting code clk270_sel_pre from invalid become effective time, select to export and organize clock selecting code clk_sel_pre in advance, in other cases, all select to export original set clock selecting code clk_sel.Like this, when the first clock signal clk 0 is switched to the 3rd clock signal clk 180 by needs, half period completes switching in the first clock selection circuit 240 in advance, too in advance in the change half period of Selecting phasing code, same, when second clock signal CLK90 is switched to the 4th clock signal clk 270 by needs, half period completes switching in second clock selection circuit 250 in advance, too in advance in the change half period of Selecting phasing code, thus can avoid producing burr in clock handoff procedure.
In one embodiment, described Selecting phasing code ph_sel comprises the first weight code bit_b<15:0> and the second weight code bit<15:0>, second weight code be the first weight code and for steady state value, Selecting phasing decoder 230 comprises Selecting phasing decoding circuit and Selecting phasing sample circuit.The interpolation control code clk_ctrl of described Selecting phasing decoding circuit to input carries out decoding and obtains serial initial phase option code, and described Selecting phasing sample circuit utilizes sampling clock CLK to sample the first weight code bit_b<15:0> and the second weight code bit<15:0> that obtain walking abreast to serial initial clock option code.First weight code is the interpolation weights of the clock signal that the first clock selection circuit 240 exports, second weight code is the interpolation weights of the clock signal that second clock selection circuit 250 exports, phase-interpolation circuit 260 carries out interpolation according to the first weight code bit_b<15:0> and the second weight code bit<15:0> to the clock signal that two inputs input, and exports the clock signal after interpolation.Fig. 7 is clock selecting decoding circuit 230 circuit diagram in one embodiment in the present invention.As shown in Figure 7, d type flip flop DFF2<15:0> is Selecting phasing sample circuit.
In one embodiment, described clock selecting decoder 220 comprises clock selecting decoding circuit, the first clock selecting sample circuit, second clock selection sample circuit.The interpolation control code clk_ctrl of described Selecting phasing decoding circuit 220 to input carries out decoding and obtains serial initial clock option code.First clock selecting sample circuit utilizes sampling clock clk to sample the original set clock selecting code obtaining walking abreast to serial initial clock option code.Second clock selects sample circuit to utilize the inversion signal clk_b of sampling clock clk to sample the clock selecting of the group in advance code obtaining walking abreast to serial initial clock option code.Fig. 6 is clock selecting decoding circuit 210 circuit diagram in one embodiment in the present invention.As shown in Figure 6, d type flip flop DFF1<3:0> is the first clock selecting sample circuit, and d type flip flop DFF3<3:0> is that second clock selects sample circuit.
Fig. 8 is clock selection circuit in the present invention and phase-interpolation circuit circuit diagram in one embodiment.As shown in Figure 8, the first clock selecting unit 240 comprises the first gating unit and the second gating unit.First clock selecting code clk0_sel_m controls the first gating unit whether gating, the input of this first gating unit connects the first clock signal clk 0,3rd clock selecting code clk0_sel_m controls the second gating unit whether gating, the output of input connection the 3rd clock signal clk 180, first gating unit of this second gating unit is connected with the output of the second gating unit.
Second clock selected cell 250 comprises the 3rd gating unit and the 4th gating unit.Second clock option code clk90_sel_m controls the 3rd gating unit whether gating, the input of the 3rd gating unit connects second clock signal CLK90,4th clock selecting code clk270_sel_m controls the 4th gating unit whether gating, the output of input connection the 4th clock signal clk the 270, three gating unit of the 4th gating unit is connected with the output of the 4th gating unit.
Phase-interpolation circuit 260 comprises the first buffer BUF1, the second buffer BUF2 and output buffer.The input of the first buffer is connected with the output of the first clock selecting unit 240, the output of the first buffer is connected with the output of the second buffer, the input of the second buffer is connected with the output of second clock selected cell 250, and the input of output buffer is connected with the output of the second buffer.First weight code inputs the control end of the first buffer BUF1 to carry out weight setting, and the second weight code inputs the control end of the second buffer BUF2 to carry out weight setting.
Fig. 9 is the example of clock selecting decoder and phase control decoder conversion table.Clk_ctrl mono-hurdle, left side is interpolation control code, middle clk_sel mono-hurdle is one group of original clock option code, first in four is the first clock selecting code clk0_sel, second is second clock option code clk90_sel, 3rd the 3rd clock selecting code clk270_sel, the 4th is the 4th clock selecting code clk270_sel.Bit_b<15:0> is the first weight code of 16, and bit<15:0> is the second weight code of 16.Clock selecting decoder and phase control decoder carry out decoding according to this conversion table.
In the present invention, clock selecting control clk0_sel, clk90_sel, clk180_sel, clk270_sel and Selecting phasing control bit<15:0> and bit_b<15:0> are by same clock synchronous.The meaning of control logic clock synchronous is adopted to be the generation of race hazard in the process avoiding Digital Logic to change and burr.
Because synchronous logic conversion is by clock synchronous, there is the delay of a ck-to-q in the reaction time of control logic relative to clock.6 ' b01000 is transformed to for clk_ctl<5:0>=6 ' b001111, after decoder, after synchronous by clock clk, clk0_sel becomes 0 from 1, clk180_sel becomes 1 from 0, complete clock to switch, simultaneously because the output bit_b<15:0> of Selecting phasing decoder becomes 16 ' 0000000000000000 from 16 ' b1000000000000000.If the change of the change of control phase option code and clock selecting code is all the time delay of a clk-to-q relative to clk, as shown in Figure 8, the weight of BUF1 becomes 0, that is BUF1 and phase interpolator export and disconnect, and the burr produced in such clock handoff procedure can not be observed in the output of phase interpolator.
But, if consider that clk_ctl<5:0> is transformed to 6 ' b001111 from 6 ' b01000, phase control code becomes 16 ' b1000000000000000 from bit_b<15:0> from 16 ' b0000000000000000, clk180_sel becomes 0, clk0_sel from 1 and becomes 1 from 0 simultaneously.The change of Selecting phasing code and clock selecting code is also the time delay of a clk-to-q relative to clk.The process switched due to clock completes from being disconnected to the while that connection, phase interpolator exporting at BUF1, the burr produced in clock handoff procedure just embodies in the output of phase interpolator, and the clock that is phase interpolator exports will have shake or a burr produces.
As shown in Figure 6, it selects sample circuit DFF3<3:0> by increasing second clock, and adopts the output of reverse clock clkb to clock selecting decoding circuit of clk to sample.Because the logic of clock selecting decoding circuit is fairly simple, the response time, so adopt the reverse clock (supposing that the duty ratio of clk is 50%) of clk, so can to shift to an earlier date half sampling clock cycle perceived in the switching of clock than very fast.
6 ' b001111 is transformed to from 6 ' b01000 equally for clk_ctl<5:0>, by DFF3<3:0>, the output clk_sel<3:0> of clock selecting decoder is sampled, obtain clk0_sel_pre, clk90_sel_pre, clk180_sel_pre, clk270_sel_pre.
Because DFF3<3:0> is triggered by clkb, so clk0_sel_pre, clk90_sel_pre, clk180_sel_pre, clk270_sel_pre is than the output clk0_sel of DFF1<3:0>, clk90_sel, clk180_sel, clk270_sel shift to an earlier date half period change.
Eight of DFF1<3:0> and DFF3<3:0> outputs are input to clock selecting decision circuitry 270, obtain final one group of clock selecting code clk0_sel_m, clk90_sel_m, clk180_sel_m, clk270_sel_m control CLK0, clock between CLK90, CLK180, CLK270 switches.
The basis for estimation of clock selecting decision circuitry 270 is: when clk0_sel_pre becomes 1 (effectively) from 0 (invalid), and clk180_sel_pre is when becoming 0 from 1, or when clk90_sel_pre becomes 1 from 0, and when clk270_sel_pre becomes 0 from 1, by clk0_sel_pre, clk90_sel_pre, clk180_sel_pre, clk270_sel_pre select to export, otherwise export clk0_sel, clk90_sel, clk180_sel, clk270_sel.
When clk_ctl<5:0> is changed to 6 ' b001111 from 6 ' b01000, clock selecting comparatively can shift to an earlier date half period change by Selecting phasing code.That is the process that clock switches completes during bit_b<15:0> is 16 ' b0000000000000000.After half period, bit_b<15:0> is just transformed to 16 ' b1000000000000000.During clock switching, the output of BUF1 and phase interpolator disconnects, so the impact that the burr shielding clock switching exports phase interpolator.
In the present invention, " connection ", be connected, word that " companys ", the expression such as " connecing " are electrical connected, if no special instructions, then represent direct or indirect electric connection.
It is pointed out that the scope be familiar with person skilled in art and any change that the specific embodiment of the present invention is done all do not departed to claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (10)
1. a phase interpolator, is characterized in that, it comprises:
Clock selecting decoder, carry out decoding for utilizing the interpolation control code of sampling clock to input obtain original set clock selecting code and organize clock selecting code in advance, often organize in clock selecting code and include multiple clock selecting code, the clock selecting code wherein organized in advance in clock selecting code shifts to an earlier date half sampling clock cycle change compared with the clock selecting code in original set clock selecting code respectively;
Clock selecting decision circuitry, it is selected to export organize clock selecting code in advance when organizing the change of the clock selecting code in clock selecting code in advance, otherwise, select to export original set clock selecting code;
Selecting phasing decoder, carries out decoding for utilizing the interpolation control code of sampling clock to input and obtains Selecting phasing code;
First clock selection circuit, it has first input end, the second input and output, first input end receives the first clock signal, second input receives the 3rd clock signal, and the first clock selection circuit selectively exports the first clock signal or the 3rd clock signal according to one group of clock selecting code that clock selecting decision circuitry exports;
Second clock selection circuit, it has the 3rd input, four-input terminal and output, 3rd input receives second clock signal, four-input terminal receives the 4th clock signal, and second clock selection circuit selectively exports second clock signal or the 4th clock signal according to one group of clock selecting code that clock selecting decision circuitry exports;
Phase-interpolation circuit, its first input end is connected with the output of the first clock selection circuit, its second input is connected with the output of second clock selection circuit, its control end is connected with the output of Selecting phasing decoder, it carries out interpolation according to Selecting phasing code to the clock signal that two inputs input, and exports the clock signal after interpolation.
2. phase interpolator according to claim 1, it is characterized in that, often organize in clock selecting code and included the first clock selecting code, second clock option code, the 3rd clock selecting code and the 4th clock selecting code, the first clock selecting code, second clock option code, the 3rd clock selecting code and the 4th clock selecting code wherein organized in advance in clock selecting code shifts to an earlier date half sampling clock cycle change compared with the first clock selecting code in original set clock selecting code, second clock option code, the 3rd clock selecting code and the 4th clock selecting code respectively
First clock selection circuit has the first control end and the second control end, the first clock selecting code in one group of clock selecting code that its first control end receive clock selects decision circuitry to export, the 3rd clock selecting code in one group of clock selecting code that its second control end receive clock selects decision circuitry to export, it is effective at the first clock selecting code, and when the 3rd clock selecting code is invalid, export the first clock signal, it is invalid at the first clock selecting code, and when the 3rd clock selecting code is effective, export the 3rd clock signal;
Second clock selection circuit has the 3rd control end and the 4th control end, second clock option code in one group of clock selecting code that its 3rd control end receive clock selects decision circuitry to export, the 4th clock selecting code in one group of clock selecting code that its 4th control end receive clock selects decision circuitry to export, it is effective in second clock option code, and when the 4th clock selecting code is invalid, export second clock signal, it is invalid in second clock option code, and when the 4th clock selecting code is effective, export the 4th clock signal.
3. phase interpolator according to claim 2, is characterized in that,
Described clock selecting decision circuitry, to be become effectively and the 3rd clock selecting code is invalid from effectively becoming from invalid organizing the first clock selecting code in clock selecting code in advance, or second clock option code from invalid become effectively and the 4th clock selecting code from when effectively becoming invalid, select to export and organize clock selecting code in advance, otherwise, select to export original set clock selecting code; Or
Described clock selecting decision circuitry, become effectively from effectively becoming invalid and the 3rd clock selecting code from invalid organizing the first clock selecting code in clock selecting code in advance, or second clock option code from effectively become invalid and the 4th clock selecting code from invalid become effective time, select to export and organize clock selecting code in advance, otherwise, select to export original set clock selecting code.
4. phase interpolator according to claim 1, it is characterized in that, the phase of the first clock signal and the 3rd clock signal 180 degree, the phase of second clock signal and the 4th clock signal 180 degree, the phase of the first clock signal and second clock signal 90 degree, the phase of the 3rd clock signal and the 4th clock signal 90 degree.
5. phase interpolator according to claim 1, is characterized in that, described Selecting phasing code comprises the first weight code and the second weight code,
First weight code is the interpolation weights of the clock signal that the first clock selection circuit exports,
Second weight code is the interpolation weights of the clock signal that second clock selection circuit exports,
Phase-interpolation circuit carries out interpolation according to the first weight code and the second weight code to the clock signal that two inputs input, and exports the clock signal after interpolation,
Second weight code be the first weight code and for steady state value.
6. phase interpolator according to claim 5, is characterized in that, Selecting phasing decoder comprises Selecting phasing decoding circuit and Selecting phasing sample circuit,
The interpolation control code of described Selecting phasing decoding circuit to input is carried out decoding and is obtained serial initial phase option code, and Selecting phasing sample circuit utilizes sampling clock to sample the first weight code and the second weight code that obtain walking abreast to serial initial phase option code.
7. phase interpolator according to claim 6, is characterized in that, described Selecting phasing sample circuit is multiple parallel d type flip flops.
8. phase interpolator according to claim 1, is characterized in that, described clock selecting decoder comprises clock selecting decoding circuit, the first clock selecting sample circuit and second clock and selects sample circuit,
The interpolation control code of described Selecting phasing decoding circuit to input is carried out decoding and is obtained serial initial clock option code, first clock selecting sample circuit utilizes sampling clock to sample the original set clock selecting code obtaining walking abreast to serial initial clock option code, and second clock selects sample circuit to utilize the inversion signal of sampling clock to sample the clock selecting of the group in advance code obtaining walking abreast to serial initial clock option code.
9. phase interpolator according to claim 8, is characterized in that, the first clock selecting sample circuit is four parallel d type flip flops, and second clock selection sample circuit is four parallel d type flip flops.
10. according to the arbitrary described phase interpolator of claim 1-9, it is characterized in that, during the change of the clock selecting code in original set clock selecting code, Selecting phasing code synchronously changes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510260684.3A CN104821808B (en) | 2015-05-20 | 2015-05-20 | Phase interpolator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510260684.3A CN104821808B (en) | 2015-05-20 | 2015-05-20 | Phase interpolator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104821808A true CN104821808A (en) | 2015-08-05 |
| CN104821808B CN104821808B (en) | 2017-08-29 |
Family
ID=53732001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510260684.3A Active CN104821808B (en) | 2015-05-20 | 2015-05-20 | Phase interpolator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104821808B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI638522B (en) * | 2016-11-02 | 2018-10-11 | 瑞昱半導體股份有限公司 | Phase adjustment circuit and control method |
| CN113364433A (en) * | 2021-06-25 | 2021-09-07 | 中国电子科技集团公司第二十四研究所 | High-linearity phase interpolation circuit and method and electronic equipment |
| CN116743121A (en) * | 2023-08-16 | 2023-09-12 | 沐曦集成电路(上海)有限公司 | Clock selection system for digital frequency synthesizer |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090238307A1 (en) * | 2008-03-21 | 2009-09-24 | Broadcom Corporation | Digitally controlled phase interpolator circuit |
| CN101577617A (en) * | 2008-05-08 | 2009-11-11 | 台湾积体电路制造股份有限公司 | Fast locking clock and data recovery |
| US7629828B1 (en) * | 2007-04-27 | 2009-12-08 | Zilog, Inc. | Glitch-free clock multiplexer that provides an output clock signal based on edge detection |
| TW201034389A (en) * | 2009-03-10 | 2010-09-16 | Realtek Semiconductor Corp | Method and apparatus for preventing phase interpolation circuit from glitch during clock switching |
| CN204578499U (en) * | 2015-05-20 | 2015-08-19 | 灿芯半导体(上海)有限公司 | Phase interpolator |
-
2015
- 2015-05-20 CN CN201510260684.3A patent/CN104821808B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7629828B1 (en) * | 2007-04-27 | 2009-12-08 | Zilog, Inc. | Glitch-free clock multiplexer that provides an output clock signal based on edge detection |
| US20090238307A1 (en) * | 2008-03-21 | 2009-09-24 | Broadcom Corporation | Digitally controlled phase interpolator circuit |
| CN101577617A (en) * | 2008-05-08 | 2009-11-11 | 台湾积体电路制造股份有限公司 | Fast locking clock and data recovery |
| TW201034389A (en) * | 2009-03-10 | 2010-09-16 | Realtek Semiconductor Corp | Method and apparatus for preventing phase interpolation circuit from glitch during clock switching |
| CN204578499U (en) * | 2015-05-20 | 2015-08-19 | 灿芯半导体(上海)有限公司 | Phase interpolator |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI638522B (en) * | 2016-11-02 | 2018-10-11 | 瑞昱半導體股份有限公司 | Phase adjustment circuit and control method |
| CN113364433A (en) * | 2021-06-25 | 2021-09-07 | 中国电子科技集团公司第二十四研究所 | High-linearity phase interpolation circuit and method and electronic equipment |
| CN113364433B (en) * | 2021-06-25 | 2022-09-27 | 中国电子科技集团公司第二十四研究所 | High-linearity phase interpolation circuit and method and electronic equipment |
| CN116743121A (en) * | 2023-08-16 | 2023-09-12 | 沐曦集成电路(上海)有限公司 | Clock selection system for digital frequency synthesizer |
| CN116743121B (en) * | 2023-08-16 | 2023-10-27 | 沐曦集成电路(上海)有限公司 | Clock selection system for digital frequency synthesizer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104821808B (en) | 2017-08-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102012717B (en) | Clock switching method and device | |
| US10476707B2 (en) | Hybrid half/quarter-rate DFE | |
| CN110661513B (en) | Digital pulse width modulation circuit and working method | |
| US20080094113A1 (en) | Fraction-N Frequency Divider and Method Thereof | |
| CN103957005A (en) | Time-digital converter, full-digital phase-locked loop circuit and method | |
| TW201004152A (en) | System and method of controlling power consumption in a digital phase locked loop (DPLL) | |
| CN110120798B (en) | DPWM circuit with double-edge trigger mixed structure and control method thereof | |
| EP3114792B1 (en) | Clock recovery circuit for multiple wire data signals | |
| US9154291B2 (en) | Differential signal skew adjustment method and transmission circuit | |
| CN104821808A (en) | Phase interpolator | |
| CN204578499U (en) | Phase interpolator | |
| CN104821807A (en) | Improved phase interpolator | |
| EP3350928B1 (en) | High-speed programmable clock divider | |
| US8811559B1 (en) | Timing recovery circuit and receiver circuit including the same | |
| CN204578498U (en) | The phase interpolator improved | |
| WO2021008362A1 (en) | Digital frequency generator and state switching method therefor | |
| US20190007056A1 (en) | Frequency divider circuit, demultiplexer circuit, and semiconductor integrated circuit | |
| CN201917845U (en) | Clock switching device | |
| KR100617957B1 (en) | Method of sampling reverse data and reverse data sampling circuit using the same | |
| CN108233898B (en) | Multi-clock dynamic switching circuit | |
| CN112600550A (en) | Asynchronous clock selection circuit based on clock domain crossing and switching method thereof | |
| EP3748859A1 (en) | Dac device having positive dac and negative dac and associated digital-to-analog converting method | |
| CN115441865A (en) | Phase interpolator and phase interpolation method of clock signal | |
| TW200935741A (en) | Clock circuit with clock transfer capability and method | |
| JP2008066940A (en) | Clock selection circuit and clock data recovery circuit equipped with the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Phase interpolator Effective date of registration: 20180420 Granted publication date: 20170829 Pledgee: Wick International Holding Co., Ltd. Pledgor: Brite Semiconductor (Shanghai) Corporation Registration number: 2018310000019 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20190416 Granted publication date: 20170829 Pledgee: Wick International Holding Co., Ltd. Pledgor: Brite Semiconductor (Shanghai) Corporation Registration number: 2018310000019 |
|
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 201203 7th floor, building 2, 1158 Zhangdong Road, Zhangjiang hi tech, Pudong New Area, Shanghai Patentee after: Canxin semiconductor (Shanghai) Co.,Ltd. Address before: 201203 7th floor, building 2, 1158 Zhangdong Road, Zhangjiang hi tech, Pudong New Area, Shanghai Patentee before: BRITE SEMICONDUCTOR (SHANGHAI) Corp. |