JP2008066940A - Clock selection circuit and clock data recovery circuit equipped with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate glitch attributed to output switching of a clock selection circuit. <P>SOLUTION: A clock selection circuit is provided with two clock selection parts 11a and 11b for receiving a plurality of clock signals which are deviated in phase from each other and selectively outputting one or more signal from among the clock signals, a clock switch part 12 for selecting between the clock selection parts 11a and 11b and outputting a clock signal outputted by the selected clock selection part, and a control unit 13 for controlling the clock selection parts 11a and 11b and the clock switch part 12. The control unit 13 instructs re-selection of the clock signal to one of the two clock selection parts 11a and 11b which is not selected by the clock switch part 12 and designates the clock switch part 12 to switch outputs after instruction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a clock selection circuit, and more particularly to a clock selection circuit suitable for a clock data recovery circuit, a delay locked loop circuit, and the like, which selectively outputs one or more clock signals out of phase with each other. .

  In a data transmission system, a skew occurs between a received data signal and a received clock signal due to fluctuations in power supply voltage, transmission delay in a communication path, and the like. For this reason, on the receiving side, a clock data recovery circuit or the like is used to select a multi-phase clock signal generated from the reference clock signal having the optimal timing for data latch based on the received data signal. The data latch clock signal is recovered. A clock selection circuit is used to select any one of the plurality of clock signals out of phase with each other.

  The clock selection circuit has a circuit configuration in which a large number of switching elements for signal selection are connected in parallel. For this reason, a relatively large capacitance is parasitic on the common connection point of these switching elements. Then, due to this parasitic capacitance, the signal waveform is rounded at the common connection point, and the signal delay of the clock selection circuit becomes large. Furthermore, a glitch may be induced when the output of the clock selection circuit is switched due to this signal delay. This glitch adversely affects subsequent signal processing, and there is a possibility that data cannot be latched normally in the clock data recovery circuit.

  The glitch generated at the output of the clock selection circuit will be described with reference to the timing chart of FIG. It is assumed that the clock signal CK1 input to the clock selection circuit is selected and output as the clock signal CKout. The rise of the clock signal CK1 at time T1 appears later in the clock signal CKout at time T2 with a delay of ΔT1. That is, the clock signal input to the clock selection circuit is output with a delay of time ΔT1. Here, it is assumed that the output of the clock selection circuit is switched to the clock signal CK2 at the rising timing of the clock signal CKout at time T2. However, the output does not switch instantaneously at time T2, but actually switches to time T3 with a delay of time ΔT2 (ΔT2 << ΔT1). The signal level of the clock signal CK1 changes during this delay, and the signal levels of the clock signals CK1 and CK2 are inconsistent at time T3. This signal level mismatch induces a glitch in the clock signal CKout.

  If the signal delay of the clock selection circuit can be reduced, it is possible to prevent glitches from being induced in the clock signal output from the clock selection circuit even if there is an output switching delay. Conventionally, in order to suppress the signal delay of the clock selection circuit, a plurality of input clock signals are divided into a plurality of groups and each is supplied to a plurality of signal selection circuits, and the clock signals output from these signal selection circuits are An arbitrary one clock signal is finally selected by giving it to the signal selection circuit at the next stage (see, for example, Patent Document 1). By connecting the signal selection circuits in multiple stages in this way, the number of parallel connection of the switching elements for signal selection in each signal selection circuit is reduced to reduce the parasitic capacitance at the common connection point, and each signal selection circuit and thus the clock selection circuit The overall signal delay can be suppressed.

Also, an output control circuit that outputs a new clock signal after temporarily holding the output clock signal at a low level when switching of the output clock signal is instructed to eliminate glitches from the clock signal is known (for example, , See Patent Document 2).
JP 2003-179487 A JP 2004-166194 A

  In recent years, the data communication speed between devices has been increasing. For this reason, even if the absolute amount of the signal delay of the clock selection circuit is reduced by the conventional method, the clock signal frequency becomes increasingly faster, whereas the signal delay of the clock selection circuit is constant regardless of the clock signal frequency. Therefore, the relative amount of signal delay of the clock selection circuit with respect to one cycle of the clock signal increases. Further, since it is necessary to use a multi-phase clock signal in order to obtain a more accurate latch timing in the clock data recovery circuit, the relative amount of signal delay of the clock selection circuit also increases. In order to eliminate the glitch from the output of the clock selection circuit, it is necessary to switch the output when the signal levels of the clock signal currently being output and the clock signal to be selected match. However, as the frequency increases, the interval in which the signal levels of these two clock signals coincide with each other becomes narrower, and output switching control becomes very difficult. For this reason, it is difficult for the conventional method to cope with the high-speed system.

  Furthermore, parallel processing systems using multiphase clock signals are common in order to cope with recent increases in communication speed. In such a system, a plurality of clock selection circuits are connected in parallel, a plurality of input clock signals are supplied to each clock selection circuit, and a clock signal output from each clock selection circuit is arranged and output. There is a need. However, in such a circuit configuration, the wiring structure of the input portion of the clock signal is complicated and the parasitic capacitance is increased, resulting in a rounded signal waveform and a disturbance in the phase difference.

  In view of the above problems, it is an object of the present invention to eliminate a glitch caused by output switching in a clock selection circuit, and to simplify a wiring structure of an input portion and reduce signal delay particularly in a multi-output clock selection circuit. .

  Means taken by the present invention to solve the above-described problem is that the clock selection circuit receives a plurality of clock signals out of phase with each other and selectively outputs one or more of the clock signals. Receiving one of the clock signals and selectively outputting one or more of the clock signals; and selecting one of the first and second clock selection units; A clock switching unit that outputs a clock signal output from the selected one, and a control unit that controls the first and second clock selection units and the clock switching unit are provided. Here, the control unit instructs reselection of the clock signal to the one of the first and second clock selection units that is not selected by the clock switching unit, and after the instruction, the clock switching unit Is instructed to switch output.

  According to this, when the output of the clock selection circuit is switched, even if a glitch occurs in the output of the first and second clock selection units instructed to reselect the clock signal, the output is clock-switched. Therefore, the glitch does not appear in the output of the clock selection circuit.

  Specifically, the control unit has the same request signal among a first request signal indicating a request for advancing the phase of a clock signal output from the clock selection circuit and a second request signal indicating a request for delaying the phase. Is received for a predetermined number of times, the clock selection unit not selected by the clock switching unit is instructed to reselect the clock signal, and when the same request signal is received at least once, the clock Instructs the switching unit to switch the output. Preferably, the control unit receives each of the first and second request signals when the same request signal among the first and second request signals is continuously received the predetermined number of times. When both are larger than a predetermined value, the clock selection unit not selected by the clock switching unit is instructed to select a clock signal having an opposite phase.

  Further, specifically, the control unit is configured for each of a first request signal indicating a request for advancing the phase of a clock signal output from the clock selection circuit and a second request signal indicating a request for delaying the phase. When the difference value of the number of receptions in a predetermined period exceeds a predetermined value, the clock selection unit not selected by the clock switching unit is instructed to reselect the clock signal. Preferably, the control unit instructs the clock selection unit not selected by the clock switching unit to reselect a clock signal whose phase is shifted by an amount corresponding to the difference value. To do.

  On the other hand, the means provided by the present invention is a clock selection circuit that receives a plurality of clock signals out of phase with each other and selectively outputs a plurality of clock signals out of the clock signals. N (N is an integer greater than or equal to 2) signal groups divided by N (M is an integer greater than or equal to 2), and M clock signals belonging to the corresponding signal group are arranged in phase order. It is assumed that N clock selection units for selectively outputting any one of the supplied M clock signals according to a common control signal are provided.

  According to this, the wiring structure of the input portion in the multi-output clock selection circuit can be simplified, and the signal delay of the clock selection circuit can be reduced.

  Preferably, the clock selection circuit includes a clock alignment unit that receives N clock signals output from the N clock selection units and outputs the N clock signals arranged in phase order. To do.

  As described above, according to the present invention, even when the number of input clock signals is increased or the frequency of the clock signal is increased, glitches caused by output switching of the clock selection circuit can be eliminated. Further, the wiring structure of the input portion of the multi-output clock selection circuit can be simplified and the signal delay can be reduced.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 shows a configuration of a clock selection circuit according to the first embodiment. The clock selection circuit receives 45 clock signals CKin1 to CKin45 that are out of phase with each other, and selectively outputs five of them as clock signals CKout1 to CKout5. Specifically, the clock selection circuit includes two clock selection units 11a and 11b, a clock switching unit 12, and a control unit 13.

  The clock selection unit 11a receives the clock signals CKin1 to CKin45 and selectively outputs five of the clock signals CKin1 to CKin45 as clock signals CKa1 to CKa5 according to the phase selection signal PHa. Similarly, the clock selection unit 11b receives the clock signals CKin1 to CKin45 and selectively outputs five of the clock signals CKin1 to CKin45 as the clock signals CKb1 to CKb5 according to the phase selection signal PHb. These clock selection units 11a and 11b may be, for example, those related to the above-described prior art or may be a clock selection circuit according to a second embodiment described later.

  The clock switching unit 12 receives the clock signals CKa1 to CKa5 and the clock signals CKb1 to CKb5, and selectively outputs any one of these signal groups as the clock signals CKout1 to CKout5 according to the switching control signal CH. Specifically, the clock switching unit 12 receives a clock signal CKak (k is an integer from 1 to 5) and a clock signal CKbk, and outputs five 2: 1 selectors (not shown) that output the clock signal CKoutk. ).

  The control unit 13 synchronizes with any one of the clock signals CKout1 to CKout5 based on the number of receptions of the signal UP that represents a request to advance the phase of the clock signals CKout1 to CKout5 and the signal DN that represents a request to delay the phase. The selection signals PHa and PHb are output to control the clock selection units 11a and 11b, respectively. In addition, the control unit 13 outputs a switching control signal CH to control the clock switching unit 12. In particular, the control unit 13 instructs the clock selection unit 11a and 11b that is not selected by the clock switching unit 12 to reselect the clock signal, and outputs the clock switching unit 12 after the instruction is given. Is instructed to switch. As a control method by the control unit 13, there are a method based on the number of continuous receptions of the signals UP and DN and a method based on the average number of receptions. Details of these control methods will be described later.

  Next, the operation of the clock selection circuit will be described with reference to the timing chart of FIG. For convenience, switching of the clock signal CKout1 will be described. Now, it is assumed that the clock selection units 11a and 11b both select the clock signal CK1, and the clock switching unit 12 selects the clock signal CKa1. The clock switching unit 12 selects the clock signal CKa1 when the switching control signal CH is at a low level, and selects the clock signal CKb1 when the switching control signal CH is at a high level. The rising edge of the clock signal CK1 at time T1 is delayed by the time ΔT1 and appears in the clock signals CKa1 and CKb1 at time T2. That is, the signal delay amount in the clock selectors 11a and 11b is time ΔT1. Further, the rise of the clock signal CKa1 at time T2 is delayed by a time ΔT2 (ΔT2 << ΔT1), and appears in the clock signal CKout1 at time T3. That is, the signal delay amount in the clock switching unit 12 is time ΔT2.

  Here, it is assumed that the clock selection unit 11b is instructed to select a clock signal having a phase delayed by one step at time T3 when the clock signal CKout1 rises. However, the output of the clock selection unit 11b is not instantaneously switched at time T3, but is actually delayed by time ΔT3 (ΔT3 << ΔT1) and switched to time T4. Then, the signal level of the clock signal CK1 changes during this delay, and the signal levels of the clock signals CK1 and CK2 are inconsistent at time T4. Due to this mismatch in signal level, a glitch is induced in the clock signal CKb1. However, since the clock switching unit 12 still maintains the output of the clock signal CKa1, the glitch generated in the clock signal CKb1 does not appear in the clock signal CKout1.

  Thereafter, the rising edge of the clock signal CKa1 at time T5 is delayed by the time ΔT2 and appears in the clock signal CKout1 at time T6. Then, at time T6 when the clock signal CKout1 rises, that is, at a timing delayed by one cycle after the clock selection unit 11b is instructed to reselect the clock signal, the clock switching unit 12 is instructed to switch the output. The However, the output of the clock switching unit 12 is not instantaneously switched at time T6. Actually, the control unit 13 changes the switching control signal CH to a high level after the rising edge of the clock signal CKout1 is input to the control unit 13. Is delayed by a time ΔT4 (ΔT4 << ΔT1) required until the time T7 is reached. At time T7, since the signal levels of the clock signals CKa1 and CKb1 are the same, no glitch is generated in the clock signal CKout1. Here, the time ΔT4 is sufficiently smaller than the time ΔT1, and is constant regardless of the number of clock signals input to the clock selection circuit. Therefore, even when the number of clock signals input to the clock selection circuit increases and the signal delay of the clock selection units 11a and 11b increases, the clock selection circuit can perform smooth output switching without inducing glitches. .

  When the phase difference between the clock signals CKak and CKbk input to the clock switching unit 12 is sufficiently larger than the time required for the signal level of the switching control signal CH to change after the clock signal CKoutk is input to the control unit 13 In addition, the signal levels of the clock signals CKak and CKbk at the time of actual output switching are not matched, and a glitch is generated in the clock signal CKoutk. Referring to the timing chart of FIG. 2, if the rising edge of the clock signal CKb1 between time T6 and time T7 occurs after time T7, the signal levels of the clock signals CKa1 and CKb1 at time T7 are inconsistent, A glitch occurs in the clock signal CKout1.

  In order to solve the above problem, the clock switching unit 12 may be configured as follows. FIG. 3 shows a configuration example of the clock switching unit 12. The clock switching unit 12 receives the clock signal CKak and the clock signal CKbk, and outputs five 2: 1 selectors 121, 122, 123, 124, and 125 that output the clock signal CKoutk, and a control that controls the selectors 121 to 125. A circuit 126 is provided. The control circuit 126 includes three flip-flops 1261, 1262, and 1263. The flip-flop 1261 latches the switching control signal CH in synchronization with the clock signal CKout1 and outputs a signal CH1. The flip-flops 1262 and 1263 latch the signal CH1 in synchronization with the clock signals CKout4 and CKout5, and output the signals CH4 and CH5, respectively. The selector 121 is controlled by the signal CH4, the selector 122 is controlled by the signal CH5, the selector 123 is controlled by the signal CH1, the selector 124 is controlled by the signal CH5, and the selector 125 is controlled by the signal CH1.

  As described above, by switching the outputs of the selectors 121 to 125 in synchronization with the output clock signals of the other selectors that rise later than the output clock signal of the selectors 121 to 125, Since the signal levels of the two clock signals input to the output signal coincide with each other, glitches associated with output switching can be eliminated.

  Next, a control method based on the number of continuous receptions of the signals UP and DN by the control unit 13 and a control method based on the average number of receptions will be described in order.

≪Control example 1 based on the number of continuous receptions≫
A control method of the control unit 13 based on the number of continuous receptions of the signals UP and DN will be described with reference to the state transition diagram shown in FIG. In the figure, “U” and “D” indicate that the signal UP and the signal DN are received, respectively.

  The controller 13 starts from the state S0 and transitions in the order of the state S1, the state S2, and the state S3 every time the signal DN is received. During this time, when the signal UP is received, the state returns to the state S0. That is, when the signal DN is continuously received three times from the state S0, the state transitions to the state S3. The number of continuous receptions is not limited to three and is arbitrary. When the state transitions to the state S3, the control unit 13 instructs the clock selection unit 11a and 11b that is not selected by the clock switching unit 12 to select a clock signal having a phase delayed by one step. Specifically, when the clock signals CKa1 to CKa5 are output as the clock signals CKout1 to CKout5, the control unit 13 changes the phase selection signal PHb to have a phase delayed by one step with respect to the clock selection unit 11b. Instructs the user to select a clock signal. On the other hand, when the clock signals CKb1 to CKb5 are output as the clock signals CKout1 to CKout5, the control unit 13 changes the phase selection signal PHa to generate a clock signal having a phase delayed by one step with respect to the clock selection unit 11a. Instruct to select.

  When the signal UP is received in the state S3, the state returns to the state S0. On the other hand, when the signal DN is received in the state S3, the state transitions to the state S4. That is, when the signal DN is continuously received four times from the state S0, the control unit 13 transitions to the state S4. The number of continuous receptions is not limited to four and is arbitrary. Thereafter, the control unit 13 changes the switching control signal CH to instruct the clock switching unit 12 to switch the output, and then returns to the state S0. As a result, the phases of the clock signals CKout1 to CKout5 are delayed by one step.

  Similarly to the above, the control unit 13 starts from the state S0 and transitions in order of the state S5, the state S6, and the state S7 each time the signal UP is received. That is, when the signal UP is continuously received three times from the state S0, the state transits to the state S7. At this time, the control unit 13 instructs the clock selection unit 11a and 11b that is not selected by the clock switching unit 12 to select a clock signal having a phase advanced by one step. When the signal UP is further received in the state S7, the state transitions to the state S8. That is, when the signal UP is continuously received four times from the state S0, the control unit 13 transitions to the state S8. Thereafter, the control unit 13 changes the switching control signal CH to instruct the clock switching unit 12 to switch the output, and then returns to the state S0. As a result, the phases of the clock signals CKout1 to CKout5 advance by one stage.

  The control unit 13 can be realized as a CPU that performs the above operation according to a predetermined program, and can also be configured by dedicated hardware. FIG. 5 shows a hardware configuration of the control unit 13 related to the control based on the number of continuous receptions. The control unit 13 includes counters 131u and 131d, a selection control unit 132 that controls the clock selection units 11a and 11b, and a switching control unit 133 that controls the clock switching unit 12.

  The counters 131u and 131d respectively count the number of continuous receptions of the signal UP and the signal DN in synchronization with the clock signal CK that is one of the clock signals CKout1 to CKout5. The selection control unit 132 sets the phase selection signals PHa and PHb based on the count values of the counters 131u and 131d and the switching control signal CH, respectively. Here, it is possible to determine which of the clock selection units 11a and 11b is selected by the clock switching unit 12 by referring to the switching control signal CH. Specifically, the selection control unit 132 outputs the signal RST1 and resets the counters 131u and 131d when either one of the signal UP and the signal DN cannot be continuously received three times or more. On the other hand, the selection control unit 132 activates the signal ENu when receiving the signal UP three times continuously, and the signal ENd when receiving the signal DN three times continuously.

  The switching control unit 133 sets the switching control signal CH based on the count values of the counters 131u and 131d. Specifically, when receiving the signal UP or the signal DN four times continuously, the switching control unit 133 changes the switching control signal CH, and then outputs the signal RST2 to reset the counters 131u and 131d.

≪Control example 2 based on the number of continuous receptions≫
The control unit 13 counts the number of times the signals UP and DN are received, and the number of times the signals UP and DN are received is a predetermined number when the state transitions to the state S3 or the state S7 in the state transition diagram shown in FIG. If it exceeds the threshold value, it may instruct the clock selectors 11a and 11b that are not selected by the clock switching unit 12 to select a clock signal having an opposite phase. FIG. 6 shows a configuration of the control unit 13 having a function of instructing the clock selection units 11a and 11b to select clock signals having opposite phases. The control unit 13 has a configuration in which a counter 134u for counting the number of receptions of the signal UP and a counter 134d for counting the number of receptions of the signal DN are added to the configuration shown in FIG. These counters 134u and 134d are reset by a signal RST2. The selection control unit 132 refers to the count values of the counters 134u and 134d when the setting of the phase selection signal PHa or PHb should be changed, and if both of these count values exceed a predetermined value, the phase selection signal Invert PHa or PHb. As a result, the clock selection unit 11a or 11b outputs a clock signal having a phase opposite to that of the clock selection unit 11a or 11b.

  When this clock selection circuit is used in the clock data recovery circuit, the edge adjustment of the clock signal starts near the transition point of the data signal, but this transition point shakes the clock for a while from the system startup. Signals UP and DN are alternately input to the selection circuit. When one of the signals UP and DN is continuously input a predetermined number of times, the edge of the clock signal output from the clock selection circuit converges to the optimum point, that is, the midpoint between the two data transition points. To do. In such a case, the clock signal output from the clock selection circuit can be set to the optimum phase earlier by setting the phase of the clock signal to the opposite phase at a stroke rather than advancing or delaying the phase one step at a time.

≪Control example 1 based on average number of receptions≫
Next, a control method of the control unit 13 based on the average number of receptions of the signals UP and DN will be described with reference to the state transition diagram shown in FIG. Note that “CK” in the figure indicates that the rising of the clock signal CK, which is one of the clock signals CKout1 to CKout5, has occurred.

  Starting from the state S0, the control unit 13 increments the number of receptions every time it receives the signal UP, and increments the number of receptions every time it receives the signal DN. When a predetermined time T elapses from the state S0, the state transitions to the state S1, and the control unit 13 calculates a difference value between the reception times of the signals UP and DN. Then, when the rising edge of the clock signal CK occurs in the state S1, the state transits to the state S2, and the control unit 13 is delayed by one step with respect to the clock selection unit 11a and 11b that is not selected by the clock switching unit 12 or Instructs to select a clock signal with advanced phase. Specifically, when the control unit 13 determines that the number of receptions of the signal UP is larger based on the difference value between the receptions of the signals UP and DN, the control unit 13 determines that the unselected clock selection unit To select a clock signal having a phase advanced by one step. On the other hand, if it is determined that the number of receptions of the signal DN is larger, the non-selected clock selection unit is instructed to select a clock signal having a phase delayed by one step.

  When the rising edge of the clock signal CK occurs in the state S2, the state transitions to the state S3. The transition to the state S3 may be made after the rising edge of the clock signal CK occurs twice or more. Thereafter, the control unit 13 changes the switching control signal CH to instruct the clock switching unit 12 to switch the output, and then returns to the state S0. As a result, the phases of the clock signals CKout1 to CKout5 are delayed or advanced by one step.

  Note that a condition may be added to instruct the non-selected clock selection unit to reselect the clock signal when the absolute value of the difference between the reception times of the signals UP and DN is larger than a predetermined value. . As a result, it is possible to control such that the output of the clock selection circuit is switched only when the difference in the number of receptions of the signals UP and DN is increased to some extent.

  The control unit 13 can be realized as a CPU that performs the above operation according to a predetermined program, and can also be configured by dedicated hardware. FIG. 8 shows a hardware configuration of the control unit 13 related to the control based on the average number of receptions. The control unit 13 includes a counter 131, a selection control unit 132 that controls the clock selection units 11a and 11b, and a switching control unit 133 that controls the clock switching unit 12.

  The counter 131 is configured by an up / down counter that performs a count-up operation and a count-down operation by receiving the signals UP and DN in synchronization with the clock signal CK, respectively, and calculates a difference value between the reception times of the signals UP and DN. A signal DIF is output. The selection control unit 132 sets the phase selection signals PHa and PHb based on the signal DIF and the switching control signal CH, respectively. Specifically, the selection control unit 132 resets the counter 131 by outputting a reset signal RST1 if the value represented by the signal DIF after the elapse of a predetermined period from the start of the operation of the counter 131 is zero or within a predetermined range. On the other hand, if the value represented by the signal DIF is outside the predetermined range, one of the phase selection signals PHa and PHb is changed and the signal EN is activated. When the signal EN is activated, the switching control unit 133 changes the switching control signal CH in synchronization with the clock signal CK, and then outputs the signal RST2 to reset the counters 131u and 131d.

≪Control example 2 based on average number of receptions≫
The control unit 13 is a clock signal whose phase is shifted by an amount corresponding to the difference value between the reception times of the signals UP and DN with respect to the clock selection unit 11a and 11b which is not selected by the clock switching unit 12. May be instructed to be reselected. Specifically, in the configuration shown in FIG. 8, the control unit 13 adaptively changes one of the phase selection signals PHa and PHb with respect to the difference value represented by the signal DIF. As a result, when the clock selection circuit is used in the clock data recovery circuit as described above, the clock signal output from the clock selection circuit can be set to the optimum phase earlier.

(Second Embodiment)
FIG. 9 shows a configuration of a clock selection circuit according to the second embodiment. The clock selection circuit receives 45 clock signals CKin1 to CKin45 that are out of phase with each other, and selectively outputs five of these clock signals CKin1 to CKin45 as clock signals CKout1 to CKout5 according to the phase selection signal PH. To do. Specifically, the present clock selection circuit is provided with nine clock signals, and five 9: 1 selectors 21, 22, 23, 24 for selectively outputting any one of these clock signals. And a clock alignment unit 30 that outputs the clock signals output from the selectors 21 to 25 in the order of the phases. It is assumed that the clock signals CKin1 to CKin45 are arranged in phase order with phases shifted by an electrical angle of 8 °. This is because the clock selection circuit is assumed to be used in the clock data recovery circuit, and does not limit the present invention.

  The selector 21 receives the clock signals CKin1 to CKin9 and outputs the clock signal CK1. The selector 22 receives the clock signals CKin10 to CKin18 and outputs the clock signal CK2. The selector 23 receives the clock signals CKin19 to CKin27 and outputs the clock signal CK3. The selector 24 receives the clock signals CKin28 to CKin36 and outputs the clock signal CK4. The selector 25 receives the clock signals CKin37 to CKin45 and outputs the clock signal CK5. That is, nine clock signals CKin1 to CKin45 are input to the selectors 21 to 25 in order of phase. These selectors 21 to 25 select a clock signal in accordance with a common phase selection signal PH. Accordingly, the selectors 21 to 25 output clock signals CK1 to CK5 arranged in phase order with phases shifted by 72 ° from each other.

  FIG. 10 shows a configuration example of the selector 21. The selector 21 includes nine AND gates 211 to which each of the clock signals CKin1 to CKin9 and each bit of the 9-bit phase selection signal PH are input, and a dynamic selector 212 having a PMOS transistor as a load. . Of the nine AND gates 211, the input phase selection signal PH having a high level passes the input clock signal. The selector 212 receives the clock signal provided from any one of the nine AND gates 211 and outputs the clock signal CK1. According to this configuration, the clock signals CKin1 to CKin9 that are not selected by the phase selection signal PH are blocked by the AND gate 211, so that unnecessary clock signals are not input to the selector 212.

  In the above configuration, as the number of clock signals input to the selector 21 increases, the parasitic capacitance added to the output portion of the dynamic selector 212 increases and the signal delay increases. In order to avoid this problem, the selector 21 may have a multi-stage configuration. FIG. 11 shows another configuration example of the selector 21. The selector 21 is provided with three clock signals, and is composed of four 3: 1 selectors 213a, 213b, 213c, and 213d that selectively output one of these clock signals. The selector 213a includes three AND gates 211 to which the clock signals CKin1 to CKin3 and each bit of the 3-bit phase selection signal PH are input, and a dynamic selector 214 having a PMOS transistor as a load. . The selectors 213b, 213c and 213d have the same configuration. In particular, the selector 213d receives three clock signals output from the selectors 213a to 213c, selects any one of these clock signals, and outputs it as the clock signal CK1. In the case of this configuration, the selector 21 can be controlled by a 6-bit phase selection signal PH.

  Returning to FIG. 9, the clock alignment unit 30 is provided with five clock signals, and five 5: 1 selectors 31, 32, 33, 34 that selectively output any one of these clock signals. And 35. The selector 31 receives these clock signals in an array of clock signals CK1, CK2, CK3, CK4, and CK5, and outputs a clock signal CKout1. The selector 32 receives these clock signals in an array of clock signals CK2, CK3, CK4, CK5, and CK1, and outputs a clock signal CKout2. The selector 33 receives these clock signals in an array of clock signals CK3, CK4, CK5, CK1 and CK2, and outputs a clock signal CKout3. The selector 34 receives these clock signals in an array of clock signals CK4, CK5, CK1, CK2 and CK3, and outputs a clock signal CKout4. The selector 35 receives these clock signals in an array of clock signals CK5, CK1, CK2, CK3, and CK4, and outputs a clock signal CKout5. That is, the clock signals CK1 to CK5 are input to the selectors 31 to 35 in the five kinds of phase order, each of which is the first. These selectors 31 to 35 select a clock signal in accordance with a common phase selection signal PH. Therefore, the clock alignment unit 30 outputs five kinds of phase-ordered clock signals CKout1 to CKout5 in which any one of the clock signals CK1 to CK5 is the clock signal CKout1.

  As described above, according to the present embodiment, since a plurality of input clock signals are processed separately for each signal group in the multi-output clock selection circuit, the wiring structure of the input portion can be simplified. Thereby, even if the number of input clock signals is large, the signal delay in the clock selection circuit can be made relatively small.

  In the clock selection circuits according to the first and second embodiments, the number of input and output clock signals is not limited to the above. For example, the number of clock signals output from the clock selection circuit according to the first embodiment may be one.

(Third embodiment)
FIG. 12 shows a configuration of a clock data recovery circuit according to the third embodiment. The clock data recovery circuit receives the reference clock signal CK0 and the data signal DATA0, and outputs a clock signal CK recovered for data latching and a data signal DATA latched by the clock signal CK. Specifically, the clock data recovery circuit includes a multiphase clock generation unit 101, a clock selection circuit 102, and a phase comparator 103.

  The multi-phase clock generation unit 101 receives the reference clock signal CK0, and generates 40 clock signals CKin1 to CKin40 arranged in phase order with phases shifted by an electrical angle of 9 ° from each other. The multiphase clock generation unit 101 can be configured by a PLL (Phase Locked Loop) or the like.

  The clock selection circuit 102 receives the clock signals CKin1 to CKin40, selects four clock signals that are out of phase with each other by an electrical angle of 90 ° and are arranged in order from the clock signals CKin1 to CKin40, and selects the clock signal CKout1. Output as ~ CKout4. The clock selection circuit 102 selects a clock signal according to the signals UP and DN output from the phase comparator 103. Signals UP and DN are as described above. The clock selection circuit 102 can be configured by a clock generation circuit according to any of the first and second embodiments.

  The phase comparator 103 compares the phase of any one of the clock signals CKout1 to CKout4 with the data transition point of the data signal DATA0, and selects one of the clock signals CKout1 to CKout4 used for latching the data signal DATA0. In addition to outputting as the clock signal CK, the data signal DATA latched by the clock signal CK is output. The phase comparator 103 outputs signals UP and DN as a result of the phase comparison.

  Next, the operation of the phase comparator 103 will be described with reference to the timing chart of FIG. Here, the phase comparator 103 does not use the clock signal CKout1 and outputs the clock signal CKout3 as the clock signal CK. When the phase comparator 103 detects the transition of the data signal DATA0 in a period corresponding to an electrical angle of 90 ° from the rising edge of the clock signal CKout2 to the rising edge of the clock signal CKout3, the phase comparator 103 outputs the signal DN. On the other hand, the phase comparator 103 outputs a signal UP when detecting a transition of the data signal DATA0 in a period corresponding to an electrical angle of 90 ° from the rising edge of the clock signal CKout3 to the rising edge of the clock signal CKout4. As a result, the phase of the clock signal CK is adjusted so that the rising edge of the clock signal CK moves away from the transition point of the data signal DATA0, that is, rises at the stable point of the signal level of the data signal DATA0.

  As described above, according to the present embodiment, a clock signal without glitch is supplied from the clock selection circuit, so that accurate clock recovery and data recovery can be performed.

  Since the clock selection circuit according to the present invention does not induce glitches due to output switching, it is particularly useful for a clock data recovery circuit in a system that performs high-speed data communication.

1 is a configuration diagram of a clock selection circuit according to a first embodiment. FIG. 2 is a timing chart of the clock selection circuit shown in FIG. 1. It is a block diagram of a clock switching part. It is a state transition diagram of the control part which concerns on control based on the frequency | count of continuous reception. It is a block diagram of the control part which concerns on the control based on the frequency | count of continuous reception. It is a block diagram of the control part which has a phase inversion instruction | indication function. It is a state transition diagram of the control part which concerns on control based on the average frequency | count of reception. It is a block diagram of the control part which concerns on the control based on an average frequency | count of reception. It is a block diagram of the clock selection circuit which concerns on 2nd Embodiment. FIG. 10 is a block diagram of the 9: 1 selector shown in FIG. 9. FIG. 10 is another configuration diagram of the 9: 1 selector illustrated in FIG. 9. It is a block diagram of the clock data recovery circuit which concerns on 3rd Embodiment. It is a timing chart of the phase comparator shown in FIG. 6 is a timing chart for explaining that a glitch occurs in the output of the clock selection circuit.

Explanation of symbols

11a Clock selection unit (first clock selection unit)
11b Clock selection unit (second clock selection unit)
12 clock switching unit 13 control unit 131 counter 131u counter (first counter)
131d counter (second counter)
132 Selection control unit 133 Switching control unit 134u Counter (third counter)
134d counter (fourth counter)
21-25, 31-35 Selector 30 Clock alignment unit 101 Multiphase clock generation unit 102 Clock selection circuit 103 Phase comparator

Claims (16)

A clock selection circuit that receives a plurality of clock signals out of phase with each other and selectively outputs one or more of these clock signals,
First and second clock selectors which receive the plurality of clock signals and selectively output one or more of these clock signals;
A clock switching unit that selects one of the first and second clock selection units and outputs a clock signal output from the selected one;
A control unit that controls the first and second clock selection units and the clock switching unit;
The control unit instructs a reselection of the clock signal to the one of the first and second clock selection units that has not been selected by the clock switching unit and, after the instruction, instructs the clock switching unit. A clock selection circuit for instructing switching of an output. The clock selection circuit according to claim 1,
M × N clock signals (where M and N are integers of 2 or more) are input to the clock selection unit,
Each of the first and second clock selectors is provided corresponding to each of N signal groups obtained by dividing the M × N clock signals by M in phase order. M clock signals to which the clock signal belongs are provided in order of phase, and N selectors are provided for selectively outputting any one of the supplied M clock signals according to a common control signal. A clock selection circuit. The clock selection circuit according to claim 2,
Each of the first and second clock selection units includes a clock alignment unit that receives N clock signals output from the N selectors and outputs the N clock signals in phase order. A clock selection circuit. The clock selection circuit according to claim 2,
The clock alignment unit includes:
Each of the N clock signals is provided in correspondence with the phase order of the N N clock signals, each of which is the first, and the N clock signals are provided in the corresponding phase order. A clock selection circuit comprising N selectors for selectively outputting any one of the given N clock signals in accordance with a common control signal. The clock selection circuit according to claim 1,
The control unit continues the same request signal a predetermined number of times among a first request signal indicating a request for advancing the phase of the clock signal output from the clock selection circuit and a second request signal indicating a request for delaying the phase. The clock selection unit that is not selected by the clock switching unit is instructed to reselect the clock signal, and when the same request signal is received at least once in succession, the clock switching unit is A clock selection circuit for instructing switching of an output. The clock selection circuit according to claim 5, wherein
The control unit receives both of the first and second request signals when the same request signal among the first and second request signals is continuously received for the predetermined number of times. A clock selection circuit for instructing a clock selection unit not selected by the clock switching unit to select a clock signal having an opposite phase. The clock selection circuit according to claim 5, wherein
The controller is
First and second counters for counting the number of continuous receptions of the first and second request signals, respectively;
When the count value of any one of the first and second counters reaches the first specified value, the clock selection unit not selected by the clock switching unit responds to the continuously received request signal. A selection control unit for instructing reselection of the selected clock signal;
And a switching control unit that instructs the clock switching unit to switch output when the count value of one of the first and second counters reaches a second specified value. Clock selection circuit. The clock selection circuit according to claim 7, wherein
The control unit includes third and fourth counters for counting the number of receptions of the first and second request signals, respectively.
The selection control unit is configured such that each of the count values of the third and fourth counters when the count value of one of the first and second counters reaches the first specified value is predetermined. When the value is larger than the value, the clock selection circuit instructs the clock selection unit that is not selected by the clock switching unit to select a clock signal having an opposite phase. The clock selection circuit according to claim 1,
The control unit includes a difference in the number of receptions in a predetermined period for each of a first request signal indicating a request for advancing the phase of a clock signal output from the clock selection circuit and a second request signal indicating a request for delaying the phase. A clock selection circuit, wherein when the value exceeds a predetermined value, the clock selection unit not selected by the clock switching unit is instructed to reselect a clock signal. The clock selection circuit according to claim 9, wherein
The control unit instructs the clock selection unit not selected by the clock switching unit to reselect a clock signal whose phase is shifted by an amount corresponding to the difference value. circuit. The clock selection circuit according to claim 9, wherein
The controller is
In the predetermined period, when receiving the first request signal, the counter performs one operation of counting up and counting down, while performing the other operation when receiving the second request signal;
When the count value of the counter after the lapse of the predetermined period exceeds the predetermined value, the clock selection unit that is not selected by the clock switching unit, among the first and second request signals, A selection control unit for instructing reselection of a clock signal in accordance with a larger number of receptions in a predetermined period;
A clock selection circuit comprising: a switching control unit that instructs the clock switching unit to switch the output after the selection control unit instructs reselection of the clock signal. The clock selection circuit according to claim 11, wherein
When the count value of the counter after the elapse of the predetermined period exceeds the predetermined value, the selection control unit responds to the clock selection unit that is not selected by the clock switching unit according to the count value A clock selection circuit which instructs to reselect a clock signal whose phase is shifted by an amount. A clock selection circuit that receives a plurality of clock signals out of phase with each other and selectively outputs a plurality of these clock signals,
The plurality of clock signals are respectively provided corresponding to N (N is an integer of 2 or more) signal groups obtained by dividing M (M is an integer of 2 or more) in order of phase, and M belonging to the corresponding signal group. A plurality of clock signals are provided in order of phase, and N selectors are provided for selectively outputting any one of the supplied M clock signals in accordance with a common control signal. A clock selection circuit. The clock selection circuit according to claim 13.
A clock selection circuit comprising a clock alignment unit that receives N clock signals output from the N selectors and outputs the N clock signals arranged in phase order. The clock selection circuit according to claim 14, wherein
The clock alignment unit includes:
Each of the N clock signals is provided in correspondence with the phase order of the N N clock signals, each of which is the first, and the N clock signals are provided in the corresponding phase order. A clock selection circuit comprising N selectors for selectively outputting any one of the given N clock signals in accordance with a common control signal. A clock data recovery circuit that receives a reference clock signal and a data signal and generates a clock signal for data latch of the data signal,
A multi-phase clock generator that generates a plurality of clock signals out of phase with each other from the reference clock signal;
The clock selection circuit according to any one of claims 1 and 13, wherein a plurality of clock signals generated by the multiphase clock generation unit are provided.
A phase comparator that compares the phase of the clock signal output from the clock selection circuit and the data signal;
The clock data recovery circuit, wherein the clock selection circuit selects a clock signal based on a result of phase comparison by the phase comparator.

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