JP3986358B2 - Serial / parallel converter and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a serial / parallel converter that self-corrects a skew of a data signal with respect to a clock signal.
[0002]
[Prior art]
When the propagation times of the clock signal and the data signal are different, a skew that is a variation in the phase of the signal occurs between the two signals. As a result, there may occur a problem that the setup time and hold time of the data signal with respect to the clock signal are not sufficiently satisfied. Further, in the case of high-speed data transmission, there is a tendency that erroneous data reception occurs.
[0003]
Therefore, as a solution to the above problem, Japanese Patent Laid-Open No. 11-168365 discloses a technique related to a skew correction apparatus. The skew correction apparatus includes a transition detector for supplying a pulse signal when a transition of an input data signal is detected, and first delay data obtained by delaying the input data signal by a variable delay amount. A variable delay line, a fixed delay line for generating a second delayed data signal obtained by further delaying the first delayed data signal by a fixed delay amount, and transition of the second delayed data signal to the clock A phase comparator for comparing with the phase of the signal. Then, on the condition that the pulse signal is supplied from the transition detector, the phase comparator is configured so that the transition of the second delayed data signal is substantially in phase with the rising edge of the clock signal. A delay amount is controlled, and a first delayed data signal is output together with the clock signal.
[0004]
By using this skew correction device, the control of the variable delay line by the phase comparator is enabled only when there is a transition of the data signal, so the clock signal and the data signal can be used not only in the setup mode but also in the normal operation mode. Can be corrected. Therefore, skew correction according to environmental changes such as temperature rise becomes possible.
[0005]
Japanese Patent Laid-Open No. 2000-780277 discloses a serial / parallel conversion device, a semiconductor device, and an electronic device as a technique for eliminating a clock phase shift on the receiving side and improving a display image even when jitter occurs on the transmitting side. And a technique related to a data transmission system is disclosed. In this technology, as a solution to the above problem, a clock for serial / parallel conversion is regenerated from the transmission clock, and a synchronization detection bit is provided for each unit data string of serial data to synchronize with the regenerated clock for stable operation. The serial-parallel conversion is performed. That is, the serial / parallel conversion unit samples the serial data DA1 following the synchronization period from the first data string having a unit data string of a predetermined number of bits based on the conversion clock CL1 from the original parallel data. The unit data string is converted into parallel data. The signal generating means generates a synchronization signal based on the serial data DA1 and the clock CL1. The serial data includes a second data string for synchronization detection of a unit data string having a predetermined bit pattern within the synchronization period. The signal generating means detects the unit data string in the second data string to generate a synchronization signal, and the serial / parallel converter detects the head position of the unit data string in the first data string.
[0006]
With such a configuration and operation, it is possible to eliminate a shift in conversion timing in the serial / parallel conversion unit, accurately convert serial data into parallel data, and improve the display image on the receiving side.
[0007]
[Problems to be solved by the invention]
In the skew correction apparatus disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 11-168365, it can be effective when the clock rate and the data rate are equal, but multi-bit serial data exists for one clock rate, and these serial data Is not suitable for use in a system that converts the signal to parallel.
[0008]
In addition, the technique disclosed in the above Japanese Patent Laid-Open No. 2000-780277 requires the transmission side to code the synchronization detection bit in advance in the data, which is not suitable for converting simple serial data into parallel data. .
[0009]
Therefore, the present invention was created to solve the above problem, and its purpose is to pre-code the synchronization detection bit in the data without causing a skew between the data signal and the clock signal. To provide a serial / parallel converter for self-correcting an input data signal with respect to a clock signal.
[0010]
[Means for Solving the Problems]
The present invention has the following configuration as means for solving the above problems.
[0013]
  (1)A serial / parallel converter for converting serial transmission data into parallel transmission data,
  A PLL circuit that divides the clock signal and outputs a plurality of tap output signals;
  A strobe generation circuit for generating a plurality of strobe signals having different phases using the plurality of tap output signals;
The serial transmission data is latched using a plurality of strobe signals output from the strobe generation circuit, and from the latched serial transmission data,Skew between the serial transmission data and the clock signalPresence ofDetectAnd output a control signal according to the result.A skew detection circuit that
  A strobe selection circuit for selecting a strobe signal according to the detected skew;
  A logic circuit for converting serial transmission data into parallel transmission data by the selected strobe signal;
  It is provided with.
[0014]
  In this configuration, the serial / parallel converter isA PLL circuit that divides the clock signal and outputs a plurality of tap output signals; a strobe generation circuit that generates a plurality of strobe signals having different phases using the plurality of tap output signals;The serial transmission data is latched using a plurality of strobe signals output from the strobe generation circuit, and a control signal corresponding to the result of detecting the presence or absence of skew from the latched serial transmission data is output.A skew detection circuit; a strobe selection circuit that selects a strobe signal according to the detected skew; and a logic circuit that converts serial transmission data into parallel transmission data using the selected strobe signal. Convert to parallel transmission data. Therefore,When converting serial data to parallel dataReliable detection of skew with dedicated circuitIn addition, since an appropriate strobe signal can be selected based on the detection result, stable serial / parallel conversion is performed even when data has a skew.It becomes possible.
[0015]
  (2) A serial / parallel converter for converting serial transmission data into parallel transmission data,
  A PLL circuit that divides the clock signal and outputs a plurality of tap output signals;
  A strobe generation circuit for generating a plurality of strobe signals having different phases using the plurality of tap output signals;
  Edge detection circuit for detecting a transition of the serial transmission data and outputting a detection signalWhen,
  in frontA skew between the serial transmission data and the clock signal is detected based on the strobe signal generated by the strobe generation circuit and the detection signal.A skew detection circuit;
  A strobe selection circuit for selecting a strobe signal according to the detected skew;
  A logic circuit for converting serial transmission data into parallel transmission data by the selected strobe signal;
  It is characterized by having.
[0016]
  In this configuration,The serial-parallel converter includes a PLL circuit that divides a clock signal and outputs a plurality of tap output signals, and a strobe generation circuit that generates a plurality of strobe signals having different phases using the plurality of tap output signals, An edge detection circuit that detects a transition of serial transmission data and outputs a detection signal, and a skew detection that detects a skew between the serial transmission data and the clock signal based on the strobe signal and the detection signal created by the strobe creation circuit Circuit, a strobe selection circuit that selects a strobe signal according to the detected skew, and a logic circuit that converts serial transmission data into parallel transmission data using the selected strobe signal, and thereby serial transmission data is transmitted in parallel Convert to data.Therefore, the skew between the serial transmission data and the clock signal can be detected without requiring specific detection bit data in the serial data. Further, by controlling the strobe signal, the resolution of skew detection can be made variable. Note that the detection of the transition of serial transmission data refers to the detection of rising or falling of serial transmission data.
[0017]
  (3)The PLL circuit includes a voltage controlled oscillator and a frequency divider, and the skew adjustment resolution is variable by changing the division ratio of the frequency divider and changing the oscillation frequency setting of the voltage controlled oscillator. It is characterized by that.
[0018]
In this configuration, the skew adjustment resolution of the PLL circuit is variable by changing the division ratio of the frequency divider and changing the oscillation frequency setting of the voltage controlled oscillator. Therefore, since the skew self-correction sensitivity can be easily changed, the serial / parallel conversion accuracy can be improved according to the intended use.
[0019]
  (4)the above(3), T is the period of the clock signal, M is the number of stages of the inverter elements constituting the voltage controlled oscillator, and N is the frequency division ratio of the frequency divider, the skew adjustment resolution is T / (M · N ).
[0020]
In this configuration, the skew adjustment resolution of the serial / parallel converter is as follows: T / is the period of the clock signal, M is the number of stages of the inverter elements constituting the voltage controlled oscillator, and N is the frequency division ratio of the frequency divider. (M · N). Therefore, the number of strobe signals for skew detection can be increased by changing the frequency division ratio of the frequency divider of the PLL circuit and increasing the input signal frequency to the strobe generation circuit. By increasing the number of strobe signals assigned to the signal, the resolution of skew detection can be increased, and the skew can be detected with higher accuracy. Further, since an appropriate strobe can be selected, it is possible to provide a stable serial / parallel conversion circuit and a semiconductor device.
[0021]
  (5)The PLL circuit includes an oscillator composed of M-stage (M: odd number) elements, a frequency divider that divides the output of the oscillator by 1 / N, the 1 / N frequency-divided signal, and the phase of the clock signal. And a control circuit for controlling the oscillator so as to eliminate the phase difference, and each element of the oscillator outputs the tap output signal corresponding to the clock signal.
[0022]
In this configuration, in the PLL circuit, the control circuit compares the phase of the 1 / N frequency-divided signal and the clock signal, and controls the oscillator so that the phase difference is eliminated. The oscillator is composed of M-stage (M: odd) elements, and each element outputs a tap output signal corresponding to the clock signal. Therefore, by changing the number of stages of each element in the oscillator of the PLL circuit, the number of data strobe signals can be increased or decreased to make the skew adjustment resolution variable.
[0023]
  (6)The skew detection circuit performs skew detection on a serial data pattern in which only one bit in input serial transmission data transitions.
[0024]
In this configuration, the skew detection circuit performs skew detection on a serial data pattern in which only one bit in the input serial transmission data transitions. Therefore, it is not necessary to code the skew detection bit in the serial data in advance, and it is possible to react only when a certain pattern is input to any data input, to perform skew detection and simultaneously perform skew correction. Become.
[0025]
  (7)the above(6)In the above, the skew detection means is characterized in that it performs skew detection on one bit that transitions in the serial transmission data and one bit before and after the bit.
[0026]
In this configuration, the skew detection means performs skew detection for one bit that transitions in the serial transmission data and one bit before and after the bit. Therefore, the skew can be reliably detected with a small amount of data.
[0027]
  (8)(1) to(7)The serial-parallel conversion device according to any one of the above is formed on a semiconductor substrate.
[0028]
  In this configuration, the semiconductor device includes (1) to (1).(7)The serial-parallel converter described in any of the above is formed on a semiconductor substrate. Therefore, it is possible to provide a semiconductor device that performs serial / parallel conversion stably.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
FIG. 1 is a block diagram showing a schematic configuration of a serial / parallel converter according to a first embodiment of the present invention. The serial / parallel conversion device 1 converts N-bit serial transmission data (hereinafter referred to as serial data) into N-bit parallel transmission data (hereinafter referred to as parallel data). A PLL circuit 12 and a strobe generation circuit 13 for generating a strobe signal for causing the serial / parallel conversion logic circuit 11 to execute serial / parallel conversion, a strobe selection circuit 14 for selecting an optimum strobe signal, and a data signal The skew detection circuit 15 is configured to detect a skew with the clock signal.
[0030]
The configuration and operation of each part in the serial / parallel converter will be described below. First, the PLL (Phase Locked Loop) circuit 12 will be described. FIG. 2 is a block diagram showing the configuration of the PLL circuit. The PLL circuit 12 has a general PLL circuit configuration, and includes a phase comparator 21, a charge pump 22, a loop filter 23, a VCO (voltage controlled oscillator) 24, and a frequency divider 25.
[0031]
The phase comparator 21 detects a phase difference between the reference signal (fr) and the feedback signal (fp) from the frequency divider 25, and increases or decreases the control signal (UP) that increases the oscillation frequency of the VCO 24. The control signal (DN) to be output is output. When the feedback signal (fp) is delayed with respect to the reference signal (fr), the phase comparator 21 outputs a control signal (UP) that increases the oscillation frequency of the VCO 24 for a period corresponding to the phase difference. Conversely, when the feedback signal (fp) is advanced with respect to the reference signal (fr), the phase comparator 21 outputs a control signal (DN) for decreasing the oscillation frequency of the VCO 24 for a period corresponding to the phase difference. The Thus, the phase comparator 21 outputs a signal obtained by performing pulse width conversion on the phase difference between two input signals.
[0032]
The charge pump 22 converts the control signal (UP, DN) from the phase comparator 21 into an analog signal, and applies the output signal CPO to the VCO 24 through the loop filter 23 as the control voltage (Vc).
[0033]
The loop filter 23 is a low-pass filter circuit composed of a resistor and a capacitor, and is used for the purpose of reducing switching noise included in the output signal CPO from the charge pump 22 and the purpose of stabilizing the feedback loop.
[0034]
The output signal (fo) of the VCO 24 is output as the output signal (fo) of the PLL circuit 12, and is divided by the frequency divider 25 and input to the phase comparator 21 as a feedback signal (fp). At that time, since the output signal (fo) is converted to a frequency of 1 / N by the frequency divider 25, the relationship between the frequency of the feedback signal (fp) and the output signal (fo) is expressed by the following equation (1). Is done.
fp = fo / N (1)
The frequency divider 25 can change the frequency division ratio.
[0035]
Since the PLL circuit 12 controls the control voltage (Vc) so that fr = fp, the output signal (fo) is expressed by the following equation (2).
fo = N × fr (2)
That is, an output signal (fo) having a frequency N times that of the reference signal (fr) is output from the PLL circuit 12.
Next, the configuration of the VCO 24 will be described. FIG. 3 is a circuit diagram showing a schematic configuration of the VCO 24. As shown in FIG. 3B, the VCO 24 of the present invention has a configuration including an M-stage (M: odd number) ring oscillator 31 whose oscillation frequency changes according to an input control voltage (Vc). In the present invention, the output signals phi 1 to phi (M) output from the taps of the M inverter elements constituting the ring oscillator 31 are used as the output of the PLL circuit 12. Further, the output signal phi1 is input to the frequency divider, frequency-divided, and fed back to the phase comparator as a feedback signal (fp).
[0036]
With this configuration, the output signals phi1 to phi (M) that are the outputs of the PLL circuit 12 have a frequency that is a frequency division ratio (N) times the reference signal (fr), and the period of the reference signal (fr) is changed. Assuming T, each phase is an output signal delayed by T / (N · M).
[0037]
Next, the strobe creation circuit 13 will be described. The strobe generation circuit 13 receives the output signals phi1 to phi (M) output from the PLL circuit 12 and generates a plurality of strobe signals.
[0038]
FIG. 4 is a circuit diagram showing a schematic configuration of the strobe generation circuit. The strobe generation circuit 13 can generate a strobe signal using the output signals (tap output signals) phi1 to phi (M) of the PLL circuit 12 with a simple configuration using a D flip-flop. For example, as shown in FIG. 4, the output signals phi1 to phi (M) of the PLL circuit 12 are connected to the clock input terminals CK of M D flip-flops d1 to d (M), respectively. . Further, only the D flip-flop d1 that inputs the output signal phi1 to the clock input terminal connects the output terminal / Q to the data input terminal D. Further, the output terminals Q of the D flip-flops d1 to d (M-1) are connected to the data input terminals D of the D flip-flops d2 to d (M) at the next stage, respectively. The signals output from the output terminals Q of the D flip-flops d1 to dM are set as strobe signals stb1 to stb (M). With this configuration, a plurality of strobe signals are created using the output signals phi1 to phi (M). Further, the combination of the input signals phi1 to phi (M) to the strobe generation circuit 13 for generating the strobe signal must be appropriately selected so that a plurality of strobe signals to be output are regularly generated. .
[0039]
Next, the skew detection circuit 15 will be described. The skew detection circuit 15 uses the strobe signal generated by the strobe generation circuit 13 to latch serial data input to the serial / parallel conversion logic circuit 11. Based on the latch result, the skew detection circuit 15 determines the presence or absence of skew.
[0040]
That is, attention is focused on serial data in which only one bit in the serial data is changed from the serial data pattern that is arbitrarily input. Then, the skew detection circuit 15 determines the presence or absence of skew based on the result of latching a plurality of bits including one transition bit. In this way, it is not necessary to code the skew detection bit in the serial data in advance, and it reacts only when a certain pattern is input to any data input, and performs skew detection and simultaneously performs skew correction. It can be carried out.
[0041]
Further, the bit combination in the N-bit serial data to be determined is data in which only one bit is changed as in the following two patterns.
D [1: N] = 00 ... 010 ... 00 (3)
D [1: N] = 11 ... 101 ... 11 (4)
Now, when the skew detection data is the pattern (3), it is assumed that the skew detection method is performed on the three bits before and after the transition including one bit. In addition, 1 bit which is changing is hereinafter referred to as X bit. The result latched by the plurality of strobe signals supplied from the strobe generation circuit 13 for each bit is (X-1 bit, X bit, X + 1 bit) = (000... 0, 1. ········ 000).
[0042]
On the other hand, when the skew is caused by the data delay, the result of latching with the strobe that created the continuous 3 bits 0, 1, 0 including the transitioning 1 bit is (X-1 bit, X bit, X + 1 bit) ) = (000..0,0.111.1,1, .. 000). On the other hand, when the skew is caused by the data advance, the result of latching with the strobe is (X-1 bit, X bit, X + 1 bit) = (000..1,1.111.0,0..000) It becomes.
[0043]
As described above, in the case of the above pattern (3), the result of latching 1-bit data (High data) in which serial data is transitioned with several strobe signals is all “1” when there is no skew. (High). On the other hand, when there is a skew, it can be seen that the latched results do not all become “1”. That is, paying attention to data in which only one bit of serial data changes, the presence or absence of skew can be determined based on the result of latching with a plurality of regularly created strobes.
[0044]
Similarly, when the skew detection data is the pattern (4), the result of latching by the strobe obtained from the strobe generation circuit 13 for the three bits before and after the transitioning one bit is (X −1 bit, X bit, X + 1 bit) = (111... 1, 0... 000... 0, 1... 111).
[0045]
On the other hand, when the skew is caused by the data delay, the latch result is (X-1 bit, X bit, X + 1 bit) = (111... 1, 1,000 .0, 0.. 111). . On the other hand, when the skew is caused by the data advance, the result of latching with the strobe is (X−1 bit, X bit, X + 1 bit) = (111 · 0,0000 · 1,1, ·· 111) It becomes.
[0046]
As described above, in the case of the pattern (4) as well, the result of latching 1-bit data (Low data) in which serial data is transitioned with several strobe signals is all “ 0 "(Low). On the other hand, when there is a skew, it can be seen that the latched results are not all “0” (Low). That is, paying attention to data in which only one bit of serial data changes, the presence or absence of skew can be determined based on the result of latching with a plurality of regularly created strobes.
[0047]
Next, the strobe selection circuit 14 will be described. The strobe selection circuit 14 is configured by a MUX (multiplexer) circuit or the like, and selects an appropriate strobe signal based on the detection result of the skew detection circuit 15. When there is no skew, the strobe signal stb (N) is selected for each bit data of the serial data. On the other hand, when the data is skewed, that is, when the data is delayed, the strobe signals stb (N + 1), stb (N + 2),... Are selected. When the data is advanced, the strobe signals stb (N-1), stb (N-2),... Are selected. Therefore, a strobe that constantly becomes the center of each bit data of the serial data is selected.
[0048]
Next, the overall operation of the serial / parallel converter 1 will be described with reference to FIG. FIG. 5 is a waveform timing chart of each part in the serial / parallel converter. In the serial / parallel converter 1, N-bit serial data is transmitted in one clock cycle. A clock signal CLKIN that is a rectangular wave with a period T is input to the input terminal of the PLL circuit 12 as a reference signal (fr). Further, as shown in FIG. 5, the N-bit serial data is input to the serial / parallel conversion logic circuit 11 at the falling timing of the clock signal CLKIN. The PLL circuit 12 divides the clock signal CLKIN and outputs output signals phi1 to phi (M). The output signals phi1 to phi (M) of the PLL circuit 12 are input to the strobe generation circuit 13 and converted into strobe signals stb1 to stb (M). Then, the result of latching the N-bit serial data input to the serial / parallel conversion logic circuit 11 with the strobe signals stb 1 to stb (M) is output to the skew detection circuit 15.
[0049]
As described above, the skew detection circuit 15 detects the occurrence of skew and outputs a control signal to the strobe selection circuit 14. The strobe selection circuit 14 selects an appropriate strobe signal corresponding to the skew based on the control signal. The serial / parallel conversion logic circuit 11 outputs N-bit serial data that is not shifted from the clock signal CLKIN even if a skew occurs between the clock signal CLKIN and the N-bit serial data.
[0050]
Since the frequency divider 25 of the PLL circuit 12 can change the frequency division ratio as described above, the skew adjustment resolution can be changed by changing the setting of the oscillation frequency of the VCO 24.
[0051]
As described above, it is possible to provide a serial-to-parallel conversion device that performs stable serial-to-parallel conversion by self-correcting an input data signal with respect to a clock signal even when a skew occurs due to the present invention.
[0052]
Next, embodiments of the present invention will be described in more detail. Hereinafter, a configuration in which 7-bit serial data is transmitted in one clock cycle in the serial-parallel converter of the present invention will be described. FIG. 6 is a block diagram showing a configuration of a serial / parallel converter in which 7-bit serial data is transmitted in one clock cycle. As shown in FIG. 6, the serial / parallel conversion device 101 has the same configuration as the serial / parallel conversion device 1 shown in FIG. 1, and includes a serial / parallel conversion logic circuit 111, a PLL circuit 112, and a strobe generation circuit 113. , A strobe selection circuit 114, and a skew detection circuit 115.
[0053]
First, the PLL circuit 112 will be described. FIG. 7 is a block diagram showing the configuration of the PLL circuit 112 and a circuit diagram showing the configuration of the VCO 124. The PLL circuit 112 has the same configuration as that of the PLL circuit 12 shown in FIG. 2, and includes a phase comparator 121, a charge pump 122, a loop filter 123, a VCO 124, and a frequency divider 125. Is as described with reference to FIG. Since the serial-parallel converter of the present invention is configured to transmit 7-bit serial data in one clock cycle, the number of stages M of the ring oscillator 131 provided in the VCO 124 is set to 7 and the frequency divider 125 is divided. The circumferential ratio N = 2.
[0054]
As shown in FIG. 7B, the seven-stage ring oscillator 131 included in the VCO 124 is a loop circuit in which seven inverter elements are connected in series, and the output of each inverter element is output signals phi1 to phi7. It becomes. A control voltage Vc is applied to each inverter element.
[0055]
Next, the strobe creation circuit 113 will be described. FIG. 8 is a circuit diagram showing a configuration for generating strobe signals stb1 to stb7 in the strobe generation circuit. FIG. 9 is a circuit diagram showing a configuration for generating strobe signals stb1 ′ to stb7 ′ in the strobe generating circuit. FIG. 10 is a circuit diagram showing a configuration for generating strobe signals stb1 ″ to stb7 ″ in the strobe generation circuit.
[0056]
The strobe generation circuit 113 uses the strobe generation circuits 113a to 113c from the output signals phi1 to phi7 of the PLL circuit 112 to supply an appropriate strobe signal according to the presence or absence of skew between the 7-bit serial data and the clock signal CLKIN. Strobe signals stb1 to stb7, strobe signals stb1 'to stb7', and strobe signals stb1 "to stb7", respectively.
[0057]
As shown in FIG. 8, the strobe generation circuit 113a receives the output signals phi1 to phi7 of the PLL circuit 112 at the clock input terminals CK of the seven D flip-flops d11 to d17, and phi1, phi4, phi7, phi3, phi6. , Phi2, and phi5 are connected so as to be input in this order. Further, only the D flip-flop d11 that inputs the output signal phi1 to the clock input terminal connects the output terminal / Q to the data input terminal D. Further, the output terminals Q of the D flip-flops d11 to d16 are connected to the data input terminals D of the next-stage D flip-flops d12 to d17, respectively. The signals output from the output terminals Q of the D flip-flops d11 to d17 are referred to as strobe signals stb1 to stb7. Note that the strobe signals output from the output terminals Q of the D flip-flops d11 to d17 are in the order of stb4, stb3, stb2, stb1, stb7, stb6, and stb5.
[0058]
As shown in FIG. 9, the strobe generation circuit 113b outputs the output signals phi1 to phi7 of the PLL circuit 112 to the clock input terminals CK of the seven D flip-flops d21 to d27, and phi2, phi6, phi3, phi7, phi4. , Phi1, and phi4 are connected so as to be input in this order. Further, only the D flip-flop d21 that inputs the output signal phi2 to the clock input terminal connects the output signal phi5 to the data input terminal D. Further, the output terminals Q of the D flip-flops d21 to d26 are connected to the data input terminals D of the D flip-flops d22 to d27 at the next stage, respectively. The signals output from the output terminals Q of the D flip-flops d21 to d27 are referred to as strobe signals stb1 ′ to stb7 ′. Note that the strobe signals output from the output terminals Q of the D flip-flops d21 to d27 are in the order of stb1 ′ to stb7 ′.
[0059]
As shown in FIG. 10, the strobe generation circuit 113c outputs the output signals phi1 to phi7 of the PLL circuit 112 to the clock input terminals CK of the seven D flip-flops d31 to d37, phi4, phi1, phi5, phi2, phi6. , Phi3, and phi7, so that they are input in this order. Further, only the D flip-flop d31 that inputs the output signal phi4 to the clock input terminal connects the output signal phi7 to the data input terminal D. Further, the output terminals Q of the D flip-flops d31 to d36 are connected to the data input terminals D of the next-stage D flip-flops d32 to d37, respectively. The signals output from the output terminals Q of the D flip-flops d31 to d37 are referred to as strobe signals stb1 "to stb7". Note that the strobe signals output from the output terminals Q of the D flip-flops d31 to d37 are in the order of stb1 "to stb7".
[0060]
The strobe generation circuits 113a to 113c are configured by basic flip-flops. However, the strobe signals stb1 to stb7, the strobe signals stb1 ′ to stb7 ′, and the strobe signals stb1 ″ to stb7 are formed from the basic flip-flops. Other configurations may be used as long as the circuit generates ″.
[0061]
Next, the strobe selection circuit 114 will be described. FIG. 11 is a circuit diagram showing input / output signals of the strobe selection circuit. The strobe selection circuit 114 receives as input signals strobe signals stb1 to stb7, strobe signals stb1 'to stb7', and strobe signals stb1 "to stb7". Control signals S1 to S9 are input from the skew detection circuit 115 as control signals. Further, any one of strobe signals stb1 to stb7, strobe signals stb1 ′ to stb7 ′, or strobe signals stb1 ″ to stb7 ″ is output as an output signal.
[0062]
The strobe selection circuit 114 is configured by a MUX (multiplexer) circuit or the like, and selects an appropriate strobe signal based on the detection result of the skew detection circuit 115. That is, when there is no skew, the strobe signals stb1 to stb7 are selected for each bit data of the serial data. On the other hand, when the skew occurs because the data is delayed, the strobe signals stb1 "to stb7" are selected. Further, when a skew occurs due to the advance of data, the strobe signals stb1 ′ to stb7 ′ are selected. Therefore, a strobe that constantly becomes the center of each bit data of the serial data is selected.
[0063]
Next, the skew detection circuit 115 will be described. FIG. 12 is a circuit diagram showing a schematic configuration of the skew detection circuit. The skew detection circuit 115 detects a pattern in which only one bit in the serial data is transitioned. For example, stb3 to stb5, stb3 ′ to stb5 ′, stb3 ″ to D3, D4, and D5 including D4 that is transiting only one bit in the 7-bit serial data D [1: 7] are generated by the strobe generation circuit. Each strobe signal of stb5 ″ is used as a clock input.
[0064]
In this case, as shown in FIG. 12, stb3 to stb5 and stb3 ′ to stb5 ′ generated by the strobe generation circuit are connected to the clock input terminals CK of the nine D flip-flops d41 to d49 constituting the skew detection circuit 115. , Stb3 ″ to stb5 ″ are input in the order of stb3, stb3 ′, stb3 ″, stb4, stb4 ′, stb4 ″, stb5, stb5 ′, stb5 ″. Also, each of the D flip-flops d41 to d49. A serial data input is connected to the data input terminal D. Output signals from the output terminals Q of the D flip-flops d41 to d49 are input to the strobe selection circuit 114 as control signals S1 to S9.
[0065]
Next, the overall operation of the serial / parallel converter 101 will be described with reference to FIG. FIG. 13 is a timing chart of input / output signals of each unit in the serial / parallel converter 101. As shown in FIG. 13, 7-bit serial data is input to the serial / parallel converter 101 at the falling timing of the clock signal CLKIN.
[0066]
As described above, by setting the frequency dividing ratio of the frequency divider 125 of the PLL circuit 112 to 1/2, the VCO 124 oscillates at twice the frequency of the clock signal CLKIN input as the reference signal fr. The tap output signals phi1 to phi7 have signal waveforms that change at the timing shown in FIG.
[0067]
At this time, if the clock signal CLKIN is a rectangular wave with a period T, the output signal phi1 becomes a rectangular wave with a period T / 2, and the output signal phi1 falls at the falling timing of the clock signal CLKIN. Further, since the frequency division ratio N = 2 of the frequency divider 125, the output signal phi2 is a rectangular wave having a period T / 2 as in the case of the output signal phi1, and is composed of a seven-stage ring oscillator (M = 7). Since this is the first-stage tap output, it is delayed by T / 14 and becomes the inverted waveform of the output signal phi1. Similarly, the output signal phi3 is delayed by T / 14 from the output signal phi2 and has an inverted waveform of the output signal phi2. The same applies to the output signals phi4 to phi7, and fluctuates at the timing shown in FIG.
[0068]
When the output signals phi1 to phi7 are input to the strobe generation circuit 113, the strobe signals stb1 to stb7, the strobe signals stb1 ′ to stb7 ′, and the strobe signals stb1 ″ to stb7 ″ are output from the strobe generation circuits 113a to 113c.
[0069]
For example, the strobe signal stb1 is a rectangular wave with a period T, and rises at approximately the center value at D1 of 7-bit serial data. The strobe signal stb1 ′ has a period T and is advanced by T / 14 with respect to the strobe signal stb1. The strobe signal stb1 ″ has a period T and is delayed by T / 14 with respect to the strobe signal stb1.
[0070]
The relationship between the strobe signals stb2 ′ to stb7 ′ and the strobe signals stb2 ″ to stb7 ″ with respect to the other strobe signals stb2 to stb7 is the same.
[0071]
Next, the skew detection circuit 115 performs a detection operation on the following 7-bit serial data.
D [1: 7] = “0001000” (P1)
D [1: 7] = “1110111” (P2)
That is, the detection is performed for the pattern in which only one bit is changed in the serial data. In the case of the above pattern (P1) and pattern (P2), strobe signals stb3 to stb5 generated by the strobe generation circuit including D3, D4, and D5 including D4 in which only one bit in D [1: 7] is transitioned. The strobe signals stb3 ′ to stb5 ′ and the strobe signals stb3 ″ to stb5 ″ are latched by the latch circuit having the configuration shown in FIG. 12 and the result is determined based on the result.
[0072]
First, the skew detection circuit 115 performs a detection operation on the pattern (P1) and the pattern (P2) using the strobe signals stb3 to stb5, the strobe signals stb3 ′ to stb5 ′, and the strobe signals stb3 ″ to stb5 ″.
[0073]
FIG. 14 is a skew detection operation and strobe selection schematic diagram (when pattern (P1) is detected without skew) in the embodiment of the present invention when 7-bit serial data is input. FIG. 15 is a skew detection operation and strobe selection schematic diagram (when pattern 2 is detected without skew) in the embodiment when inputting 7-bit serial data according to the present invention. FIG. 16 is a skew detection operation and strobe selection schematic diagram (pattern (P1) is detected and skew is present <data is delayed with respect to CLKIN>) in the embodiment of the present invention when 7-bit serial data is input. . FIG. 17 is a skew detection operation and strobe selection schematic diagram (when pattern (P2) is detected-skew <data is delayed with respect to CLKIN>) in the embodiment when inputting 7-bit serial data according to the present invention. . FIG. 18 is a skew detection operation and strobe selection schematic diagram in the embodiment of the present invention when 7-bit serial data is input (detection of pattern (P1)-with skew <when data is advanced with respect to CLKIN>). . FIG. 19 is a skew detection operation and strobe selection schematic diagram in the embodiment when inputting 7-bit serial data according to the present invention (when pattern (P2) is detected and skew is present <data is advanced with respect to CLKIN>). .
[0074]
When there is no skew, the result of detection of the pattern (P1) by the skew detection circuit 115 is “000111000” as shown in FIG. Similarly, the result detected for the pattern (P2) is “111000111” as shown in FIG.
[0075]
When there is a skew because of data delay, the result of detection of the pattern (P1) by the skew detection circuit 115 is “0000011100” as shown in FIG. Similarly, the result detected for the pattern (P2) is “111100011” as shown in FIG.
[0076]
When there is a skew because data advances, the result of detection of the pattern (P1) by the skew detection circuit 115 is “001110000” as shown in FIG. Similarly, the result detected for the pattern (P2) is “110001111” as shown in FIG.
[0077]
These detection results are output to the strobe selection circuit 114. As shown in FIGS. 14 and 15, in the strobe selection circuit 114, if “000111000” or “111000111”, which is a detection result when there is no skew, is input to the input terminal IN of the strobe selection circuit 114, The signals stb1 to stb7 are selected and this strobe signal is supplied to the serial / parallel conversion logic circuit 111.
[0078]
As shown in FIGS. 16 and 17, when the detection result “000011100” or “111100011” when the serial data is delayed with respect to the clock CLKIN is input to the input terminal IN of the strobe selection circuit 114, the strobe The signals stb 1 ″ to stb 7 ″ are selected and this strobe signal is supplied to the serial / parallel conversion logic circuit 111.
[0079]
As shown in FIGS. 18 and 19, when the detection result “001110000” or “110001111” when the serial data is advanced with respect to the clock CLKIN is input to the input terminal IN of the strobe selection circuit 114, the strobe The signals stb 1 ′ to stb 7 ′ are selected and this strobe signal is supplied to the serial / parallel conversion logic circuit 111.
[0080]
For other combinations of detection results, the strobe signals stb1 to stb7 are initially selected, and the current output is maintained for other combinations of detection results after the second time. As a result, when a combination of other serial data patterns is input, strobe selection can be performed for all detection result values that the detection circuit can take, and malfunctions can be avoided.
[0081]
In this way, even when the serial data input signal is skewed with respect to the clock signal CLKIN due to the influence of the operating environment such as manufacturing variation and operating temperature, a certain pattern is self-detected and the strobe of the regularly created strobe A more appropriate strobe can be selected from the inside. Thereby, a stable serial / parallel converter can be provided.
[0082]
Further, by forming the serial / parallel conversion device on a semiconductor substrate, it is possible to provide a semiconductor device that performs serial / parallel conversion stably.
[0083]
In the present embodiment, an embodiment using three strobes per bit of serial data is shown. However, the frequency ratio of the input signal to the strobe generating circuit is changed by changing the frequency division ratio of the frequency divider of the PLL circuit. By increasing, the number of strobe signals for skew detection can be increased. This is because the strobe generation circuit has a configuration using D flip-flops, so that the number of strobe signals to be generated increases as the number of edges that transition in unit time increases as the input frequency increases. Can do.
[0084]
As described above, by increasing the number of strobe signals allocated per bit of serial data, the resolution of skew detection (adjustment) can be increased, and the skew can be detected with higher accuracy. In addition, since an appropriate strobe can be selected, a stable serial / parallel conversion circuit and a semiconductor device can be provided.
[0085]
[Second Embodiment]
FIG. 20 is a block diagram showing a schematic configuration of the serial-parallel converter according to the second embodiment of the present invention. The serial-parallel converter 201 is a serial-parallel conversion logic circuit 211 that converts N-bit serial data into N-bit parallel data, and a strobe signal for causing the serial-parallel conversion logic circuit 211 to perform serial-parallel conversion. A PLL circuit 212 to be created, a strobe timing generation circuit 213 which is a strobe creation circuit, a strobe selection circuit 214 for selecting an optimum strobe signal, a skew detection circuit 215 for detecting a skew between a data signal and a clock signal, and serial data , That is, an edge detection circuit 216 that detects the rise or fall of serial data.
[0086]
The configuration and operation of each unit in the serial / parallel converter 201 will be described below. First, the PLL (Phase Locked Loop) circuit 12 will be described. FIG. 21 is a block diagram showing a schematic configuration of a PLL circuit of the serial / parallel converter according to the second embodiment of the present invention. The PLL circuit 212 includes a phase comparator 221, a charge pump 222, a loop filter 223, a VCO (voltage controlled oscillator) 224, and a frequency divider N225. Each part of the PLL circuit 212 operates in the same manner as the general PLL circuit 12 shown in FIG.
[0087]
Next, the configuration of the VCO 224 will be described. As shown in FIG. 21, the VCO 224 of the present invention is configured to include an M-stage (M: odd number) ring oscillator 231 whose oscillation frequency changes according to an input control voltage (Vc). In the present invention, tap output signals PS <b> 1 to PS (M) output from each tap of the M inverter elements constituting the ring oscillator 231 are used as the output of the PLL circuit 212. Further, the tap output signal PS1 is input to the frequency divider 225, frequency-divided, and fed back to the phase comparator 221 as a feedback signal (fp).
[0088]
With this configuration, the tap output signals PS1 to PS (M) that are output from the PLL circuit 212 have a frequency that is a frequency division ratio (N) times the reference signal (fr), and the period of the reference signal (fr). If T is T, each phase is an output signal delayed by T / (N · M).
[0089]
Next, the strobe timing generation circuit 213 will be described. When the tap output signals PS1 to PS (M) output from the PLL circuit 212 are input, the strobe timing generation circuit 213 outputs a plurality of strobe signals. That is, the first data strobe signals PST1 to PST (R) are output to the strobe selection circuit 214. Also, second data strobe signals DPST1 to DPST (R) corresponding to the skew adjustment resolution are output to the skew detection circuit 215.
[0090]
The edge detection circuit 216 detects a rising edge of the serial data Ds and outputs an edge detection signal EDDs. FIG. 22 is an example of a circuit diagram illustrating a schematic configuration of the edge detection circuit. As an example, the edge detection circuit 216 is a differentiation circuit including an AND gate 221 and an odd number of NOT gate chains 222 (five in the figure). The rising edge of the serial data Ds can be detected by the AND gate 221 constituting this differentiation circuit. Further, if a NOR gate is used instead of the AND gate 221, a falling edge can be detected.
[0091]
The skew detection circuit 215 latches the rising edge detection signal EDDs of the serial data Ds with the second data strobe signal DPST from the strobe timing generation circuit 213, and outputs the skew detection signal SD as a result. A specific configuration of the skew detection circuit 215 is shown in FIG. FIG. 23 is a circuit diagram showing a schematic configuration of the skew detection circuit. The skew detection circuit 215 includes R D flip-flops d231-1 to d231-R. The rising edge detection signal EDDs of serial data is input to the data input terminals D of the D flip-flops d231-1 to d231-R. The second data strobe signals DPST1 to DPST (R) generated by the strobe timing generation circuit 213 are input to the clock input terminals CK of the D flip-flops d231-1 to d231-R, respectively. The output signals from the output terminals Q of the D flip-flops d231-1 to d231-R are input to the strobe selection circuit 214 as the skew detection signal SD.
[0092]
The strobe selection circuit 214 is configured by MUX or the like. Further, when the skew detection signal SD is supplied, the strobe selection circuit 214 selects an appropriate data strobe according to the combination of the skew detection signals SD, that is, the state of occurrence of the skew, and supplies the strobe to the serial / parallel conversion circuit 211. Supply signal.
[0093]
The serial / parallel conversion circuit 211 converts serial data into parallel data using the optimum data strobe signal output from the strobe selection circuit 214.
[0094]
Here, the skew detection operation between the serial data Ds and the clock CK in the second embodiment of the present invention will be described with reference to FIG. FIG. 24 is a timing chart for explaining a skew detection operation between the serial data Ds and the clock CK. 24A shows a case where there is no skew between the clock CK and the serial data Ds, FIG. 24B shows a case where the serial data Ds is delayed with respect to the clock CK, and FIG. This shows a case where the serial data Ds is advanced. In the following description, a case where the edge detection circuit 216 detects the rising edge of the serial data Ds and performs skew detection from the edge detection signal will be described.
[0095]
When the serial data Ds is input to the edge detection circuit 216, the rising edge of the serial data is detected as shown in FIG. That is, in the edge detection circuit 216, the serial data Ds is input to one port of the AND gate 221 and also to the other port of the AND gate 221 through the odd-numbered NOT gate chain 222. Detect edges. The detection pulse width can be controlled by increasing / decreasing the number of odd-numbered NOT gate chains.
[0096]
The skew detection circuit 215 latches the detected edge detection signal EDDs with the data strobe signal DPST generated by the strobe timing generation circuit 213. The result is output to the strobe selection circuit 214 as a detection signal SD. At this time, the skew detection circuit 215 outputs a skew detection signal SD corresponding to the skew. That is, when there is no skew between the clock CK and the serial data Ds, SD [2: 0] = [0 1 0] is output, for example, as shown in FIG. When the serial data Ds is delayed with respect to the clock CK, for example, SD [2: 0] = [0 0 1] is output as shown in FIG. Further, when the serial data Ds is advanced with respect to the clock CK, SD [2: 0] = [1 0 0] is output as shown in FIG. 24C, for example. In FIG. 24, the detection resolution (skew adjustment resolution) R is shown as 3 bits.
[0097]
The strobe selection circuit 214 is supplied with the first data strobe signal PST generated by the strobe timing generation circuit 213, and a combination of results obtained by latching the edge detection signal EDDs, that is, a strobe signal corresponding to the skew detection signal SD. It is set as the structure of the MUX which selects and outputs. Then, the strobe selection circuit 214 selects the optimum strobe signal ST and supplies it to the serial / parallel conversion circuit 211. The serial / parallel conversion circuit 211 converts serial data into parallel data by the optimum strobe signal ST.
[0098]
Next, the configuration of the serial / parallel converter according to the second embodiment of the present invention will be described with a specific example. FIG. 25 is a timing chart of serial data input. In serial data transmission, as shown in FIG. 25, predetermined bit data (7-bit data in the figure) is normally mapped and transmitted during one clock cycle. The case where the serial / parallel converter converts 7-bit serial data into parallel data and sets the skew adjustment resolution to 3 bits will be described below. First, the configuration of the serial / parallel converter will be described. FIG. 26 is a circuit diagram showing the configuration of a specific example of the serial / parallel converter. As shown in FIG. 26, the serial / parallel converter 301 converts the serial / parallel conversion logic circuit 311 into serial / parallel conversion logic circuit 311 which converts N-bit serial data into N-bit parallel data. PLL circuit 312 for generating a strobe signal for executing the operation, a strobe timing generation circuit 313 which is a strobe generation circuit, a strobe selection circuit 314 for selecting an optimal strobe signal, and a skew between a data signal and a clock signal are detected. It is composed of a skew detection circuit 315 and an edge detection circuit 316 that detects a transition (rise or fall) of serial data.
[0099]
FIG. 27 is a block diagram showing a configuration of the PLL circuit 312. In the PLL circuit 312 shown in FIG. 21, the frequency dividing ratio of the frequency divider 225 is N = 2, and the number of stages of the ring oscillator 231 of the VCO 224 is M = 7. That is, the configuration includes a phase comparator 321, a charge pump 322, a loop filter 323, a VCO 324, and a frequency divider 325, and the operation of each unit is as described with reference to FIG.
[0100]
The ring oscillator 331 having a seven-stage configuration included in the VCO 324 is a loop circuit in which seven stages of inverter elements are connected in series, and outputs of the inverter elements are tap output signals PS1 to PS7. Further, a control voltage Vc that is an output of the loop filter 323 is applied to each inverter element.
[0101]
Next, the strobe timing generation circuit 313 will be described. FIG. 28 is a circuit diagram showing a configuration of the PST generation circuit. FIG. 29 is a circuit diagram showing a configuration of a DPST generation circuit. As shown in FIG. 28, the PST generating circuit 313a that generates the first data strobe signal PST includes 14 D flip-flops d321 to d334. The odd-numbered D flip-flop has the clock input terminal CK high active, and the even-numbered D flip-flop has the clock input terminal CK low active. Further, tap output signals PS1 to PS7 of the PLL circuit 312 are connected to clock input terminals CK of the D flip-flops d321 to d327 and D flip-flops d328 to d334, respectively, in this order. Further, only the D flip-flop d321 connects the output terminal / Q to the data input terminal D. Further, the output terminals Q of the D flip-flops d321 to d333 are connected to the data input terminals D of the next D flip-flops d322 to d334, respectively. The signals output from the output terminals Q of the D flip-flops d321 to d334 are referred to as first data strobe signals PST1 to PST14.
[0102]
The DPST generation circuit 313b that generates the second data strobe signal DPST has a configuration including four D flip-flops d341 to d344 as shown in FIG. In the D flip-flop d343, the clock input terminal CK is active low, and in the other D flip-flops, the clock input terminal CK is active high. PS1, PS6, PS5 and PS4 selected from the output signal of the PLL circuit 112 are connected to the clock input terminals CK of the four D flip-flops d341 to d344, respectively, in this order. The D flip-flop d321 connects the output terminal / Q to the data input terminal D. Further, the output terminals Q of the D flip-flops d341 and d342 and the output terminal / Q of d343 are connected to the data input terminals D of the D flip-flops d342 to d344 in the next stage, respectively. The signals output from the output terminal Q of the D flip-flop d342 and the output terminals / Q of the D flip-flops d343 and 344 are referred to as second strobe signals DPST3 to DPST1.
[0103]
Note that the combination of input signals of the DPST generation circuit 313b shown in FIG. 29 is intended to determine the presence or absence of skew for D1 in the serial data bit, and the second data strobe is used using PS1, PS4, PS5, and PS6. The signal DPST1 to DPST3 are obtained in combination. That is, it is possible to easily set a serial data bit for detecting a skew and create a DPST signal corresponding to the set bit position by changing a combination of input signals (a combination of PS signals).
[0104]
As shown in FIGS. 28 and 29, the DPST generation circuit and the PST generation circuit in the strobe timing generation circuit 313 input the tap output signals PS1 to PS7 to the circuit constituted by the D flip-flops as described above. The first data strobe signals PST1 to PST14 and the second data strobe signals DPST1 to DPST3 can be easily created. Further, various variations of the first data strobe signal PST and the second data strobe signal DPST can be created by combining the tap output signals PS1 to PS7.
[0105]
Next, the edge detection circuit 316 has the configuration described based on FIG.
[0106]
Next, the configuration of the skew detection circuit 315 will be described. FIG. 30 is a circuit diagram showing a configuration of the skew detection circuit. The skew detection circuit 315 has three D flip-flops d351 to d353. In each of the D flip-flops d351 to d353, the clock input terminal CK is high active. Further, the second data strobe signals DPST1 to DPST3 output from the strobe timing generation circuit 313 are connected to the clock input terminals CK of the D flip-flops d351 to d353, respectively, in this order. In addition, the edge detection signal EDDs output from the edge detection circuit 316 is connected to the data input terminals D of the D flip-flops d351 to d353. The output terminals Q of the D flip-flops d351 to d353 are connected to the select terminal S of the strobe selection circuit 314 so that the skew detection signals SD1 to SD3 are input.
[0107]
Next, the configuration of the strobe selection circuit 314 will be described. FIG. 31 is a circuit diagram showing the configuration of the strobe selection circuit. The strobe selection circuit 314 includes a MUX, and outputs signals selected from the first data strobe signals PST1 to PST14 according to the select signal S as strobe signals ST1 to ST7.
[0108]
Next, the configuration of the serial / parallel conversion circuit 311 will be described. FIG. 32 is a circuit diagram showing the configuration of the strobe selection circuit. The serial / parallel conversion circuit 311 includes seven D flip-flops d361 to d367. In each of the D flip-flops d361 to d367, the clock input terminal CK is high active. The strobe signals ST1 to ST7 output from the strobe selection circuit 314 are connected to the clock input terminals CK of the D flip-flops d361 to d367, respectively, in this order. In addition, the serial data Ds is connected to the data input terminals D of the D flip-flops d361 to d367. The signals D1 to D7 output from the output terminals Q of the D flip-flops d361 to d367 are parallel data.
[0109]
Next, in the serial / parallel conversion device 301 having the above-described configuration, the skew state is divided into three patterns for a series of operations when a skew is actually present between the clock CK and the serial data Ds. The skew detection, strobe selection, and serial / parallel conversion operations will be described in more detail. FIG. 33 is an operation timing chart when there is no skew between the serial data Ds and the clock CK in the serial-to-parallel converter of the present invention.
[0110]
The 7-bit serial data Ds input to the serial / parallel converter 301 is data that is at a high level at the input timings D1, D4, and D7 as shown in FIG. The rising timing of the clock signal CK is substantially the same as the rising timing at the input timing D1 of the serial data Ds. Therefore, there is no skew between the clock CK and the serial data Ds. A series of operations in each part of the serial / parallel converter 301 in this case is as follows. That is, the edge detection circuit 316 detects the rising edge of the serial data Ds, and the edge detection signal EDDs is output substantially simultaneously with the rising timing of the serial data Ds. Subsequently, the edge detection signal EDDs is latched by the second data strobe signals DPST1 to DPST3 regularly generated by the DPST generation circuit in the strobe timing generation circuit 313.
[0111]
As shown in FIG. 33, skew detection signals SD1 to SD3 = [0 1 0] are detected as a result of latching. The skew detection signal SD is supplied to the data strobe selection circuit 314. The strobe signals ST1 to ST7 corresponding to the SD signal are selected by the first data strobe signals PST1 to PST14, and output to the serial / parallel conversion circuit. Is converted to parallel data.
[0112]
Here, when the skew detection signals SD1 to SD3 = [0 1 0] are supplied to the select terminal S of the data strobe selection circuit 214, that is, when there is no skew, the selected strobe is the first strobe shown in FIG. The MUX is configured to be the data strobe signals PST2, PST4, PST6, PST8, PST10, PST12, and PST14. As a result, ST1 = PST2, ST2 = PST4, ST3 = PST6, ST4 = PST8, ST5 = PST10, ST6 = PST12, ST7 = PST14 are output to the serial / parallel conversion circuit 211 as the strobe signal ST. A serial / parallel conversion operation is performed using .about.ST7.
[0113]
As shown in FIG. 33, the strobe signals ST1 to ST7 are located at the data center of each bit D1 to D7 of the serial data, and stable serial / parallel conversion can be performed in the serial / parallel conversion circuit. .
[0114]
Next, as a second pattern, a case where there is a skew between the serial data Ds and the clock CK and the serial data Ds is delayed with respect to the clock CK will be described with reference to FIG. FIG. 34 is an operation timing chart when the serial data Ds is delayed with respect to the clock CK in the serial-parallel converter of the present invention.
[0115]
The 7-bit serial data Ds input to the serial / parallel converter 301 is data at a high level at the input timings D1, D4, and D7 as shown in FIG. The rising timing of the clock signal CK is input timing D7 'earlier than the rising timing at the input timing D1 of the serial data Ds. Therefore, the serial data Ds is delayed with respect to the clock CK, and there is a skew between the clock CK and the serial data Ds. A series of operations in each part of the serial / parallel converter 301 in this case is as follows. In the serial / parallel converter 301, the edge detection circuit 316 detects the rising edge of the serial data Ds and outputs an edge detection signal EDDs to the skew detection circuit 315. The edge detection signal EDDs is latched in the skew detection circuit 315 by the second data strobe signals DPST1 to DPST3 generated by the tap output signals PS1 to PS7 in the DPST generation circuit in the strobe timing generation circuit 313.
[0116]
As a result of latching, skew detection signals SD1 to SD3 = [0 0 1] are detected. The skew detection signal SD is supplied to the data strobe selection circuit 314. Strobe signals ST1 to ST7 corresponding to the skew detection signal SD are selected from the first data strobe signals PST1 to PST14, and the serial / parallel conversion circuit 311 is selected. The serial data Ds is output and converted into parallel data PD. At this time, the data strobe selection circuit 314 is selected and output from the first data strobe signals PST1 to PST14 according to the select signal S. The first data strobe signals PST1 to PST14 are generated by the PST generation circuit in the strobe timing generation circuit 313.
[0117]
When the skew detection signals SD1 to SD3 = [0 0 1] are supplied to the select terminal S of the data strobe selection circuit 314, the MUX is configured such that the following first data strobe signal is selected. That is, PST3, PST5, PST7, PST9, PST11, PST13, and PST1. As a result, ST1 = PST3, ST2 = PST5, ST3 = PST7, ST4 = PST9, ST5 = PST11, ST6 = PST13, ST7 = PST1 to the serial / parallel conversion circuit 311 as the strobe signal ST to the serial / parallel conversion circuit 311. Output.
[0118]
In the strobe signals ST1 to ST7 selected in this way, even if there is a skew in the serial data Ds with respect to the clock CK and the serial data Ds is delayed with respect to the clock CK, the data in each bit D1 to D7 of the serial data Located in the center. In other words, even if there is a skew, it is possible to perform strobe at the center position of the serial data bit, so that the serial / parallel conversion circuit 311 can perform stable serial / parallel conversion.
[0119]
Next, as a third pattern, a case where there is a skew between the serial data Ds and the clock CK and the serial data Ds is advanced with respect to the clock CK will be described with reference to FIG. FIG. 35 is an operation timing chart when the serial data Ds advances with respect to the clock CK in the serial-parallel converter of the present invention.
[0120]
The 7-bit serial data Ds input to the serial / parallel converter 301 is data that is at a high level at the input timings D1, D4, and D7 as shown in FIG. The rising timing of the clock signal CK is later than the rising timing at the input timing D1 of the serial data Ds, and is in the middle of the input timing D1. Therefore, the serial data Ds is advanced with respect to the clock CK, and there is a skew between the clock CK and the serial data Ds. A series of operations in each part of the serial / parallel converter 301 in this case is as follows. In the serial / parallel converter 301, the edge detection circuit 316 detects the rising edge of the serial data Ds and outputs an edge detection signal EDDs to the skew detection circuit 315. The edge detection signal EDDs is latched in the skew detection circuit 315 by the second data strobe signals DPST1 to DPST3 generated by the tap output signals PS1 to PS7 in the DPST generation circuit in the strobe timing generation circuit 313.
[0121]
As a result of latching, skew detection signals SD1 to SD3 = [1 0 0] are detected. The skew detection signal SD is supplied to the strobe selection circuit 314. Strobe signals ST1 to ST7 corresponding to the skew detection signal SD are selected from the first data strobe signals PST1 to PST14 and output to the serial / parallel conversion circuit 311. The serial data Ds is converted into parallel data PD. At this time, the data strobe selection circuit 314 is selected from the first data strobe signals PST1 to PST14 according to the select signal S and is output.
[0122]
The MUX may be configured to select the following first data strobe signal when the skew detection signal SD = [1 0 0] is supplied to the select terminal S of the strobe selection circuit 314. That is, the MUX is configured to be the first data strobe signals PTS1, PST3, PST5, PST7, PST9, PST11, and PST13. Thus, the strobe signals ST1 = PST1, ST2 = PST3, ST3 = PST5, ST4 = PST7, ST5 = PST9, ST6 = PST11, ST7 = PST13 are supplied to the serial / parallel conversion circuit 311 as the strobe signal ST. The data is output to the conversion circuit 311.
[0123]
In the strobe signals ST1 to ST7 selected in this way, even if there is a skew in the serial data Ds with respect to the clock CK and the serial data Ds is advanced with respect to the clock CK, the data in each bit D1 to D7 of the serial data Located in the center. In other words, even if there is a skew, strobe can be performed at the center position of the serial data bit, so that the serial / parallel conversion circuit 311 can perform stable serial / parallel conversion.
[0124]
In this way, the rising edge of the serial data Ds is detected, the edge detection signal EDDs is obtained, the skew is detected by latching the edge detection signal EDDs with the second data strobe signals DPST1 to DPST3, and the skew detection signal SD According to the combination, that is, according to the skew state, the data strobe selection circuit 314 selects and outputs the optimum strobe signals ST1 to ST7 to the serial / parallel conversion circuit 311 from the first data strobe signals PST1 to PST15. .
[0125]
Therefore, even if there is a skew in the serial data Ds with respect to the clock CK, the skew can be detected, and an optimum strobe can be selected and supplied to the serial / parallel conversion circuit 311. Also, it is possible to provide a serial / parallel converter capable of receiving stable high-speed serial data.
[0126]
Next, in the above embodiment, the skew adjustment resolution is 3 bits, but the adjustment resolution can be further increased by changing the configuration of the strobe timing generation circuit 313. Details will be described below with reference to FIGS. FIG. 36 is a timing chart of input / output waveforms of each part of the serial / parallel converter. In order to improve the skew adjustment resolution, the skew detection accuracy can be improved by adopting a configuration in which the second data strobe signal DPST has a higher resolution.
[0127]
In the serial / parallel converter 201, the edge detection circuit 216 detects a rising edge and outputs an edge detection signal EDDs. Next, the edge detection signal EDDs is latched by the second data strobe signals DPST1 to DPST (R) regularly generated by the strobe timing generation circuit 213. When there is no skew, as a result of latching, skew detection signals SD1 to SD (X) = [... 0 0 1 0 0. The skew detection signal SD is supplied to the strobe selection circuit 214, and the strobe signals ST1 to ST7 corresponding to the skew detection signal SD are selected from the first data strobe signals PST1 to PST (X), and the serial / parallel conversion circuit 211 is selected. The serial data Ds is converted into parallel data PD.
[0128]
Next, when the serial data Ds is delayed with respect to the clock CK, the rising edge is similarly detected and the edge detection signal EDDs is output. The detection signal EDDs is latched by the second data strobe signals DPST1 to DPST (R). Skew detection signals SD1 to SD (X) = [... 0 0 0 1 0] are obtained, and the strobe selection circuit 214 uses the first data strobe signals PST1 to PST (X) in response to the skew detection signals SD. The optimum strobe is selected and output to the serial / parallel conversion circuit 211 as the strobe signals ST1 to ST7.
[0129]
Further, when the serial data Ds is advanced with respect to the clock CK, the rising edge is similarly detected, and the edge detection signal EDDs is obtained. By latching the edge detection signal EDDs with the second data strobe signals DPST1 to DPST (R), skew detection signals SD1 to SD (R) = [0 1 0 0 0...] Are obtained. According to SD, an optimum strobe signal is selected by the strobe selection circuit 214 from the first data strobe signals PST1 to PST (X), and is output as the strobe signals ST1 to ST7. Serial / parallel conversion is performed by the strobe signals ST1 to ST7.
[0130]
Further, since the second data strobe signal DPST for detecting the skew is regularly generated by the tap output signal PS from the PLL 212, the tap output signal PS is controlled by controlling the number of stages of the ring oscillator 231 constituting the VCO 224. And the number of variations for generating the second data strobe signal DPST can be increased. Accordingly, since the number of PS transitions in the unit serial data is increased, more second data strobe signals DPST and first data strobe signals PST can be generated, so that the resolution can be further improved. Similarly, by increasing the frequency division ratio, it is possible to increase variations for generating the second data strobe signal DPST and the first data strobe signal PST. Therefore, skew detection / adjustment with higher resolution is possible. In other words, by detecting the edge detection signal EDDs with a larger number of second data strobe signals DPST with high resolution, it becomes possible to detect the skew more finely, and even if there is a skew, a stable strobe is always detected. This can be supplied to the parallel conversion circuit 311.
[0131]
In this way, the skew resolution can be made variable. Even if the skew is detected at a higher resolution and the timing of the clock and the serial data is shifted due to the skew by selecting the strobe for serial / parallel conversion according to the detected signal, Since an appropriate serial / parallel conversion strobe can be selected, a stable high-speed serial data receiving apparatus can be provided.
[0132]
Here, in the above embodiment, the example in which the data D1 in the serial data is focused has been described, but the present invention is not limited to this. Of course, the serial / parallel conversion may be performed by paying attention to any bit in the serial data (D1 to D7). Further, in the present invention, since a certain bit in the serial data is focused, a transition of the bit is detected, and a skew state is specified from this detection signal, a specific detection bit is not required in the serial data.
[0133]
In the above embodiment, an example has been described in which a transition for one bit in serial data is detected, and a strobe is selected in common for all bits according to the detection result. It is not limited. For example, if the transition of each bit is detected and the optimum strobe is selected for each bit, it is possible to cope with the skew generated for each bit in the serial data, and it is possible to construct a high-accuracy high-speed serial data receiving system. .
[0134]
Further, by forming the serial / parallel conversion device on a semiconductor substrate, it is possible to provide a semiconductor device that performs serial / parallel conversion stably.
[0135]
【The invention's effect】
According to the present invention, the following effects can be obtained.
[0137]
  (1)The serial-to-parallel converter uses a skew detection circuit to latch serial transmission data using a plurality of strobe signals output from the strobe generation circuit, and to detect the presence or absence of skew from the latched serial transmission data. Therefore, the presence or absence of skew can be reliably detected by a dedicated circuit.
[0138]
  (2)The skew detection circuit detects a skew between the serial transmission data and the clock signal based on the strobe signal generated by the strobe generation circuit and the detection signal output by the edge detection circuit detecting the transition of the serial transmission data. As a result, the skew between the serial transmission data and the clock signal can be detected without requiring specific detection bit data in the serial data. Further, the resolution of skew detection can be made variable by controlling the strobe signal.
[0139]
  (3)By changing the division ratio of the frequency divider and changing the setting of the oscillation frequency of the voltage controlled oscillator, the PLL circuit can change the skew self-correction sensitivity easily because the skew adjustment resolution is variable. Therefore, the serial / parallel conversion accuracy can be improved according to the intended use.
[0140]
  (4)The skew adjustment resolution of the serial-to-parallel converter is T / (M · N, where T is the period of the clock signal, M is the number of stages of the inverter elements constituting the voltage controlled oscillator, and N is the frequency division ratio of the frequency divider. Therefore, the number of strobe signals for skew detection can be increased by changing the frequency division ratio of the frequency divider of the PLL circuit and increasing the input signal frequency to the strobe generation circuit. By increasing the number of strobe signals allocated per bit, it is possible to increase the resolution of skew detection and to detect skew more accurately. In addition, since an appropriate strobe can be selected, a stable serial / parallel conversion circuit and a semiconductor device can be provided.
[0141]
  (5)In the PLL circuit, the control circuit compares the phase of the 1 / N frequency-divided signal and the clock signal, and controls the oscillator so that the phase difference is eliminated. The oscillator is composed of M-stage (M: odd) elements, and each element outputs a tap output signal corresponding to the clock signal. Thus, by changing the number of stages of each element in the oscillator of the PLL circuit, the number of data strobe signals can be increased or decreased, and the skew adjustment resolution can be made variable.
[0142]
  (6)Since the skew detection circuit performs skew detection on the serial data pattern in which only one bit in the input serial transmission data transitions, it is not necessary to code the skew detection bit in the serial data in advance, and any data input can be performed. On the other hand, it is possible to react only when a certain pattern is input, detect skew, and simultaneously perform skew correction.
[0143]
  (7)Since the skew detection means detects skew with respect to 1 bit that transits in the serial transmission data and 1 bit before and after that, the skew can be reliably detected with a small amount of data.
[0144]
  (8)The semiconductor device includes (1) to (1)(7)Since the serial-parallel conversion device according to any one of the above is formed on a semiconductor substrate, a semiconductor device that stably performs serial-parallel conversion can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a serial / parallel converter according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a PLL circuit.
3 is a circuit diagram showing a schematic configuration of a VCO 24. FIG.
FIG. 4 is a circuit diagram showing a schematic configuration of a strobe generation circuit.
FIG. 5 is a timing chart of waveforms at various parts in the serial / parallel converter.
FIG. 6 is a block diagram showing a configuration of a serial / parallel converter in which 7-bit serial data is transmitted in one clock cycle.
7 is a block diagram showing a configuration of a PLL circuit 112 and a circuit diagram showing a configuration of a VCO 124. FIG.
FIG. 8 is a circuit diagram showing a configuration for generating strobe signals stb1 to stb7 in a strobe generating circuit.
FIG. 9 is a circuit diagram showing a configuration for generating strobe signals stb1 ′ to stb7 ′ in the strobe generating circuit.
FIG. 10 is a circuit diagram showing a configuration for generating strobe signals stb1 ″ to stb7 ″ in the strobe generation circuit.
FIG. 11 is a circuit diagram showing input / output signals of a strobe selection circuit.
FIG. 12 is a circuit diagram showing a schematic configuration of a skew detection circuit.
13 is a timing chart of input / output signals of each unit in the serial / parallel converter 101. FIG.
FIG. 14 is a schematic diagram of skew detection operation and strobe selection in the embodiment when inputting 7-bit serial data according to the present invention (when pattern (P1) is detected without skew).
FIG. 15 is a skew detection operation and strobe selection schematic diagram in the embodiment when inputting 7-bit serial data according to the present invention (when pattern (P2) is detected without skew).
FIG. 16 is a skew detection operation and strobe selection schematic diagram (pattern (P1) is detected and skew is present <data is delayed with respect to CLKIN>) in the embodiment when 7-bit serial data is input according to the present invention; .
FIG. 17 is a skew detection operation and strobe selection schematic diagram in the embodiment when inputting 7-bit serial data according to the present invention (detecting pattern (P2) —with skew <when data is delayed with respect to CLKIN>); .
FIG. 18 is a skew detection operation and strobe selection schematic diagram in the embodiment of the present invention when inputting 7-bit serial data according to the present invention (pattern (P1) is detected and skew is present <data is advanced with respect to CLKIN>). .
FIG. 19 is a skew detection operation and a strobe selection schematic diagram (pattern (P2) is detected and skew is present <data is advanced with respect to CLKIN>) in the embodiment of the present invention when 7-bit serial data is input; .
FIG. 20 is a block diagram showing a schematic configuration of a serial / parallel converter according to a second embodiment of the present invention.
FIG. 21 is a block diagram showing a schematic configuration of a PLL circuit of a serial / parallel converter according to a second embodiment of the present invention;
FIG. 22 is an example of a circuit diagram illustrating a schematic configuration of an edge detection circuit;
FIG. 23 is a circuit diagram showing a schematic configuration of a skew detection circuit.
FIG. 24 is a timing chart for explaining a skew detection operation between serial data Ds and a clock CK.
FIG. 25 is a timing chart of serial data input.
FIG. 26 is a circuit diagram showing a configuration of a specific example of a serial / parallel converter.
27 is a block diagram showing a configuration of a PLL circuit 312. FIG.
FIG. 28 is a circuit diagram showing a configuration of a PST generation circuit.
FIG. 29 is a circuit diagram showing a configuration of a DPST generation circuit.
FIG. 30 is a circuit diagram illustrating a configuration of a skew detection circuit.
FIG. 31 is a circuit diagram showing a configuration of a strobe selection circuit.
FIG. 32 is a circuit diagram showing a configuration of a strobe selection circuit.
FIG. 33 is an operation timing chart when there is no skew between the serial data Ds and the clock CK in the serial-parallel converter of the present invention.
FIG. 34 is an operation timing chart when serial data Ds is delayed with respect to clock CK in the serial-to-parallel converter of the present invention.
FIG. 35 is an operation timing chart when serial data Ds is advanced with respect to clock CK in the serial-parallel converter of the present invention.
FIG. 36 is a timing chart of input / output waveforms of each part of the serial-parallel converter.
[Explanation of symbols]
1,101,201,301-serial / parallel converter
11, 111, 211, 311- (serial / parallel conversion) logic circuit
12, 112, 212, 312-PLL circuit
13,113,213,313-strobe generation circuit
14, 114, 214, 314-Strobe selection circuit
15,115,215,315-skew detection circuit
216, 316-edge detection circuit

Claims (8)

A serial / parallel converter for converting serial transmission data into parallel transmission data,
A PLL circuit that divides the clock signal and outputs a plurality of tap output signals;
A strobe generation circuit for generating a plurality of strobe signals having different phases using the plurality of tap output signals;
The serial transmission data is latched using a plurality of strobe signals output from the strobe generation circuit, and the presence / absence of skew between the serial transmission data and the clock signal is detected from the latched serial transmission data, and according to the result A skew detection circuit that outputs a control signal ;
A strobe selection circuit for selecting a strobe signal according to the detected skew;
A logic circuit for converting serial transmission data into parallel transmission data by the selected strobe signal;
A serial-parallel converter characterized by comprising: A serial / parallel converter for converting serial transmission data into parallel transmission data,
A PLL circuit that divides the clock signal and outputs a plurality of tap output signals;
A strobe generation circuit for generating a plurality of strobe signals having different phases using the plurality of tap output signals;
An edge detection circuit for detecting a transition of the serial transmission data and outputting a detection signal ;
Based on the previous SL strobe signal and the detection signal strobe generation circuit creates a skew detection circuit for detecting a skew between the serial transmission data and the clock signal,
A strobe selection circuit for selecting a strobe signal according to the detected skew;
A logic circuit for converting serial transmission data into parallel transmission data by the selected strobe signal;
A serial-parallel converter characterized by comprising: The PLL circuit includes a voltage controlled oscillator and a frequency divider, and the skew adjustment resolution is variable by changing the division ratio of the frequency divider and changing the oscillation frequency setting of the voltage controlled oscillator. The serial-parallel converter according to claim 1 or 2 , wherein When the period of the clock signal is T, the number of stages of the inverter elements constituting the voltage controlled oscillator is M, and the frequency division ratio of the frequency divider is N, the skew adjustment resolution is T / (M · N). The serial / parallel converter according to claim 3 , wherein the serial / parallel converter is provided. The PLL circuit includes an oscillator composed of M-stage (M: odd number) elements, a frequency divider that divides the output of the oscillator by 1 / N, the 1 / N frequency-divided signal, and the phase of the clock signal. And a control circuit that controls the oscillator so as to eliminate a phase difference, and each element of the oscillator outputs the tap output signal corresponding to the clock signal. The serial-parallel converter in any one of 4 thru | or 4 . The skew detection circuit, to the serial data pattern transition only 1 bit serial transmission in data input, serial-parallel conversion according to any one of claims 1 to 5, characterized in that the skew detection apparatus. The serial / parallel converter according to claim 6 , wherein the skew detection unit performs skew detection on one bit that transitions and one bit before and after the bit in serial transmission data. Wherein a formation of the serial-parallel converter according to the semiconductor substrate to any one of claims 1 to 7.

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