JP6517651B2 - Display driver - Google Patents

Description

  The present invention relates to a display driver which drives a display device in accordance with a video signal.

  In a display device, for example, a liquid crystal display panel, a plurality of gate lines extending in the horizontal direction of a two-dimensional screen and a plurality of source lines extending in the vertical direction of the two-dimensional screen cross each other. . At intersections of the gate lines and the source lines, display cells corresponding to the pixels are formed. Furthermore, the liquid crystal display panel is provided with a source driver for applying a gray scale voltage corresponding to the luminance level of each pixel represented by the input video signal to the source line, and a gate driver for applying a scanning signal to the gate line. It is done.

  As a source driver, pieces of display data corresponding to respective pixels on one gate line are individually taken into a plurality of latches, and a gradation voltage corresponding to the pieces of display data taken into each latch is applied to a source line. The following patent documents have been proposed (see, for example, Patent Document 1).

  In the source driver, by causing the display data pieces corresponding to the respective pixels to be taken in to the latches at different timings, it is possible to avoid a state in which the current is concentrated and reduce noise generated with the concentration of the current. ing. Therefore, the source driver is provided with a delay circuit group in which delay circuits for delaying a clock signal are connected in cascade in order to cause a plurality of display data pieces to be taken in each latch at different timings.

JP 2004-301946 A

  By the way, according to the delay circuit group described in Patent Document 1, the circuit scale increases in proportion to the number of stages of the delay circuit, so there is a problem that the device scale of the driver itself increases.

  Therefore, an object of the present invention is to provide a display driver capable of avoiding a state in which current is concentrated and flowing without causing an increase in device size.

  The display driver according to the present invention receives a serial display data signal representing a luminance level as a series of serial bits of K (K is an integer of 2 or more) bits and an input clock signal of a single pulse at predetermined intervals. A display driver having a serial-to-parallel converter for converting the received serial display data signal into display data of K-bit parallel, wherein the serial-to-parallel converter has a delay time of 1 / (2K) of the predetermined cycle. A delay circuit in which first to K.sup.th delay elements having a cascaded circuit are connected in cascade, and output from each of the first to K.sup.th delay elements by supplying the input clock signal to the first delay element. Signal is obtained as the first to Kth delay clock signals of the first cycle, and the Kth delay clock signal of the first cycle is supplied to the first delay element. To obtain a signal output from each of the first to Kth delay elements as a 1st to Kth delay clock signal in a second cycle, and a first to 1st to 1st cycles of the first cycle. The odd-numbered delay clock signal of the Kth delay clock signal and the even-numbered delay clock signal of the first to Kth delay clock signals of the second cycle are A capture clock acquisition unit obtained as a capture clock signal, and sequentially capturing each bit in the series of serial bits represented by the serial display data signal according to the first to Kth capture clock signals And a serial-to-parallel conversion latch for obtaining the K-bit parallel display data.

  In the present invention, first, a display data signal having a series of serial bits of K bits and a clock signal of a single pulse are received at a predetermined cycle, and the clock signal is delayed by a delay circuit to obtain a serial bit sequence. K delayed clock signals synchronized with each bit are generated. Here, the serial bits are converted into parallel data by sequentially capturing each bit in the serial bit sequence according to the K delay clock signals. This avoids a state in which current concentrates and flows as the value of display data changes.

  Furthermore, in the present invention, when generating the K delayed clock signals, the received single pulse clock signal is supplied to the delay circuit, and the delayed clock signal output from the delay circuit is delayed only once. , And K delayed clock signals are generated.

  Therefore, since the circuit scale of the delay circuit can be reduced, the circuit scale of the entire device can be reduced.

It is a figure which shows schematic structure of the display apparatus 100 containing the display driver which concerns on this invention. 5 is a time chart showing an example of data format of differential display data signals SD1 (P, N) to SD4 (P, N) and differential clock signal CLK (P, N). FIG. 2 is a block diagram showing an internal configuration of a serial-to-parallel converter 200. 5 is a circuit diagram showing an internal configuration of a DLL unit 28. FIG. 5 is a time chart showing the internal operation of the DLL unit 28. FIG. 6 is a circuit diagram showing an internal configuration of an SP conversion latch 26a.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a view showing a schematic configuration of a display device 100 including a display driver according to the present invention. In FIG. 1, the display device 20 includes, for example, a liquid crystal display panel or an organic EL panel. On the display device 20, a horizontal scan line S ₁ to S _m of m that extends in the horizontal direction of the two-dimensional screen (m is a natural number of 2 or more), n pieces (n that extends in the vertical direction of the two-dimensional screen Two or more natural numbers) data lines D _{1 to} D _n are formed. A display cell responsible for red display, a display cell responsible for green display, or a display cell responsible for blue display is formed at the intersections of the horizontal scanning lines and the data lines. One pixel of the display device 20 is formed by one set of the display cell responsible for the red display, the display cell responsible for the green display, and the display cell responsible for the blue display.

  Drive control unit 11 receives differential display data signals SD1 (P, N) to SD4 (P, N) and differential clock signal CLK (differential display data signals) transmitted from a host device (not shown). P, N) are received.

  The differential display data signals SD1 (P, N) to SD4 (P, N) and the differential clock signal CLK (P, N) are, for example, FPD-Link (LVDS) transmissions employing Low Voltage Differential Signaling (LVDS) transmission. It has a data format based on Flat Panel Display Link (registered trademark).

  That is, the host device first distributes and allocates each bit of each of red data, green data and blue data corresponding to each pixel based on the video signal to the first to fourth groups. For example, red data represents the luminance level of the red component in the video signal by 7 bits, green data represents the luminance level of the green component in the video signal by 7 bits, and blue data represents the blue component of the video signal. The luminance level is represented by 7 bits. Next, for each group, the positive polarity data signal P including a series of serial bits in which each bit allocated in the group is connected for each group, and the negative polarity obtained by inverting the phase of the data signal P And the data signal N of the Then, the host device displays data signals P and N corresponding to the first group as display data signals SD1 (P, N), and data signals P and N corresponding to the second group as differential display data signals SD2 (P , N) to the drive control unit 11. In addition, the host device transmits data signals P and N corresponding to the third group as differential display data signals SD3 (P, N), and data signals P and N corresponding to the fourth group as differential display data signals SD4. It transmits to the drive control part 11 as (P, N).

  Note that at least one of the differential display data signals SD1 (P, N) to SD4 (P, N) includes bits corresponding to the horizontal synchronization signal and the vertical synchronization signal, respectively.

  Furthermore, as shown in FIG. 2, the host device has a pixel transmission period TS which is a transmission period of one pixel by differential display data signals SD1 (P, N) to SD4 (P, N). A clock signal P is generated. That is, the host device generates a clock signal P including a single positive pulse every pixel transmission cycle TS. Then, the host device transmits the clock signal P of positive polarity and the clock signal N of negative polarity obtained by inverting the phase of the clock signal P to the drive control unit 11 as the differential clock signal CLK (P, N). Do. In the example shown in FIG. 2, the duty ratio of the differential clock signal CLK (P, N) is 0.5.

  The drive control unit 11 supplies a horizontal synchronization detection signal to the scan driver 12 when the horizontal synchronization signal is detected from the differential display data signals SD1 (P, N) to SD4 (P, N).

  Further, drive control unit 11 individually sets 7-bit differential display data signals SD1 (P, N) to SD4 (P, N) in parallel form at a timing based on differential clock signal CLK (P, N). The data is converted into display data pieces, and display data signals PD1 to PD4 each including a series of display data pieces are supplied to the data driver 13.

The scan driver 12 sequentially applies a horizontal scan pulse to each of the horizontal scan lines S _{1 to} S _m of the display device 20 at timing synchronized with the horizontal synchronization detection signal supplied from the drive control unit 11.

The data driver 13 takes in the display data signals PD1 to PD4 described above, and sequentially stores the display data pieces included in these PD1 to PD4. The data driver 13 generates n pixel drive voltages each having a voltage value corresponding to the luminance level represented by the display data piece every time n display data pieces corresponding to one horizontal scanning line are taken. And applied to the data lines D _{1 to} D _n of the display device 20.

  FIG. 3 is a block diagram showing an internal configuration of serial-to-parallel conversion unit 200 included in drive control unit 11. In FIG. 3, differential buffers 21 to 24 respectively generate single display data signals SS1 to SS4 based on a pair of differential display data signals SD1 (P, N) to SD4 (P, N), The data skew adjustment unit 25 is supplied.

  The data skew adjustment unit 25 generates display data signals S1 to S4 obtained by adjusting the phases of the display data signals SS1 to SS4 so that the phase shift between the display data signals SS1 to SS4 becomes zero. The data is supplied to serial / parallel conversion latches (hereinafter, SP conversion latches) 26a to 26d.

  The differential buffer 27 generates a clock signal CK based on the differential clock signal CLK (P, N) described above, and supplies the clock signal CK to a DLL (Delay-Locked Loop) circuit 28.

  The DLL unit 28 generates a clock signal CPQ synchronized with the rising edge of the clock signal CK having a single pulse for each pixel transmission cycle TS and having the same frequency as the clock signal CK, and outputs the clock signal CPQ to the phase comparison unit 29. Supply to Here, the pulse width of the clock signal CPQ is smaller than [1 / (2 · K)] of the pixel transmission cycle TS. At this time, “K” represents the number of serial bits transmitted within the pixel transmission cycle TS, and in the example shown in FIG. 2, the number of serial bits is 7 bits, so K = 7.

  Further, the DLL unit 28 sets a time of [1 / (2 · K)] of the pixel transmission cycle TS as a unit delay time UI, and a signal obtained by delaying the clock signal CPQ by the unit delay time UI as a capture clock signal CP1. Generate

  Further, the DLL unit 28 takes in a signal obtained by delaying the take-in clock signal CP1 by (2 · UI) period as the take-in clock signal CP2, and takes a signal obtained by delaying the corresponding CP2 by (2 · UI) period as the take-in clock signal Generate as CP3. Further, the DLL unit 28 generates a signal obtained by delaying the CP3 by (2 · UI) period as a clock signal CP4 and a signal obtained by delaying the CP4 by (2 · UI) period as a clock signal CP5. Do. Further, the DLL unit 28 generates a signal obtained by delaying the CP5 by (2 · UI) period as the capture clock signal CP6 and a signal obtained by delaying the CP6 by 1 each as the capture clock signal CP7.

  The DLL unit 28 supplies the taken clock signals CP1 to CP7 to each of the SP conversion latches 26a to 26d.

  Furthermore, the DLL unit 28 supplies a signal obtained by delaying the capture clock signal CP7 by the unit delay time UI to the phase comparison unit 29 as the phase comparison clock signal n7Q.

  The DLL unit 28 adjusts the above-mentioned delay time for delaying the capture clock signals CP1 to CP7 in accordance with the phase error signal FC supplied from the charge pump unit 30. For example, the DLL unit 28 shortens the delay time when the phase error signal FC is at a high level, and lengthens the delay time when the phase error signal FC is at a high level.

  The phase comparison unit 29 includes a phase comparator 290, a charge pump unit 300, and a capacitor C1. The phase comparator 290 detects the phase difference between the clock signal CPQ and the phase comparison clock signal n7Q, and supplies a phase difference signal ER indicating the phase difference to the charge pump unit 300. The charge pump unit 300 generates a high voltage and applies the line L1 when the phase difference signal ER indicates a delayed phase, while generating a low voltage when the phase difference signal ER indicates a leading phase, the line L1. Apply. The other end of the capacitor C1 whose one end is set to the ground potential is connected to the line L1.

  When the phase comparison clock signal n7Q is in the delayed phase state with respect to the clock signal CPQ with the above-described configuration, the phase comparison unit 29 sets the phase error signal FC having a high level to the DLL unit via the line L1. Supply to 28. On the other hand, when the phase comparison clock signal n7Q is in an advanced phase with respect to the clock signal CPQ, the phase comparison unit 29 supplies the phase error signal FC having a low level to the DLL unit 28 via the line L1. Do.

The SP conversion latch 26a sequentially and individually captures and holds each bit in the 7-bit serial bit sequence included in the display data signal S1 according to the capture clock signals CP1 to CP7 every pixel transmission cycle TS. Thus, 7-bit parallel display data PQ _1-7 is converted. Then, the SP conversion latch 26a generates a signal composed of a series of display data PQ _1-7 generated for each pixel transmission cycle TS as the above-described display data signal PD1.

The SP conversion latch 26b sequentially and individually takes in and holds each bit in the 7-bit serial bit sequence included in the display data signal S2 according to the capture clock signals CP1 to CP7 every pixel transmission cycle TS. Convert to 7-bit display data PQ _1-7 . Then, the SP conversion latch 26 b generates, as the display data signal PD 2 described above, a signal formed of a series of display data PQ _1-7 generated for each pixel transmission cycle TS.

The SP conversion latch 26c sequentially and individually captures and holds each bit in the 7-bit serial bit sequence included in the display data signal S2 according to the capture clock signals CP1 to CP7 for each pixel transmission cycle TS. Convert to 7-bit display data PQ _1-7 . Then, the SP conversion latch 26c generates, as the above-mentioned display data signal PD3, a signal composed of a series of display data PQ _1-7 generated for each pixel transmission cycle TS.

The SP conversion latch 26d sequentially and individually captures and holds each bit in the 7-bit serial bit sequence included in the display data signal S2 according to the capture clock signals CP1 to CP7 for each pixel transmission cycle TS. Convert to 7-bit display data PQ _1-7 . Then, the SP conversion latch 26d generates a signal composed of a series of display data PQ _1-7 generated for each pixel transmission cycle TS as the above-described display data signal PD4.

  The internal configuration and operation of the DLL unit 28 and the SP conversion latches 26a to 26d will be described below.

  FIG. 4 is a circuit diagram showing an internal configuration of the DLL unit 28, and FIG. 5 is a time chart showing an internal operation of the DLL unit 28. As shown in FIG.

  In FIG. 4, the edge detection unit EJ synchronizes with the rising edge portion of the clock signal CK supplied from the differential buffer 27 and generates a clock signal CPQ having the same frequency as the clock signal CK. As shown in FIG. 5, the pulse width W of the clock signal CPQ is smaller than [1 / (4 · K)] of the pixel transmission period TS. In the example shown in FIG. 5, since the number of serial bits transmitted in the pixel transmission cycle TS is 7 bits, the pulse width W of the clock signal CPQ is smaller than (TS / 28).

  As shown in FIG. 4, the DLL unit 28 includes an edge detection unit EJ, a selector SEL, variable delay elements D1 to D7, a T-type flip flop TF, and AND gates A1 to A7 and AN.

  The edge detection unit EJ supplies the clock signal CPQ to the selector SEL, the reset terminal R of the T-type flip flop TF, and the phase comparison unit 29.

  Selector SEL selects and selects one of clock signal CPQ described above and delayed clock signal n7 supplied from variable delay element D7 in accordance with clock selection signal CS supplied from T-type flip flop TF. The clock signal is supplied to the variable delay element D1. For example, when the clock selection signal CS indicates the logic level 0, the selector SEL selects the delay clock signal n7 and supplies it to the variable delay element D1. On the other hand, when the clock selection signal CS indicates the logic level 1, the selector SEL selects the clock signal CPQ and supplies it to the variable delay element D1.

  The variable delay element D1 sets a signal obtained by delaying the delay clock signal n7 or the clock signal CPQ supplied from the selector SEL by the unit delay time UI as shown in FIG. 5 as the delay clock signal n1 as the variable delay element D2 and the AND gate A1. Supply to

  The variable delay element D2 supplies a signal obtained by delaying the delay clock signal n1 by the unit delay time UI as shown in FIG. 5 as the delay clock signal n2 to the variable delay element D3, the T-type flip flop TF and the AND gate A5.

  The variable delay element D3 supplies a signal obtained by delaying the delay clock signal n2 by the unit delay time UI as shown in FIG. 5 to the variable delay element D4 and the AND gate A2 as the delay clock signal n3.

  The variable delay element D4 supplies a signal obtained by delaying the delay clock signal n3 by the unit delay time UI as shown in FIG. 5 to the variable delay element D5 and the AND gate A6 as the delay clock signal n4.

  The variable delay element D5 supplies a signal obtained by delaying the delay clock signal n4 by the unit delay time UI as shown in FIG. 5 to the variable delay element D6 and the AND gate A3 as the delay clock signal n5.

  The variable delay element D6 supplies a signal obtained by delaying the delay clock signal n5 by the unit delay time UI as shown in FIG. 5 to the variable delay element D7 and the AND gate A7 as the delay clock signal n6.

  The variable delay element D7 supplies a signal obtained by delaying the delay clock signal n6 by the unit delay time UI as shown in FIG. 5 as the delay clock signal n7 to the selector SEL and the AND gates A4 and AN.

  The variable delay elements D1 to D7 adjust the delay time set in each of the variable delay elements D1 to D7 based on the phase error signal FC supplied from the phase comparison unit 29, that is, the unit delay time UI. For example, the variable delay elements D1 to D7 adjust the delay time to be smaller as the level represented by the phase error signal FC is higher.

  T-type flip flop TF is initialized to the state of logic level 1 according to clock signal CPQ, and thereafter, as shown in FIG. 5, the logic level is set each time a rising or falling edge of delayed clock signal n2 is detected. A clock selection signal CS to be inverted is generated. The T-type flip flop TF supplies a clock selection signal CS to the selector SEL and the AND gates A1 to A7 and AN.

  As shown in FIG. 5, while the clock selection signal CS is at the logic level 1, the AND gate AN supplies the delay clock signal n7 as the phase comparison clock signal n7Q to the phase comparison unit 29, while selecting the clock. While the signal CS is in the logic level 0 state, the phase comparison clock signal n7Q maintaining the logic level 0 state is supplied to the phase comparison unit 29.

  As shown in FIG. 5, the AND gate A1 supplies the delay clock signal n1 as the take-in clock signal CP1 to the SP conversion latches 26a to 26d while the clock selection signal CS is in the logic level 1 state. While the clock selection signal CS is at the logic level 0, the AND gate A1 supplies the capture clock signal CP1 maintaining the logic level 0 to the SP conversion latches 26a to 26d.

  As shown in FIG. 5, the AND gate A2 supplies the delay clock signal n3 as the take-in clock signal CP2 to the SP conversion latches 26a to 26d while the clock selection signal CS is at the logic level 0 state. While the clock selection signal CS is at the logic level 1, the AND gate A2 supplies the capture clock signal CP2 maintaining the logic level 0 to the SP conversion latches 26a to 26d.

  As shown in FIG. 5, the AND gate A3 supplies the delay clock signal n5 as the take-in clock signal CP3 to the SP conversion latches 26a to 26d while the clock selection signal CS is at the logic level 0 state. While the clock selection signal CS is at logic level 1, the AND gate A3 supplies the capture clock signal CP3 maintaining the logic level 0 to the SP conversion latches 26a to 26d.

  As shown in FIG. 5, while the clock selection signal CS is at logic level 0, the AND gate A4 supplies the delay clock signal n7 as the take-in clock signal CP4 to the SP conversion latches 26a to 26d. While the clock selection signal CS is at the logic level 1, the AND gate A4 supplies the capture clock signal CP4 maintaining the logic level 0 to the SP conversion latches 26a to 26d.

  As shown in FIG. 5, the AND gate A5 supplies the delay clock signal n2 as the take-in clock signal CP5 to the SP conversion latches 26a to 26d while the clock selection signal CS is at the logic level 0 state. While the clock selection signal CS is at logic level 1, the AND gate A5 supplies the capture clock signal CP5 maintaining the logic level 0 to the SP conversion latches 26a to 26d.

  As shown in FIG. 5, the AND gate A6 supplies the delay clock signal n4 as the take-in clock signal CP6 to the SP conversion latches 26a to 26d while the clock selection signal CS is at logic level 1. While the clock selection signal CS is at the logic level 0, the AND gate A6 supplies the capture clock signal CP6 maintaining the logic level 0 to the SP conversion latches 26a to 26d.

  As shown in FIG. 5, the AND gate A7 supplies the delay clock signal n6 as the take-in clock signal CP7 to the SP conversion latches 26a to 26d while the clock selection signal CS is in the logic level 1 state. While the clock selection signal CS is at the logic level 0, the AND gate A7 supplies the capture clock signal CP7 maintaining the logic level 0 to the SP conversion latches 26a to 26d.

  Hereinafter, the operations of the DLL unit 28 and the phase comparison unit 29 described above will be described with reference to FIG.

  First, in response to the clock signal CPQ, the T-type flip flop TF generates a clock selection signal CS of logic level 1. In response to the clock selection signal CS, the selector SEL supplies the clock signal CPQ to the variable delay element D1. Thereby, as shown in FIG. 5, the variable delay elements D1 to D7 sequentially output the first to seventh delay clock signals n1 to n7 of the first cycle. During this time, in response to the second delay clock signal n2, the T-type flip flop TF causes the clock selection signal CS to transition from the logic level 1 state to the logic level 0 state, as shown in FIG. Thus, the selector SEL supplies the seventh delay clock signal n7 in the first cycle to the variable delay element D1. Thereby, the variable delay elements D1 to D7 sequentially output the first to seventh delay clock signals n1 to n7 in the second cycle as shown in FIG. During this time, the T-type flip flop TF causes the clock selection signal CS to transition from the logic level 0 state to the logic level 1 state as shown in FIG. 5 in response to the second delay clock signal n2.

  Here, the AND gates A1 to A7 as the acquisition clock acquisition unit perform the following operation.

  The AND gate A1 outputs the delay clock signal n1 output from the variable delay element D1 while the clock selection signal is in the logic level 1 state, as a first capture clock signal CP1. The AND gates A2 to A4 receive the odd-numbered variable delay elements D3, D5, D7 of the second to seventh variable delay elements D2 to D7 while the clock selection signal CS is at the logic level 0 state. The output three delayed clock signals n3, n5, n7 are output as second to fourth take-in clock signals CP2 to CP4, respectively. Also, the AND gate A5 outputs the delayed clock signal n2 output from the second variable delay element D2 during a period in which the clock selection signal CS is at the logic level 0 as the fifth capture clock signal CP5. . The AND gates A6 to A7 output from the even-numbered variable delay elements D4 and D6 among the third to seventh variable delay elements D3 to D7 while the clock selection signal CS is in the logic level 1 state. The two delayed clock signals n4 and n6 are output as sixth and seventh acquisition clock signals CP6 and CP7.

  Also, the AND gate AN as the phase comparison clock acquisition unit is a signal output from the seventh variable delay element D7 while the clock selection signal CS is at the logic level 1, that is, the delay of the second round. The clock signal n7 is output as the phase comparison clock signal n7Q. At this time, the phase comparison unit 29 detects a phase difference between the clock signal CPQ as an input clock signal and the phase comparison clock signal n7Q, and generates a phase error signal FC having a level corresponding to the phase difference. Thus, the variable delay elements D1 to D7 adjust their delay times in accordance with the phase error signal FC.

  By the DLL unit 28 and the phase comparison unit 29 described above, the first to the first in the serial bit series of the display data signals S1 to S4 in each pixel transfer cycle TS regardless of the manufacturing variation or the fluctuation of the environmental temperature. Captured clock signals CP1 to CP7 having rising edges appearing at an intermediate timing of each of the seventh bits are generated. Then, the DLL unit 28 supplies these capture clock signals CP1 to CP7 to each of the SP conversion latches 26a to 26d.

  The SP conversion latches 26a to 26d have the same internal configuration. Therefore, the operation of the SP conversion latch will be described below by extracting 26a from among the SP conversion latches 26a to 26d.

  FIG. 6 is a circuit diagram showing an internal configuration of the SP conversion latch 26a. As shown in FIG. 6, the SP conversion latch 26a has D latches FL1 to FL7 whose display data signals S1 are supplied to the respective D terminals.

The clock signal CP1 is supplied to the clock terminal of the D latch FL1. The D latch FL1 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP1 shown in FIG. Thus, D latch FL1, as shown in FIG. 5, takes in the first bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as display data PQ _1.

The clock signal CP2 is supplied to the clock terminal of the D latch FL2. The D latch FL2 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP2 shown in FIG. Thus, D latch FL2, as shown in FIG. 5, it takes in the second bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as display data PQ _2.

The clock signal CP3 is supplied to the clock terminal of the D latch FL3. The D latch FL3 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP3 shown in FIG. Thus, D latch FL3, as illustrated in FIG. 5, takes in the third bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as display data PQ _3.

The clock signal CP4 is supplied to the clock terminal of the D latch FL4. The D latch FL4 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP4 shown in FIG. Thus, D latch FL4, as shown in FIG. 5, takes in the fourth bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as the display data PQ _4.

The clock signal CP5 is supplied to the clock terminal of the D latch FL5. The D latch FL5 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP5 shown in FIG. Thus, D latch FL5, as shown in FIG. 5, takes in the fifth bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as display data PQ _5.

The clock signal CP6 is supplied to the clock terminal of the D latch FL6. The D latch FL6 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP6 shown in FIG. Thus, D latch FL6, as shown in FIG. 5, it takes in the sixth bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as display data PQ _6.

The clock signal CP7 is supplied to the clock terminal of the D latch FL7. The D latch FL7 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP7 shown in FIG. Thus, D latch FL7, as shown in FIG. 5, takes in the seventh bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as display data PQ _7.

Therefore, the SP conversion latch 26a first takes in the first bit in the D latch FL1 among the first to seventh bits in serial form included in the display data signal S1, and the first bit is shown in FIG. as shown in 5, is output as display data PQ ₁ representing the first bit of the display data signal PD1. Next, SP conversion latch 26a is the second bit is input to the D latch FL2, the second bit, and outputs the display data PQ ₂ representing the second bit of the display data signal PD1. That is, at this time, the SP conversion latch 26a simultaneously outputs the display data PQ _1-2 representing the first and second bits in the display data signal PD1 as shown in FIG. Next, SP conversion latch 26a is the third bit is input to the D latch FL3, the third bit, and outputs the display data PQ ₃ showing a third bit of the display data signal PD1. That is, at this point, SP conversion latch 26a outputs the display data PQ _1-3 representing the first to third bit of the display data signal PD1 as shown in FIG. 5 at the same time.

Thereafter, in the same manner, the SP conversion latch 26a sequentially fetches the fourth to seventh bits into the D latches FL4 to FL7, and selects the fourth to seventh bits from the fourth to seventh bits in the display data signal PD1. It sequentially outputs as display data PQ ₄ , PQ ₅ , PQ ₆ , PQ ₇ representing the data.

That is, when the D latch FL7 takes in the final seventh bit in the display data signal S1 within each pixel transmission cycle TS, the SP conversion latch 26a parallels the first to seventh bits in serial form with 7 bits. The display data PQ _1-7 converted to is output.

As described above, the SP conversion latch 26a (26b to 26d) and the DLL unit 28 convert the series of serial bits into the display data PQ _1-7 in parallel form. The output is distributed in time. Therefore, it is avoided that the current which flows with the change of display data concentrates on a temporary point.

  Here, in the DLL unit 28, the selector SEL, the variable delay elements D1 to D7, the T-type flip flop TF, and the AND gates A1 to A7 and AN, the taken clock signals CP1 to CP7 and the phase comparison based on the clock signal CPQ. The clock signal n7Q is generated.

  That is, a signal obtained by delaying the clock signal CPQ by the unit delay time UI is generated as a capture clock signal CP1 for capturing the first bit in the serial bit sequence, and the capture clock signal CP1 is generated by 2 · UI. A delayed signal is generated as a capture clock signal CP2 for capturing the second bit in the serial bit sequence.

  Also, the DLL unit 28 generates a signal obtained by delaying the capture clock signal CP2 by 2 · UI as a capture clock signal CP3 for capturing the third bit in the serial bit sequence, and the capture clock A signal obtained by delaying the signal CP3 by 2 · UI is generated as a taken clock signal CP4 for taking the fourth bit in the serial bit sequence. Also, the DLL unit 28 generates a signal obtained by delaying the capture clock signal CP4 by 2 · UI as a capture clock signal CP5 for capturing the fifth bit in the serial bit sequence, and the capture clock signal A signal obtained by delaying CP5 by 2 · UI is generated as a capture clock signal CP6 for capturing the sixth bit in the serial bit sequence. Further, the DLL unit 28 generates a signal obtained by delaying the capture clock signal CP6 by 2 · UI as a capture clock signal CP7 for capturing the seventh bit in the serial bit sequence.

  Furthermore, in the DLL unit 28, a signal obtained by delaying the clock signal CPQ by the same period as the pixel transmission cycle TS, that is, 14 · UI, in order to correct the phase error occurring in the taken clock signals CP1 to CP7, A phase comparison clock signal n7Q to be compared with the clock signal CPQ is obtained as a phase comparison clock signal n7Q.

  Therefore, originally, in order to obtain the capture clock signals CP1 to CP7 and the phase comparison clock signal n7Q from the clock signal CPQ, a delay circuit that delays the clock signal CPQ by the same period (14 · UI) as the pixel transmission cycle TS It will be necessary. At this time, the circuit scale of the delay circuit becomes larger as the time for delaying the signal becomes longer.

  On the other hand, the delay time in the delay circuit (D1 to D7) used in the DLL unit 28 is a half of the pixel transmission cycle TS, that is, 7 · UI. Therefore, the circuit scale of the delay circuit is approximately 1⁄2 as compared with the case where a delay circuit for delaying the clock signal CPQ by 14 · UI, which is actually the same period as the pixel transmission cycle TS, is employed. The DLL unit 28 includes, in addition to the delay circuits (D1 to D7), T-type flip flops TF, AND gates A1 to A7 and AN. These T-type flip flops TF and AND gates A1 to A7 are included. In general, the circuit scale of and AN is smaller than the circuit scale by the variable delay elements D1 to D7.

  Therefore, if the DLL unit 28 having the configuration shown in FIG. 4 is employed, the scale of the entire apparatus can be reduced.

  In the embodiment described above, the serial-to-parallel converter 200 shown in FIG. 3 is included in the drive controller 11. However, the serial-to-parallel converter 200 may be provided in the data driver 13.

  Further, in the serial-to-parallel conversion unit 200 shown in FIG. 3, the number of bits to be converted in serial-to-parallel conversion is 7 bits, but the number of bits is not limited to 7 bits.

  In short, as a display driver according to the present invention, a serial display data signal (S1 to S4) representing a luminance level by a series of serial bits of K (K is an integer of 2 or more) bits and a single pulse input clock signal ( It is sufficient if it includes a serial-to-parallel converter (200) that receives CPQ) and CPQ every predetermined period (TS) and converts this serial display data signal into K-bit parallel display data (PD1 to PD14). .

  Also, the serial-to-parallel converter may be any as long as it includes the following delay circuit, delay circulation control unit, capture clock acquisition unit and serial-to-parallel conversion latch.

  That is, the delay circuit includes first to Kth delay elements (D1 to D7) each having a delay time of 1 / (2K) of a predetermined cycle. The delay circulation control unit (SEL, TF) supplies the input clock signal to the first delay element (D1) to output the signal output from each of the first to Kth delay elements in the first cycle. The first to Kth delay clock signals (n1 to n7) are obtained. Furthermore, the delay circulation control unit supplies the first delay element with the Kth delay clock signal (n7) of the first cycle to the first delay element to output the signal output from each of the first to Kth delay elements. It is obtained as the first to Kth delayed clock signals (n1 to n7) in the second round. The acquisition clock acquiring unit (A1 to A7, TF) is configured to receive an odd-numbered delay clock signal (n1, n3, n5, n7) of the first to Kth delay clock signals in the first cycle, and The even-numbered delay clock signals (n2, n4, n6) among the first to Kth delay clock signals of the round are obtained as the first to Kth acquisition clock signals (CP1 to CP7). The serial-to-parallel conversion latches (26a to 26d, FL1 to FL7) each bit in the series of serial bits represented by the serial display data signals (S1 to S4) correspond to the first to Kth capture clock signals. By sequentially fetching, display data of K bits parallel is obtained.

11 drive control units 26a to 26d SP conversion latch 28 DLL unit 29 phase comparison units A1 to A7, AN and gates D1 to D7 variable delay element EJ edge detection unit SEL selector selector TFF flip-flop

Claims (4)

A serial display data signal representing a luminance level as a series of serial bits of K (K is an integer of 2 or more) bits and an input clock signal of a single pulse are received at predetermined intervals, and the received serial display data signal A display driver having a serial-to-parallel conversion unit for converting display data to K-bit parallel,
The serial-to-parallel converter
A delay circuit in which first to Kth delay elements each having a delay time of 1 / (2K) of the predetermined cycle are cascaded;
By supplying the input clock signal to the first delay element, the signals output from each of the first to Kth delay elements are obtained as the first to Kth delay clock signals in the first cycle. The Kth delayed clock signal of the first cycle is supplied to the first delay element, and the signals output from each of the first to Kth delay elements are transmitted to the first to the second cycle of the second cycle. A delay circulation control unit obtained as a Kth delay clock signal,
The odd-numbered delay clock signal of the first to K-th delay clock signals of the first cycle and the even-numbered delay clock signal of the first to K-th delay clock signals of the second cycle And an acquisition clock acquisition unit for acquiring the first to Kth acquisition clock signals,
Serial-to-parallel conversion to obtain the K-bit parallel display data by sequentially fetching each bit in the series of serial bits represented by the serial display data signal according to the first to Kth acquisition clock signals And a latch. A phase comparison clock acquisition unit for acquiring the Kth delayed clock signal as a phase comparison clock signal from among the first to Kth delayed clock signals in the second cycle;
A phase comparison unit that detects a phase difference between the input clock signal and the phase comparison clock signal and generates a phase error signal having a level corresponding to the phase difference;
The display driver according to claim 1, wherein the first to Kth delay elements are variable delay elements that adjust the delay time according to the phase error signal. The delay circulation control unit
A clock having a logic level inverted from the first logic level to the second logic level or the second logic level to the first logic level at the timing of the rising or falling edge of the second delay clock signal T-type flip-flops that generate selection signals;
While the clock selection signal is in the first logic level state, the input clock signal is supplied to the first delay element while the clock selection signal is in the second logic level state. 3. The display driver according to claim 1, further comprising: a selector that supplies the signal output from the Kth delay element to the first delay element. The phase comparison clock acquisition unit outputs the signal output from the Kth delay element as the phase comparison clock signal while the clock selection signal is in the first logic level state. Consists of
The acquisition clock acquisition unit
A first AND gate that outputs a signal output from the first delay element during a period in which the clock selection signal is at the first logic level, as the first capture clock signal;
F (f is 2 or more and K are output from odd-numbered delay elements of the second to Kth delay elements while the clock selection signal is in the state of the second logic level And (f + 1) AND gates each outputting a signal of an integer less than 1) as a second to (f + 1) th acquisition clock signal among the first to Kth acquisition clock signals;
The signal output from the second delay element during the period when the clock selection signal is in the state of the second logic level is the (f + 2) th of the first to Kth acquired clock signals. (F + 2) AND gates output as capture clock signals,
While the clock selection signal is in the state of the first logic level, (K−f−2) signals output from even numbered delay elements of the third to Kth delay elements are selected. And (f + 3) th to Kth AND gates output respectively as the (f + 3) th to Kth acquisition clock signals among the first to Kth acquisition clock signals. The display driver according to claim 2 or 3.

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