JP2017067932A - Display driver - Google Patents

Abstract

PURPOSE: To provide a display driver with which it is possible to avoid a state in which currents flowing into a display device concentrate, and to display a high quality image free of luminance unevenness.CONSTITUTION: A display data signal having a series of K-bit serial bits and a single-pulse clock signal are received every prescribed cycle. The received single-pulse clock signal is supplied to a delay circuit, and a delayed clock signal outputted from the delay circuit is circulated to the delay circuit only once, whereby K delayed clock signals are generated. Then, each bit in the serial bit series is successively latched by the K delayed clock signals and the bit series is thereby converted into parallel data.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a display driver that drives a display device in accordance with a video signal.

  For example, in a liquid crystal display panel as a display device, a plurality of gate lines extending in the horizontal direction of the two-dimensional screen and a plurality of source lines extending in the vertical direction of the two-dimensional screen are arranged so as to cross each other. . Display cells corresponding to the pixels are formed at the intersections of the gate lines and the source lines. Furthermore, the liquid crystal display panel is equipped with a source driver that applies a gradation voltage corresponding to the luminance level of each pixel represented by the input video signal to the source line, and a gate driver that applies a scanning signal to the gate line. Has been.

  As a source driver, a display data piece corresponding to each pixel on one gate line is individually taken into a plurality of latches, and a gradation voltage corresponding to the display data piece taken into each latch is applied to the source line. Have been proposed (see, for example, Patent Document 1).

  In the source driver, the display data pieces corresponding to the respective pixels are taken into the respective latches at different timings, thereby avoiding a state in which the current flows intensively and reducing the noise generated with the current concentration. ing. Therefore, such a source driver is provided with a delay circuit group in which delay circuits for delaying a clock signal are connected in cascade in order to load a plurality of display data pieces into each latch at different timings.

JP 2004-301946 A

  By the way, according to the delay circuit group described in Patent Document 1, since the circuit scale increases in proportion to the number of stages of the delay circuits, there is a problem that the device scale of the driver itself increases.

  Therefore, an object of the present invention is to provide a display driver capable of avoiding a state in which current concentrates and flows without causing an increase in device scale.

  The display driver according to the present invention receives a serial display data signal representing a luminance level in a series of serial bits of K (K is an integer of 2 or more) bits and a single pulse input clock signal every predetermined period, A display driver having a serial / parallel converter that converts the received serial display data signal into K-bit parallel display data, each of the serial / parallel converters having a delay time of 1 / (2K) of the predetermined period. A delay circuit having first to K-th delay elements connected in cascade, and the input clock signal supplied to the first delay element to be output from each of the first to K-th delay elements. Are obtained as first to Kth delayed clock signals for the first round, and the Kth delayed clock signal for the first round is supplied to the first delay element. And a delay circulation control unit that obtains a signal output from each of the first to Kth delay elements as the first to Kth delayed clock signals in the second round, and the first to first rounds in the first round. The odd-numbered delayed clock signal of the Kth delayed clock signal and the even-numbered delayed clock signal of the first to Kth delayed clock signals in the second round are represented by the first to Kth. A take-in clock acquisition unit obtained as a take-in clock signal, and sequentially taking each bit in the serial bit series represented by the serial display data signal according to the first to Kth take-in clock signals And a serial-parallel conversion latch for obtaining the K-bit parallel display data.

  In the present invention, first, a display data signal having a K-bit serial bit sequence and a single-pulse clock signal are received at predetermined intervals, and the clock signal is delayed by a delay circuit, thereby being included in the serial bit sequence. K delayed clock signals synchronized with each bit are generated. Here, the serial bits are sequentially converted into parallel data by taking in each bit in the serial bit series in accordance with the K delayed clock signals. As a result, a state in which current concentrates and flows as the value of the display data changes is avoided.

  Furthermore, in the present invention, when generating K delayed clock signals, the received single pulse clock signal is supplied to the delay circuit, and the delayed clock signal output from the delay circuit is supplied only once. Are generated in such a manner that K delayed clock signals are generated.

  Therefore, since the circuit scale of the delay circuit can be reduced, the circuit scale of the entire apparatus can be reduced.

It is a figure which shows schematic structure of the display apparatus 100 containing the display driver which concerns on this invention. It is a time chart which shows an example of the data format of differential display data signal SD1 (P, N)-SD4 (P, N) and differential clock signal CLK (P, N). 3 is a block diagram showing an internal configuration of a serial / parallel conversion unit 200. FIG. 3 is a circuit diagram showing an internal configuration of a DLL section 28. FIG. 3 is a time chart showing an internal operation of a DLL unit 28. It is a circuit diagram which shows the internal structure of SP conversion latch 26a.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration of a display device 100 including a display driver according to the present invention. In FIG. 1, the display device 20 includes, for example, a liquid crystal display panel or an organic EL panel. The display device 20 includes m horizontal scanning lines S _{1 to} S _m (m is a natural number of 2 or more) extending in the horizontal direction of the two-dimensional screen, and n (n is a vertical extension of the two-dimensional screen). (Natural numbers of 2 or more) data lines D _{1 to} D _n are formed. A display cell responsible for red display, a display cell responsible for green display, or a display cell responsible for blue display is formed at the intersection of the horizontal scanning lines and the data lines. One pixel of the display device 20 is formed by one set of the display cell responsible for red display, the display cell responsible for green display, and the display cell responsible for blue display.

  The drive control unit 11 transmits a differential display data signal SD1 (P, N) to SD4 (P, N) and a differential clock signal CLK (each of which is transmitted from a host device (not shown), each in the form of a differential signal. P, N) is received.

  The differential display data signals SD1 (P, N) to SD4 (P, N) and the differential clock signal CLK (P, N) are, for example, FPD-Link (Low Voltage Differential Signaling) transmission employing LVDS (Low Voltage Differential Signaling). It has a data format based on Flat Panel Display Link (registered trademark).

  That is, the host device first assigns each bit of red data, green data, and blue data corresponding to each pixel based on the video signal to the first to fourth groups. For example, red data represents the luminance level of the red component in the video signal by 7 bits, green data represents the luminance level of the green component in the video signal by 7 bits, and blue data represents the blue component of the blue component in the video signal. The brightness level is represented by 7 bits. Next, the host device, for each group, has a positive polarity data signal P including a series of serial bits obtained by concatenating bits assigned to each group, and a negative polarity in which the phase of the data signal P is inverted. The data signal N is generated. Then, the host device displays the data signals P and N corresponding to the first group as the display data signal SD1 (P, N), and the data signals P and N corresponding to the second group as the differential display data signal SD2 (P , N) to the drive control unit 11. Further, the host device outputs the data signals P and N corresponding to the third group to the differential display data signal SD3 (P, N), and the data signals P and N corresponding to the fourth group to the differential display data signal SD4. (P, N) is transmitted to the drive control unit 11.

  Note that at least one of the differential display data signals SD1 (P, N) to SD4 (P, N) includes bits corresponding to the horizontal synchronizing signal and the vertical synchronizing signal, respectively.

  Further, as shown in FIG. 2, the host device has a positive polarity having a pixel transmission cycle TS which is a transmission cycle for one pixel by the differential display data signals SD1 (P, N) to SD4 (P, N). A clock signal P is generated. That is, the host device generates the clock signal P including a single positive polarity pulse every pixel transmission cycle TS. Then, the host device transmits the positive clock signal P and the negative clock signal N obtained by inverting the phase of the clock signal P to the drive control unit 11 as a differential clock signal CLK (P, N). To do. In the example shown in FIG. 2, the duty ratio of the differential clock signal CLK (P, N) is 0.5.

  The drive control unit 11 supplies the horizontal synchronization detection signal to the scan driver 12 when the horizontal synchronization signal is detected from the differential display data signals SD1 (P, N) to SD4 (P, N).

  Further, the drive control unit 11 individually converts the differential display data signals SD1 (P, N) to SD4 (P, N) into a 7-bit parallel form at a timing based on the differential clock signal CLK (P, N). The display data pieces are converted into display data pieces, and display data signals PD1 to PD4 each including a series of display data pieces are supplied to the data driver 13.

The scanning driver 12 sequentially applies a horizontal scanning pulse to each of the horizontal scanning lines S _{1 to} S _m of the display device 20 at a timing synchronized with the horizontal synchronization detection signal supplied from the drive control unit 11.

The data driver 13 takes in the above display data signals PD1 to PD4 and sequentially stores the display data pieces included in these PD1 to PD4. Each time the data driver 13 captures n display data pieces corresponding to one horizontal scanning line, the data driver 13 generates n pixel drive voltages each having a voltage value corresponding to the luminance level represented by the display data pieces. And applied to the data lines D _{1 to} D _n of the display device 20.

  FIG. 3 is a block diagram showing an internal configuration of the serial / parallel conversion unit 200 included in the drive control unit 11. In FIG. 3, differential buffers 21 to 24 generate single display data signals SS1 to SS4, respectively, based on a pair of differential display data signals SD1 (P, N) to SD4 (P, N), respectively. The data is supplied to the data skew adjustment unit 25.

  The data skew adjustment unit 25 generates display data signals S1 to S4 obtained by adjusting the phases of the display data signals SS1 to SS4 so that the phase shift between the display data signals SS1 to SS4 becomes zero, The data is supplied to serial / parallel conversion latches (hereinafter referred to as SP conversion latches) 26a to 26d.

  The differential buffer 27 generates a clock signal CK based on the above-described differential clock signal CLK (P, N), and supplies this to a DLL (Delay-Locked Loop) circuit 28.

  The DLL unit 28 generates a clock signal CPQ having the same frequency as that of the clock signal CK in synchronization with the rising edge portion of the clock signal CK having a single pulse for each pixel transmission period TS, and this is generated as a phase comparison unit 29. To supply. Here, the pulse width of the clock signal CPQ is smaller than [1 / (2 · K)] of the pixel transmission cycle TS. In this case, “K” represents the number of serial bits transmitted in the pixel transmission cycle TS. In the example shown in FIG. 2, the number of serial bits is 7 bits, so K = 7.

  Further, the DLL unit 28 takes a time of [1 / (2 · K)] of the pixel transmission cycle TS as a unit delay time UI, and takes a signal obtained by delaying the clock signal CPQ by the unit delay time UI as a clock signal CP1. Generate.

  Further, the DLL unit 28 takes in a clock signal CP2 obtained by delaying the take-in clock signal CP1 by (2 · UI) period, and takes in a signal obtained by delaying the CP2 by (2 · UI) period. Generated as CP3. Further, the DLL unit 28 generates a clock signal CP4 which is obtained by delaying the CP3 by (2 · UI) period, and a clock signal CP5 which is obtained by delaying the CP4 by (2 · UI) period. To do. Further, the DLL unit 28 generates a signal obtained by delaying the CP5 by the (2 · UI) period, and generates a signal obtained by delaying the CP6 by 1 as a clock signal CP7.

  The DLL unit 28 supplies the capture clock signals CP1 to CP7 to each of the SP conversion latches 26a to 26d.

  Further, the DLL unit 28 supplies a signal obtained by delaying the capture clock signal CP7 by the unit delay time UI to the phase comparison unit 29 as the phase comparison clock signal n7Q.

  The DLL unit 28 adjusts the above-described delay time for delaying the fetch clock signals CP1 to CP7 according to the phase error signal FC supplied from the charge pump unit 30. For example, the DLL unit 28 shortens the delay time when the phase error signal FC is at a high level, and lengthens the delay time when the phase error signal FC is at a high level.

  The phase comparison unit 29 includes a phase comparator 290, a charge pump unit 300, and a capacitor C1. The phase comparator 290 detects the phase difference between the clock signal CPQ and the phase comparison clock signal n7Q, and supplies the phase difference signal ER indicating the phase difference to the charge pump unit 300. The charge pump unit 300 generates a high voltage and applies the line L1 when the phase difference signal ER indicates a delayed phase, while generating a low voltage when the phase difference signal ER indicates a leading phase and generates the line L1. Apply. The other end of the capacitor C1 whose one end is set to the ground potential is connected to the line L1.

  When the phase comparison clock signal n7Q is in a delayed phase with respect to the clock signal CPQ, the phase comparison unit 29 transmits the phase error signal FC having a high level to the DLL unit via the line L1. 28. On the other hand, when the phase comparison clock signal n7Q is advanced and in phase with respect to the clock signal CPQ, the phase comparison unit 29 supplies the phase error signal FC having a low level to the DLL unit 28 via the line L1. To do.

The SP conversion latch 26a sequentially captures and holds each bit in the 7-bit serial bit sequence included in the display data signal S1 in accordance with the capture clock signals CP1 to CP7 for each pixel transmission period TS. Thus, the data is converted into 7-bit parallel display data PQ _1-7 . Then, the SP conversion latch 26a generates a signal composed of a series of display data PQ _1-7 generated every pixel transmission cycle TS as the display data signal PD1.

The SP conversion latch 26b sequentially captures and holds each bit in the 7-bit serial bit sequence included in the display data signal S2 in accordance with the capture clock signals CP1 to CP7 for each pixel transmission cycle TS. Thus, the data is converted into 7-bit display data PQ _1-7 . Then, the SP conversion latch 26b generates a signal composed of a series of display data PQ _1-7 generated every pixel transmission cycle TS as the display data signal PD2.

The SP conversion latch 26c sequentially captures and holds each bit in the 7-bit serial bit sequence included in the display data signal S2 according to the capture clock signals CP1 to CP7 for each pixel transmission cycle TS. Thus, the data is converted into 7-bit display data PQ _1-7 . Then, the SP conversion latch 26c generates a signal composed of a series of display data PQ _1-7 generated every pixel transmission cycle TS as the display data signal PD3.

The SP conversion latch 26d sequentially captures and holds each bit in the 7-bit serial bit sequence included in the display data signal S2 in accordance with the capture clock signals CP1 to CP7 for each pixel transmission period TS. Thus, the data is converted into 7-bit display data PQ _1-7 . Then, the SP conversion latch 26d generates a signal composed of a series of display data PQ _1-7 generated every pixel transmission cycle TS as the display data signal PD4.

  The internal configuration and operation of the DLL unit 28 and the SP conversion latches 26a to 26d will be described below.

  FIG. 4 is a circuit diagram showing an internal configuration of the DLL unit 28, and FIG. 5 is a time chart showing an internal operation of the DLL unit 28.

  In FIG. 4, the edge detection unit EJ generates a clock signal CPQ having the same frequency as that of the clock signal CK in synchronization with the rising edge of the clock signal CK supplied from the differential buffer 27. As shown in FIG. 5, the pulse width W of the clock signal CPQ is smaller than [1 / (4 · K)] of the pixel transmission period TS. In the example shown in FIG. 5, since the number of serial bits transmitted within the pixel transmission period TS is 7 bits, the pulse width W of the clock signal CPQ is smaller than (TS / 28).

  As shown in FIG. 4, the DLL unit 28 includes an edge detection unit EJ, a selector SEL, variable delay elements D1 to D7, a T-type flip-flop TF, AND gates A1 to A7, and AN.

  The edge detection unit EJ supplies the clock signal CPQ to the selector SEL, the reset terminal R of the T-type flip-flop TF, and the phase comparison unit 29.

  The selector SEL selects and selects one of the clock signal CPQ and the delayed clock signal n7 supplied from the variable delay element D7 in accordance with the clock selection signal CS supplied from the T-type flip-flop TF. The clock signal is supplied to the variable delay element D1. For example, when the clock selection signal CS represents the logic level 0, the selector SEL selects the delayed clock signal n7 and supplies it to the variable delay element D1. On the other hand, when the clock selection signal CS represents logic level 1, the selector SEL selects the clock signal CPQ and supplies it to the variable delay element D1.

  The variable delay element D1 includes the variable delay element D2 and the AND gate A1 as a delay clock signal n1 obtained by delaying the delayed clock signal n7 or the clock signal CPQ supplied from the selector SEL by a unit delay time UI as shown in FIG. To supply.

  The variable delay element D2 supplies a signal obtained by delaying the delay clock signal n1 by the unit delay time UI as shown in FIG. 5 to the variable delay element D3, the T-type flip-flop TF, and the AND gate A5 as the delay clock signal n2.

  The variable delay element D3 supplies a signal obtained by delaying the delay clock signal n2 by the unit delay time UI as shown in FIG. 5 to the variable delay element D4 and the AND gate A2 as a delay clock signal n3.

  The variable delay element D4 supplies a signal obtained by delaying the delay clock signal n3 by the unit delay time UI as shown in FIG. 5 to the variable delay element D5 and the AND gate A6 as a delay clock signal n4.

  The variable delay element D5 supplies a signal obtained by delaying the delay clock signal n4 by the unit delay time UI as shown in FIG. 5 to the variable delay element D6 and the AND gate A3 as the delay clock signal n5.

  The variable delay element D6 supplies a signal obtained by delaying the delayed clock signal n5 by the unit delay time UI as shown in FIG. 5 to the variable delay element D7 and the AND gate A7 as the delayed clock signal n6.

  The variable delay element D7 supplies a signal obtained by delaying the delayed clock signal n6 by a unit delay time UI as shown in FIG. 5 to the selector SEL, AND gates A4 and AN as a delayed clock signal n7.

  The variable delay elements D1 to D7 adjust the delay time, that is, the unit delay time UI, which is set based on the phase error signal FC supplied from the phase comparison unit 29. For example, the variable delay elements D1 to D7 are adjusted so as to reduce the delay time as the level represented by the phase error signal FC is higher.

  The T-type flip-flop TF is initialized to a logic level 1 state in accordance with the clock signal CPQ, and thereafter, as shown in FIG. 5, the logic level is set every time a rising or falling edge of the delayed clock signal n2 is detected. A clock selection signal CS to be inverted is generated. The T-type flip-flop TF supplies the clock selection signal CS to the selector SEL, AND gates A1 to A7, and AN.

  As shown in FIG. 5, the AND gate AN supplies the delayed clock signal n7 as the phase comparison clock signal n7Q to the phase comparison unit 29 while the clock selection signal CS is in the logic level 1 state, while the clock selection signal CS is selected. While the signal CS is in the logic level 0 state, the phase comparison clock signal n7Q that maintains the logic level 0 state is supplied to the phase comparison unit 29.

  As shown in FIG. 5, the AND gate A1 supplies the delayed clock signal n1 to the SP conversion latches 26a to 26d as the fetch clock signal CP1 while the clock selection signal CS is in the logic level 1 state. While the clock selection signal CS is in the logic level 0 state, the AND gate A1 supplies the capture clock signal CP1 that maintains the logic level 0 state to the SP conversion latches 26a to 26d.

  As shown in FIG. 5, the AND gate A2 supplies the delayed clock signal n3 to the SP conversion latches 26a to 26d as the take-in clock signal CP2 while the clock selection signal CS is in the logic level 0 state. While the clock selection signal CS is in the logic level 1, the AND gate A2 supplies the capture clock signal CP2 that maintains the logic level 0 state to the SP conversion latches 26a to 26d.

  As shown in FIG. 5, the AND gate A3 supplies the delayed clock signal n5 to the SP conversion latches 26a to 26d as the take-in clock signal CP3 while the clock selection signal CS is in the logic level 0 state. While the clock selection signal CS is in the logic level 1, the AND gate A3 supplies the capture clock signal CP3 that maintains the logic level 0 state to the SP conversion latches 26a to 26d.

  As shown in FIG. 5, the AND gate A4 supplies the delayed clock signal n7 to the SP conversion latches 26a to 26d as the fetch clock signal CP4 while the clock selection signal CS is in the logic level 0 state. While the clock selection signal CS is in the logic level 1, the AND gate A4 supplies the capture clock signal CP4 that maintains the logic level 0 state to the SP conversion latches 26a to 26d.

  As shown in FIG. 5, the AND gate A5 supplies the delayed clock signal n2 to the SP conversion latches 26a to 26d as the fetch clock signal CP5 while the clock selection signal CS is in the logic level 0 state. While the clock selection signal CS is in the logic level 1, the AND gate A5 supplies the capture clock signal CP5 that maintains the logic level 0 state to the SP conversion latches 26a to 26d.

  As shown in FIG. 5, the AND gate A6 supplies the delayed clock signal n4 to the SP conversion latches 26a to 26d as the fetch clock signal CP6 while the clock selection signal CS is in the logic level 1 state. While the clock selection signal CS is in the logic level 0 state, the AND gate A6 supplies the capture clock signal CP6 that maintains the logic level 0 state to the SP conversion latches 26a to 26d.

  As shown in FIG. 5, the AND gate A7 supplies the delayed clock signal n6 to the SP conversion latches 26a to 26d as the fetch clock signal CP7 while the clock selection signal CS is in the logic level 1 state. While the clock selection signal CS is in the logic level 0 state, the AND gate A7 supplies the capture clock signal CP7 that maintains the logic level 0 state to the SP conversion latches 26a to 26d.

  The operations of the DLL unit 28 and the phase comparison unit 29 will be described below with reference to FIG.

  First, the T-type flip-flop TF generates a logic level 1 clock selection signal CS according to the clock signal CPQ. In response to the clock selection signal CS, the selector SEL supplies the clock signal CPQ to the variable delay element D1. As a result, the variable delay elements D1 to D7 sequentially output the first to seventh delayed clock signals n1 to n7 in the first cycle, as shown in FIG. During this time, in response to the second delayed clock signal n2, the T-type flip-flop TF changes the clock selection signal CS from the logic level 1 state to the logic level 0 state as shown in FIG. Therefore, the selector SEL supplies the seventh delay clock signal n7 in the first round to the variable delay element D1. As a result, the variable delay elements D1 to D7 sequentially output the first to seventh delayed clock signals n1 to n7 in the second round as shown in FIG. During this time, in response to the second delayed clock signal n2, the T-type flip-flop TF changes the clock selection signal CS from the logic level 0 state to the logic level 1 state as shown in FIG.

  Here, the AND gates A1 to A7 as the acquisition clock acquisition units perform the following operations.

  The AND gate A1 outputs the delayed clock signal n1 output from the variable delay element D1 during the period in which the clock selection signal is in the logic level 1 as the first capture clock signal CP1. The AND gates A2 to A4 receive the odd-numbered variable delay elements D3, D5, and D7 from the second to seventh variable delay elements D2 to D7 during the period when the clock selection signal CS is in the logic level 0 state. The output three delayed clock signals n3, n5, n7 are output as second to fourth acquisition clock signals CP2 to CP4, respectively. The AND gate A5 outputs the delayed clock signal n2 output from the second variable delay element D2 during the period when the clock selection signal CS is in the logic level 0 state as the fifth capture clock signal CP5. . The AND gates A6 to A7 output from the even-numbered variable delay elements D4 and D6 among the third to seventh variable delay elements D3 to D7 during the period in which the clock selection signal CS is in the logic level 1 state. The two delayed clock signals n4 and n6 are output as sixth and seventh acquisition clock signals CP6 and CP7.

  The AND gate AN as the phase comparison clock acquisition unit is a signal output from the seventh variable delay element D7 during the period when the clock selection signal CS is in the logic level 1, that is, the delay of the second round. The clock signal n7 is output as the phase comparison clock signal n7Q. At this time, the phase comparison unit 29 detects the phase difference between the clock signal CPQ as the input clock signal and the phase comparison clock signal n7Q, and generates a phase error signal FC having a level corresponding to this phase difference. Therefore, the variable delay elements D1 to D7 adjust their delay times according to the phase error signal FC.

  The above-described DLL section 28 and phase comparison section 29 allow the first to first serial bit sequences of the display data signals S1 to S4 within each pixel transfer period TS regardless of manufacturing variations or environmental temperature variations. Capture clock signals CP1 to CP7 in which rising edge portions appear at intermediate timings of the seventh bits are generated. The DLL unit 28 supplies the fetch clock signals CP1 to CP7 to each of the SP conversion latches 26a to 26d.

  The SP conversion latches 26a to 26d have the same internal configuration. Therefore, the operation of the SP conversion latch will be described below by extracting 26a from the SP conversion latches 26a to 26d.

  FIG. 6 is a circuit diagram showing the internal configuration of the SP conversion latch 26a. As shown in FIG. 6, the SP conversion latch 26a has D latches FL1 to FL7 in which the display data signal S1 is supplied to each D terminal.

The clock signal CP1 is supplied to the clock terminal of the D latch FL1. The D latch FL1 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP1 shown in FIG. Thus, D latch FL1, as shown in FIG. 5, takes in the first bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as display data PQ _1.

The clock signal CP2 is supplied to the clock terminal of the D latch FL2. The D latch FL2 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP2 shown in FIG. Thus, D latch FL2, as shown in FIG. 5, it takes in the second bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as display data PQ _2.

The clock signal CP3 is supplied to the clock terminal of the D latch FL3. The D latch FL3 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP3 shown in FIG. Thus, D latch FL3, as illustrated in FIG. 5, takes in the third bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as display data PQ _3.

The clock signal CP4 is supplied to the clock terminal of the D latch FL4. The D latch FL4 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP4 shown in FIG. Thus, D latch FL4, as shown in FIG. 5, takes in the fourth bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as the display data PQ _4.

The clock signal CP5 is supplied to the clock terminal of the D latch FL5. The D latch FL5 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP5 shown in FIG. Thus, D latch FL5, as shown in FIG. 5, takes in the fifth bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as display data PQ _5.

The clock signal CP6 is supplied to the clock terminal of the D latch FL6. The D latch FL6 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP6 shown in FIG. Thus, D latch FL6, as shown in FIG. 5, it takes in the sixth bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as display data PQ _6.

The clock signal CP7 is supplied to the clock terminal of the D latch FL7. The D latch FL7 captures and holds the display data signal S1 at the timing of the rising edge of the capture clock signal CP7 shown in FIG. Thus, D latch FL7, as shown in FIG. 5, takes in the seventh bit in the first to seventh bit sequence represented by the display data signal S1, and outputs it as display data PQ _7.

Therefore, the SP conversion latch 26a first fetches the first bit from the first to seventh bits in the serial form included in the display data signal S1 into the D latch FL1, and stores the first bit in the FIG. As shown in FIG. 5, the data is output as display data PQ ₁ representing the first bit in the display data signal PD1. Next, SP conversion latch 26a is the second bit is input to the D latch FL2, the second bit, and outputs the display data PQ ₂ representing the second bit of the display data signal PD1. That is, at this point, SP conversion latch 26a outputs the display data PQ _1-2 representing the first and second bit of the display data signal PD1 as shown in FIG. 5 at the same time. Next, SP conversion latch 26a is the third bit is input to the D latch FL3, the third bit, and outputs the display data PQ ₃ showing a third bit of the display data signal PD1. That is, at this time, the SP conversion latch 26a simultaneously outputs the display data PQ _1-3 representing the first to third bits in the display data signal PD1, as shown in FIG.

Thereafter, similarly, the SP conversion latch 26a sequentially takes the fourth to seventh bits into the D latches FL4 to FL7, and takes the fourth to seventh bits as the fourth to seventh bits in the display data signal PD1. Display data PQ ₄ , PQ ₅ , PQ ₆ , and PQ ₇ are sequentially output.

That is, within each pixel transmission period TS, when the D latch FL7 fetches the final seventh bit in the display data signal S1, the SP conversion latch 26a converts the first to seventh bits in the serial form into a 7-bit parallel. The display data PQ _1-7 converted into is output.

As described above, in the SP conversion latch 26a (26b to 26d) and the DLL unit 28, the first to seventh bits are converted bit by bit when converting the serial bit sequence into the parallel display data PQ _1-7. The output is distributed over time. Therefore, it is possible to avoid the current flowing along with the change of the display data from being concentrated on the temporary point.

  Here, the DLL unit 28 uses the selector SEL, the variable delay elements D1 to D7, the T-type flip-flop TF, and the AND gates A1 to A7 and AN to compare the captured clock signals CP1 to CP7 and the phase comparison based on the clock signal CPQ. The clock signal n7Q is generated.

  That is, a signal obtained by delaying the clock signal CPQ by the unit delay time UI is generated as an acquisition clock signal CP1 for acquiring the first bit in the serial bit sequence, and the acquisition clock signal CP1 is only 2 · UI. The delayed signal is generated as a capture clock signal CP2 for capturing the second bit in the serial bit sequence.

  Further, the DLL unit 28 generates a signal obtained by delaying the capture clock signal CP2 by 2 · UI as a capture clock signal CP3 for capturing the third bit in the serial bit sequence. A signal obtained by delaying the signal CP3 by 2 · UI is generated as a capture clock signal CP4 for capturing the fourth bit in the serial bit sequence. Further, the DLL unit 28 generates a signal obtained by delaying the capture clock signal CP4 by 2 · UI as the capture clock signal CP5 for capturing the fifth bit in the serial bit series, and the capture clock signal A signal obtained by delaying CP5 by 2 · UI is generated as a capture clock signal CP6 for capturing the sixth bit in the serial bit sequence. Further, the DLL unit 28 generates a signal obtained by delaying the capture clock signal CP6 by 2 · UI as the capture clock signal CP7 for capturing the seventh bit in the serial bit series.

  Further, in the DLL unit 28, a signal obtained by delaying the clock signal CPQ by the same period as that of the pixel transmission cycle TS, that is, 14 · UI, in order to correct the phase error generated in the captured clock signals CP1 to CP7, This is obtained as a phase comparison clock signal n7Q that is a phase comparison target with the clock signal CPQ.

  Therefore, originally, in order to obtain the capture clock signals CP1 to CP7 and the phase comparison clock signal n7Q from the clock signal CPQ, a delay circuit that delays the clock signal CPQ for the same period (14 · UI) as the pixel transmission cycle TS. Necessary. At this time, the circuit scale of the delay circuit becomes larger as the signal delay time becomes longer.

  On the other hand, the delay time in the delay circuit (D1 to D7) used in the DLL unit 28 is a half of the pixel transmission cycle TS, that is, 7 · UI. Therefore, the circuit scale of the delay circuit is approximately ½ compared to the case where a delay circuit that delays the clock signal CPQ by 14 · UI, which is actually the same period as the pixel transmission cycle TS, is employed. The DLL unit 28 includes T-type flip-flops TF, AND gates A1 to A7 and AN in addition to the delay circuits (D1 to D7). These T-type flip-flops TF and AND gates A1 to A7 are included. And the circuit scale of AN is generally smaller than the circuit scale of the variable delay elements D1 to D7.

  Therefore, if the DLL unit 28 having the configuration shown in FIG. 4 is employed, the scale of the entire apparatus can be reduced.

  In the above-described embodiment, the serial / parallel conversion unit 200 shown in FIG. 3 is included in the drive control unit 11, but the serial / parallel conversion unit 200 may be provided in the data driver 13.

  In the serial / parallel conversion unit 200 shown in FIG. 3, the number of bits to be converted into serial / parallel is 7 bits, but the number of bits is not limited to 7 bits.

  In short, the display driver according to the present invention includes a serial display data signal (S1 to S4) representing a luminance level as a serial bit sequence of K (K is an integer of 2 or more) bits, and a single pulse input clock signal ( CPQ) is received every predetermined period (TS), and any serial parallel conversion unit (200) that converts the serial display data signal into K-bit parallel display data (PD1 to PD14) may be used. .

  The serial / parallel conversion unit may include any of the following delay circuits, a delay / circulation control unit, an acquisition clock acquisition unit, and a serial / parallel conversion latch.

  That is, the delay circuit includes first to Kth delay elements (D1 to D7) each having a delay time of 1 / (2K) of a predetermined period. The delay cycle control unit (SEL, TF) supplies the input clock signal to the first delay element (D1), and thereby outputs the signal output from each of the first to Kth delay elements in the first cycle. Obtained as 1st to Kth delayed clock signals (n1 to n7). Further, the delay cycle control unit supplies the first delay element to the first delay element by supplying the first delay element with the Kth delay clock signal (n7) in the first period. Obtained as the first to Kth delayed clock signals (n1 to n7) in the second round. The acquisition clock acquisition unit (A1 to A7, TF) includes an odd-numbered delayed clock signal (n1, n3, n5, n7) of the first to Kth delayed clock signals in the first round, and a second The even-numbered delayed clock signals (n2, n4, n6) of the first to Kth delayed clock signals in the cycle are obtained as the first to Kth fetch clock signals (CP1 to CP7). The serial / parallel conversion latches (26a to 26d, FL1 to FL7) respond to the first to Kth fetch clock signals for each bit in the serial bit series represented by the serial display data signals (S1 to S4). The display data of K-bit parallel is obtained by sequentially taking in.

11 Drive control unit 26a to 26d SP conversion latch 28 DLL unit 29 Phase comparison unit A1 to A7, AN AND gate D1 to D7 Variable delay element EJ Edge detection unit SEL Selector TF T type flip-flop

Claims (4)

A serial display data signal representing a luminance level as a serial bit sequence of K bits (K is an integer of 2 or more) and a single pulse input clock signal are received at predetermined intervals, and the received serial display data signal is received. A display driver having a serial-parallel conversion unit for converting to K-bit parallel display data,
The serial-parallel converter is
A delay circuit in which first to Kth delay elements each having a delay time of 1 / (2K) of the predetermined period are cascaded;
By supplying the input clock signal to the first delay element, a signal output from each of the first to Kth delay elements is obtained as the first to Kth delay clock signals in the first round. By supplying the first delay element with the K-th delayed clock signal of the first round, the signals output from each of the first to K-th delay elements are supplied to the first to first rounds of the second round. A delay circulation control unit obtained as a Kth delayed clock signal;
The odd-numbered delayed clock signal of the first to Kth delayed clock signals in the first round and the even-numbered delayed clock signal of the first to Kth delayed clock signals in the second round. And an acquisition clock acquisition unit for obtaining the first to Kth acquisition clock signals,
Serial-parallel conversion for obtaining the K-bit parallel display data by sequentially acquiring each bit in the serial bit series represented by the serial display data signal according to the first to K-th acquisition clock signals A display driver comprising: a latch; A phase comparison clock acquisition unit that acquires the Kth delayed clock signal as a phase comparison clock signal from the first to Kth delayed clock signals in the second round;
A phase comparison unit that detects a phase difference between the input clock signal and the phase comparison clock signal and generates a phase error signal having a level corresponding to the phase difference;
The display driver according to claim 1, wherein the first to Kth delay elements are variable delay elements that adjust the delay time according to the phase error signal. The delay circulation control unit includes:
A clock having a logic level that is inverted from the first logic level to the second logic level or from the second logic level to the first logic level at the timing of the rising or falling edge of the second delayed clock signal. A T-type flip-flop for generating a selection signal;
While the clock selection signal is in the first logic level state, the input clock signal is supplied to the first delay element, while the clock selection signal is in the second logic level state. The display driver according to claim 1, further comprising: a selector that supplies a signal output from the Kth delay element to the first delay element. The phase comparison clock acquisition unit outputs, as the phase comparison clock signal, a signal output from the Kth delay element during a period when the clock selection signal is in the state of the first logic level. Consists of
The capture clock acquisition unit
A first AND gate that outputs a signal output from the first delay element during the period in which the clock selection signal is in the first logic level as the first capture clock signal;
During the period when the clock selection signal is in the state of the second logic level, f outputs from the odd-numbered delay elements among the second to Kth delay elements (f is 2 or more and K A second (f + 1) -th AND gate that outputs a second (f + 1) -th acquisition clock signal among the first to K-th acquisition clock signals,
The signal output from the second delay element during the period in which the clock selection signal is in the second logic level is the (f + 2) th of the first to Kth acquisition clock signals. A (f + 2) th AND gate that outputs as a capture clock signal;
(K−f−2) signals output from the even-numbered delay elements among the third to Kth delay elements during the period in which the clock selection signal is in the first logic level state. And (f + 3) to (k + 3) th to Kth AND gates that respectively output as the (f + 3) to Kth acquisition clock signals among the first to Kth acquisition clock signals. The display driver according to claim 2 or 3.

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