JP2012151628A - Phase adjustment device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase adjustment device capable of automatically performing phase adjustment without performing visual determination with a projection image when performing the phase adjustment between digital image data and a clock.SOLUTION: A data selector 104 selects the delay clock of one kind of delay time corresponding to an n-bit counter value to be supplied to a select terminal among multiple delay clocks which are supplied from a delay circuit 101 in parallel and mutually different in delay time by prescribed time. A latch circuit 105 latches digital data by the rising and falling of the delay clock that has been output from the data selector 104. A four-stage shift register 106 performs the four-shifting of the digital data from the latch circuit 105 with the delay clock that is output from the data selector 104 as a shift clock. A comparator 107 compares the input digital data of the four-shift register 106 with the output digital data, and determines correctness in latching when coincidence is obtained in a comparison result.

Description

  The present invention relates to a phase adjustment device, and more particularly to a phase adjustment device that automatically adjusts the relative phase of data and clock when data and clock are input to a liquid crystal display device in an initial state after power-on.

  In recent years, a liquid crystal on silicon (LCOS) type liquid crystal display device is often used as a central part for projecting an image in a projector device or a projection television. In the display method of the liquid crystal display device such as LCOS, an analog video signal is conventionally input to a semiconductor element such as a CMOS (Complementary Metal Oxide Semiconductor), and the signal is held as it is on the pixel electrode of the liquid crystal display element for each pixel. A method of changing the orientation of the liquid crystal, a method of applying a video signal that has been subjected to pulse width modulation (PWM) by a digital signal to the pixel electrode of the liquid crystal display element, and driving by switching the orientation of the liquid crystal over time. there were. Among them, the method of directly applying an analog signal to the pixel electrode has a problem that liquid crystal burn-in easily occurs.

  In order to solve the problem, the present applicant firstly intersects each of a plurality of data lines each including two data lines (column signal lines) and a plurality of gate lines (row scanning lines). Each pixel is disposed in a portion, and in each of the pixels, a positive video signal and a negative video signal are separately sampled and held in two holding capacitors, and then the holding voltage is alternately applied to the pixel electrode to liquid crystal A liquid crystal display device in which the display element is AC driven has been proposed (see, for example, Patent Document 1).

  FIG. 6 shows a schematic block diagram of an example of the liquid crystal display device. As shown in the figure, the liquid crystal display device 200 includes a horizontal drive circuit 203 including a data latch 201, a shift register and comparator 202, a video switch, and the like, a plurality of pixels 204 regularly arranged in a two-dimensional matrix, and a vertical drive. Circuits 205 and 206 are included.

  The data latch 201 latches digital image data (Data) to be displayed by a bit with a horizontal clock (hCK) of 1H cycle, generates b-bit digital image data and a shift clock, and sends them to the shift register and comparator 202. Supply. The shift register in the shift register and comparator 202 develops one line of digital image data input from the data latch 201, temporarily holds it, and supplies it in parallel to the comparator in the shift register and comparator 202. A total of n comparators in the shift register and comparator 202 are provided for each column corresponding to n (n is an integer of 2 or more) data lines (column signal lines). The shift register and comparator 202 is for a comparator that is obtained by counting a counter / comparator clock (hereinafter also referred to as a clock CK) and that changes stepwise from a minimum value to a maximum value within a horizontal scanning period. While the counter output (reference gradation data) is supplied to n comparators in common, the image data held by the shift register is supplied for each pixel of one line, and the two are compared. Then, the coincidence pulse is supplied to the horizontal drive circuit 203.

  The horizontal driving circuit 203 has a video switch connected to each data line (column signal line), and outputs a coincidence pulse when a coincidence pulse is supplied from the shift register and the comparator for each column in the comparator 202. The video switch provided corresponding to the comparator is turned off. Each video switch is commonly supplied with a periodic ramp signal whose level indicating gradation changes monotonously in synchronization with the reference gradation data. A value (that is, an analog value obtained by D / A converting input image data) is sampled on a data line.

  In the pixel 204, n sets of data lines (column signal lines) are provided at intersections between D1 to Dn and m gate lines (row scanning lines) G1 to Gm. The signal voltage sampled and input from the video switch through the data line is held in the holding capacitor and then applied to the pixel electrode of the liquid crystal display element. The liquid crystal display element has a known configuration in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode provided to face each other.

  In this liquid crystal display device 200, the voltage applied to the pixel electrode can be held in two holding capacitors for one frame period, so that the AC drive frequency of the liquid crystal display element does not depend on the vertical scanning frequency, but the pixel circuit It can be set freely with the inversion control cycle at. As a result, according to the liquid crystal display device 200, the AC drive frequency can be set extremely higher than the vertical scanning frequency, thereby preventing burn-in compared to the conventional case, and reducing the display quality such as reliability, stability, and stains. In addition, it is possible to obtain features such as that gradation can be correctly expressed by the digital PWM method.

JP 2009-223289 A

  In the liquid crystal display device 200, as shown in FIG. 6, a clock hCK for temporarily latching digital image data supplied from the outside by the data latch 201 is required, and a data latch error occurs depending on the latch timing. In particular, when the digital image data is data having a large number of pixels, such as full high-definition (FHD), the data rate is high, and thus the phase adjustment between the clock and the digital image data is essential. However, it is possible to suppress an increase in data rate to some extent by inputting in parallel.

  However, when the data rate is high, the liquid crystal display device 200 has the following problems.

  The first problem is that the liquid crystal display device 200 is composed of CMOS semiconductor elements, and the number of terminals is limited. The second problem is that it is difficult to increase the data rate from the viewpoint of power consumption. However, when displaying a full high-definition image at a quadruple speed, a 10-bit digital image data input is converted into a serial-parallel format. In the case of bit data, even if sampling is performed at both the rising and falling edges of the clock, a high frequency clock of 150 MHz is required.

  The third problem is that the period of the 20-bit digital image data is 3 ns, and the phase with the sampling edge of the clock needs to be suppressed within several ns. The fourth problem is that the phase of the digital image data and the clock can be adjusted with a resolution of 200 ps by using a phase locked loop (PLL) circuit or the like in an external drive circuit. Means that it is necessary to adjust each chip. However, this digital image data and clock phase adjustment is performed while looking at the image displayed by the adjuster using the finest data etc., but it is possible to confirm whether or not a data sampling error has occurred. It is difficult and may be complicated as a production process.

  The present invention has been made in view of the above points, and provides a phase adjustment device that can automatically adjust without adjusting visual judgment using a projection image when adjusting the phase of digital image data and a clock. Objective.

  In order to achieve the above object, the phase adjustment apparatus of the present invention latches digital image data with a latch clock and supplies the digital image data as display digital image data to the display device, and is the same as the latch clock. A delay clock that delays a first clock of a frequency by a predetermined time unit, and sequentially switches a plurality of delay clocks having different delay times for each predetermined period larger than the period of the first clock and outputs the delayed clock serially. Generating means, second latch means for latching digital data for phase adjustment for each delay clock having a different delay time outputted from the delay clock generating means, and a latch obtained by latching by the second latch means The digital data for later phase adjustment is shifted for a predetermined period by the delay clock used at the time of latching. A comparison unit that generates the data and compares the digital data for phase adjustment before the shift with the digital data after the shift for all of the plurality of delay clocks, and a comparison in which the two digital data match by the comparison unit And an output means for supplying the delayed clock when the result is obtained as a latch clock to the first latch means.

  In order to achieve the above object, in the phase adjustment apparatus of the present invention, the output means compares the digital data for phase adjustment before the shift with the digital data after the shift for all of the plurality of delay clocks by the comparison means. Among the comparison results obtained by holding the holding means for holding the delay time of the minimum value and the delay time of the maximum value in the delay time range of the delay clock indicating that the comparison results match, and the minimum held by the holding means And an averaging means for calculating an average value of the delay time of the value and the delay time of the maximum value and supplying the delay clock of the delay time of the average value to the first latch means as a latch clock. To do.

  According to the present invention, it is possible to automatically adjust the optimum phase of the clock for latching the digital image data without making a visual judgment, so that the number of adjustment steps can be eliminated and a margin can be easily secured.

It is a circuit system diagram of one embodiment of a phase adjustment device of the present invention. FIG. 2 is a circuit diagram of an embodiment of a minimum value holding circuit in FIG. 1. FIG. 2 is a circuit diagram of an embodiment of a maximum value holding circuit in FIG. 1. 2 is a timing chart for explaining the operation of FIG. 1. FIG. 2 is a diagram schematically illustrating an example of a relationship between a delay time of a delay clock output from a delay circuit in FIG. 1 and a comparison result of a comparator. It is a schematic block diagram of an example of the liquid crystal display device previously disclosed by the present applicant.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a circuit diagram of an embodiment of a phase adjusting device according to the present invention. As shown in the figure, the phase adjustment apparatus 100 according to the present embodiment counts a delay circuit 101 that receives a clock (CK) from the outside via a terminal CK and generates a plurality of delay clocks, and a counter CK. The n-bit counter 102, the changeover switch 103 for selecting one of the delay setting value or the counter value of the n-bit counter 102, and the data for selecting the delay clock from the delay circuit 101 according to the value selected by the changeover switch 103 A selector 104, a latch circuit 105 that latches, for example, 10-bit digital data input from the outside through the terminal Data, a four-stage shift register 106, a comparator 107, a latch circuit 108, and a minimum value holding circuit 109 The maximum value holding circuit 110 and the averaging circuit 111 for outputting the delay setting value It is configured.

  The delay circuit 101 is composed of an inverter chain in which a plurality of inverters are connected in cascade. The delay circuit 101 delays an input CK and outputs a plurality of delays CK different from each other in delay time units of the inverters to the data selector 104 in parallel. The repetition frequency of the input CK is the same repetition frequency as the latch clock hCK supplied to the data latch 201 of the liquid crystal display device 200 shown in FIG. The change-over switch 103 selects the n-bit count value from the counter 102 and outputs it to the data selector 104 in the initial state. When the n-bit delay setting value is output from the averaging circuit 111, the delay setting is set. A value is selected and output to the data selector 104.

  The data selector 104 receives the n-bit value selected by the selector switch 103 as a select signal, and delays a delay time corresponding to the value of the n-bit select signal among the plurality of delays CK supplied from the delay circuit 101. CK is selected and output serially, and is output to the latch circuit 105, the four-stage shift register 106, the minimum value holding circuit 109, and the maximum value holding circuit 110. Further, the data selector 104 supplies the delay clock after the delay setting to the data latch 201 of the liquid crystal display device 200 shown in FIG. 6 as a latch clock hCK. The data latch 201 constitutes a first latch means of the present invention that latches digital image data with a latch clock hCK and outputs it as display digital image data.

  The latch circuit 105 is configured by a D-type flip-flop (DFF), and 10-bit digital data (Data) supplied to the data input terminal D of the delay CK supplied from the data selector 104 to the clock terminal. Latching is performed at both rising and falling edges, and the latched digital data is output from the Q output terminal. The latch circuit 105 constitutes second latch means of the present invention.

  The four-stage shift register 106 shifts the digital data output after being latched by the latch circuit 105 in synchronization with both rising and falling edges of the delay clock supplied from the data selector 104. The comparator 107 compares the digital data delayed by four cycles of the delayed clock from the data selector 104 by the four-stage shift register 106 with the digital data latched by the latch circuit 105, and the comparison result is sent to the latch circuit 108. Output. The four-stage shift register 106 and the comparator 107 constitute the comparison means of the present invention.

  The latch circuit 108 is constituted by a DFF, and latches the counter value supplied from the counter 102 to the data input terminal D through the change-over switch 103 when the comparison result from the comparator 107 supplied to the clock terminal shows a match. Then, the latched n-bit counter value is supplied to the minimum value holding circuit 109 and the maximum value holding circuit 110.

  The averaging circuit 111 averages the minimum value held by the minimum value holding circuit 109 and the maximum value held by the maximum value holding circuit 110 after all the delayed clocks have been sequentially output from the data selector 104. The averaged n-bit value is output as a delay setting value. The latch circuit 108, the minimum value holding circuit 109, the maximum value holding circuit 110, and the averaging circuit 111 constitute the output means of the present invention. When the delay setting value is input, the changeover switch 103 is switched to select it.

  FIG. 2 shows a circuit diagram of an embodiment of the minimum value holding circuit 109 in FIG. As shown in the figure, the minimum value holding circuit 109 includes a DFF 1091, a subtraction circuit 1092, and a data selector (D / S) 1093. The subtraction circuit 1092 subtracts the n-bit input value (B) input this time from the n-bit value (A) output last time obtained by latching by the DFF 1091, and when the subtraction value is positive (that is, When the input value B is smaller than the previous output value A, a borrow signal having a logical value of “1” is output from the Borrow terminal, and otherwise (that is, the input value B is greater than or equal to the previous output value A). ), A borrow signal having a logical value of “0” is output from the Borrow terminal. The n-bit input value (B) is the delay time of the delay clock output from the data selector 104.

  When the borrow signal has a logical value “1”, the data selector 1093 selects and outputs the input value supplied to the terminal 1 and supplies it to the DFF 1091 for latching, so that the borrow signal has a logical value “0”. At this time, the previous output value from the DFF 1091 supplied to the terminal 0 is selected and output and supplied to the DFF 1091 to be latched. Therefore, the data selector 1093 outputs an input value smaller than the past output value, that is, a minimum value.

  FIG. 3 shows a circuit diagram of an embodiment of the maximum value holding circuit 110 in FIG. As shown in the figure, the maximum value holding circuit 110 includes a DFF 1101, a subtraction circuit 1102, and a data selector (D / S) 1103. The subtraction circuit 1102 subtracts the n-bit input value (B) input this time from the n-bit value (A) output last time obtained by latching by the DFF 1101, and when the subtraction value is negative (that is, When the input value B is larger than the previous output value A), a carry signal having a logical value of “1” is output from the carry terminal, and otherwise (that is, the input value B is equal to or lower than the previous output value A). ), A carry signal having a logical value of “0” is output from the carry terminal. The input value (B) is a delay time of the delay clock output from the data selector 104.

  When the carry signal has a logical value “1”, the data selector 1103 selects and outputs the input value supplied to the terminal 1 and supplies it to the DFF 1101 for latching, so that the carry signal has a logical value “0”. At this time, the previous output value from the DFF 1101 supplied to the terminal 0 is selected and output and supplied to the DFF 1101 to be latched. Therefore, the data selector 1103 outputs an input value larger than the past output value, that is, the maximum value.

  Next, the operation of FIG. 1 will be described with reference to the timing chart of FIG. After power-on, digital data (Data) shown in FIG. 4 (A) is input from the outside to the data input terminal D of the latch circuit 105, and the first clock (CK) shown in FIG. 4 (B) is a delay circuit. The counter CK that is the second clock shown in FIG. 4D is input to the n-bit counter 102. The input digital data is reference data in which the same signal as the data input to the pixel 204 is prepared for phase adjustment.

  The delay circuit 101 receives a first CK shown in FIG. 4B from the outside via a terminal CK, generates a plurality of delay clocks having different delay times in units of inverter delay times, and outputs data in parallel. This is supplied to the selector 104. On the other hand, the n-bit counter 102 counts the counter CK shown in FIG. 4D, which is the second clock, and generates an n-bit count value shown in FIG. 4C. The first CK and the second CK are synchronized with each other, and the cycle of the second CK is set to twice the cycle of the first CK.

  Since the changeover switch 103 is connected to select the n-bit count value from the n-bit counter 102 from the initial state until a later-described delay setting value is determined, the count value is transmitted through the changeover switch 103 to the data selector. 104 is supplied to the select terminal. The data selector 104 selects a delay clock having one delay time corresponding to the n-bit counter value supplied to the select terminal from the plurality of delay clocks supplied in parallel from the delay circuit 101, and latches it. The clock is supplied to the clock terminal of the circuit 105, the clock terminal of the four-stage shift register 106, the clock terminal of the minimum value holding circuit 109, and the clock terminal of the maximum value holding circuit 110, respectively.

  The latch circuit 105 latches the digital data shown in FIG. 4A at the rising and falling edges of the delay clock output from the data selector 104, and outputs the digital data shown in FIG. The four-stage shift register 106 shifts the digital data output after being latched by the latch circuit 105 by four stages using the delay clock output from the data selector 104 as a shift clock. As a result, the output of the first stage of the four-stage shift register 106 is shown in FIG. 4F, the output of the second stage is shown in FIG. 4G, the output of the third stage is shown in FIG. The output is as shown in FIG.

  The comparator 107 compares the digital data output from the fourth stage of the four-stage shift register 106 and delayed by two cycles of the delay clock with the digital data supplied to the four-stage shift register 106. Here, the 4-stage shifted digital data output from the fourth stage of the four-stage shift register 106 is the delay set in the data selector 104 by the n-bit counter 102 as shown in FIGS. This is the data before the time delay clock is switched to the delay clock of the next delay time. Therefore, the comparator 107 compares the digital data before and after the shift, which is the latch result of one delay clock, so that if the comparison results match, it can be determined that the latch is correct and the comparison is completed. If the results do not match, it can be determined that the latch is not correct. Therefore, the above operation is repeated for all of the plurality of delay clocks output from the delay circuit 101, and the comparison result of the comparator 107 obtained thereby is obtained, so that the correct data can be obtained from which phase (delay time) of the plurality of delay clocks. You will know if you are reading. FIG. 4J shows the comparison result output from the comparator 107. When the comparison result matches, a high level is output, and when the comparison result does not match, a pulse is generated.

  The latch circuit 108 latches the n-bit counter value from the n-bit counter 102 by the coincidence signal that is output when the comparison result coincides with the comparator 107, and outputs it to the minimum value holding circuit 109 and the maximum value holding circuit 110, respectively. To do.

  Subsequently, the n-bit counter value from the n-bit counter 102 is switched to the next value, and the data selector 104 selects and outputs a delay clock of the next one type of delay time accordingly. Thereafter, the same operation as described above is performed.

  In this manner, the data selector 104 sequentially outputs a delay clock whose delay time is switched in a predetermined time unit (one cycle unit of the counter CK in the example of FIG. 3), and latches corresponding to the delay clock. The latch operation of the digital image data by the circuit 105 and the shift operation by the four-stage shift register 106 are performed each time, and the comparator 107 compares the data before and after the shift corresponding to the delay clock. When the results match, the latch operation of the latch circuit 108 is performed.

  The minimum value holding circuit 109 and the maximum value holding circuit 110 hold the minimum value and the maximum value, respectively, of the n-bit counter values that are latched by the latch circuit 108 and sequentially input, and output them to the averaging circuit 111. To do. The minimum value and the maximum value of the n-bit counter values latched by the latch circuit 108 and sequentially input indicate the minimum value and the maximum value of the delay time range of the delay clock indicating that the comparison results match. The averaging circuit 111 averages the minimum value and the maximum value of the n-bit counter values held by the minimum value holding circuit 109 and the maximum value holding circuit 110 and outputs the result as a delay setting value.

  Next, the basic concept of how to set the phase will be described.

  FIG. 5 schematically shows an example of the relationship between the delay time of the delay clock output from the delay circuit 101 and the comparison result of the comparator 107. In the example of FIG. 3, the data selector 104 outputs a delay clock that changes in units of delay time “1” from the delay clock with the shortest delay time “0” to the delay clock with the longest delay time “15”. At this time, it is indicated by ◯ that a coincidence comparison result is obtained from the comparator 107 from the delay clock with the delay time “3” to the delay clock with the delay time “13”.

  In this case, the minimum value holding circuit 109 holds the value “3” when the delay clock with the delay time “3” is output from the data selector 104, and the maximum value holding circuit 110 receives the delay time “13” from the data selector 104. The value “13” when the delayed clock is output is held. Therefore, after the delay clocks of all delay times are output from the data selector 104, the averaging circuit 111, the holding value “3” of the minimum value holding circuit 109 and the holding value “3 of the maximum value holding circuit 110”. The average value “8” obtained by dividing the sum of 13 ”by 2 is calculated as the delay setting value, and the automatic adjustment is terminated.

  Thereby, thereafter, the changeover switch 103 always supplies the delay set value “8” to the select terminal of the data selector 104 and causes the data selector 104 to output the delay clock of the delay time “8” from the data selector 104 in a fixed manner. . Since this delay setting value “8” is the average value of the minimum and maximum delay times determined to be correctly latched, the delay time of the delay clock that has been adjusted in phase with the most margin in phase. Indicates. Note that the data selector 104 supplies a delay clock having a delay time “8” to the data latch 201 shown in FIG. 6 as a latch clock hCK. Thereafter, the liquid crystal display device 200 performs a normal operation.

  As described above, according to the present embodiment, after the power is turned on, the reference digital data is input from the outside, and the digital data is latched by the delay clock having the set delay time, and the obtained digital data is latched. Comparing two digital data consisting of digital data and the shifted digital data obtained by shifting it with the same delay clock by the comparator 107, it is latched correctly when they are the same data to decide. According to the present embodiment, the phase of the latch clock that can be correctly latched by repeating while switching the delay time of the delay clock in a predetermined time unit (that is, while switching the clock phase in a predetermined phase unit). By obtaining the range, it is possible to automatically adjust the optimum phase of the clock for latching the digital image data without performing visual judgment, so that adjustment man-hours can be eliminated and a margin can be easily secured.

DESCRIPTION OF SYMBOLS 100 Phase adjustment apparatus 101 Delay circuit 102 n bit counter 103 Changeover switch 104 Data selector 105, 108 Latch circuit 106 Four stage shift register 107 Comparator 109 Minimum value holding circuit 110 Maximum value holding circuit 111 Averaging circuit 200 Liquid crystal display device 201 Data latch 204 pixels

Claims (2)

First latch means for latching digital image data with a latch clock and supplying the digital image data as display digital image data to a display device;
A first clock having the same frequency as the latch clock is delayed by a predetermined time unit, and a plurality of delayed clocks having different delay times are sequentially switched every predetermined period longer than the cycle of the first clock. Delay clock generating means for serially outputting,
Second latch means for latching digital data for phase adjustment for each of the delay clocks having different delay times that are switched and output from the delay clock generation means;
The phase-adjusted digital data obtained by latching by the second latch means is shifted for the predetermined period by the delay clock used at the time of latching to generate the shifted digital data. Comparing means for comparing the previous digital data for phase adjustment and the digital data after the shift for all of the plurality of delay clocks;
An output means for supplying a delay clock when the comparison means obtains a comparison result that matches the two digital data to the first latch means as the latch clock. . The output means includes
Of the comparison results obtained by comparing the digital data for phase adjustment before the shift and the digital data after the shift for all of the plurality of delay clocks by the comparison means, the delay whose comparison result indicates coincidence Holding means for holding the minimum delay time and the maximum delay time of the clock delay time range;
An average value of the delay time of the minimum value and the delay time of the maximum value held by the holding means is calculated, and a delay clock of the delay time of the average value is used as the latch clock in the first latch means. The phase adjusting apparatus according to claim 1, further comprising: an averaging unit that supplies the phase adjusting unit.

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