JP5509579B2 - VIDEO OUTPUT DEVICE, VIDEO OUTPUT METHOD, AND PROJECTOR - Google Patents

Description

  The present invention relates to a video output technique for outputting a video signal to a display device that is driven by dividing one screen into a plurality of channels.

  In an active matrix liquid crystal display, pixels arranged in a horizontal direction and a vertical direction are selected by scanning, and an image signal input from the outside is applied to an electrode (pixel electrode) constituting the selected pixel. Writing is performed. The video signal writing time is difficult to shorten because the voltage of the pixel electrode with respect to the counter electrode is substantially the same as the voltage of the video signal. Therefore, when the number of pixels in the horizontal direction and the vertical direction increases, it takes time to scan the pixel electrodes, and the display update frequency cannot be increased. Therefore, in an active matrix liquid crystal display, for example, a pixel is divided into a plurality of channels in the horizontal direction, and writing is performed almost simultaneously on the plurality of channels.

  Thus, when writing to a plurality of channels, if the output level of the output circuit supplying the video signal is different for each channel, a difference occurs in the voltage of the video signal written to the same input. Display unevenness is generated with different gradations. Therefore, in order to suppress the occurrence of display unevenness, the output circuit provided for each channel can be level-adjusted, and the output when a reference signal is input to each output circuit is compared with reference data prepared in advance. It has been proposed to correct the level adjustment amount of the corresponding output circuit in accordance with the comparison result (for example, Patent Document 1).

Japanese Patent Laid-Open No. 5-150751

  However, in order to realize such a level adjustment method, a high-speed analog / digital (A / D) converter is used for the output from each output circuit in order to obtain data for comparison with reference data. There is a need. In the high-speed A / D converter, when the resolution (number of bits) is increased, the circuit scale rapidly increases. Therefore, in order to correct the level adjustment amount with sufficient accuracy to sufficiently suppress display unevenness, there is a problem that the configuration of the entire video output apparatus becomes complicated. On the other hand, if an A / D converter with a small circuit scale is used to simplify the configuration of the video output device, the time required for A / D conversion increases and the time required for level adjustment increases. The problem is that the optical state of each pixel is determined in accordance with the level of the video signal, and the display device is driven by a plurality of channels. This is a problem common to organic EL displays and plasma displays.

  The present invention has been made to solve the above-described conventional problems, and an object of the present invention is to sufficiently and quickly suppress display unevenness with an apparatus having a simpler configuration.

  In order to solve at least a part of the above problems, the present invention can be realized as the following forms or application examples.

[Application Example 1]
A video output device that outputs a video signal to a display device that is driven by dividing one screen into a plurality of channels,
A plurality of level adjustment units provided for each of the plurality of channels, for adjusting a level of a video signal input for each channel and outputting the level to the display device;
In a non-display period in which the video signal is not output to the display device, a reference signal input unit that inputs a first reference signal to each of the level adjustment units;
Each of the reference signals output from the level adjustment unit when the first reference signal is input is compared with a second reference signal corresponding to the first reference signal, and the reference signal is the first reference signal. An adjustment amount correction unit that increases or decreases each adjustment amount of the level adjustment unit so as to be adjusted toward the reference signal of 2;
Increase / decrease amount that makes the increase / decrease amount of the adjustment amount in the second period after the first period smaller than the increase / decrease amount of the adjustment amount in the first period in the period in which the adjustment amount is corrected. A video output device comprising a reduction unit.

  According to this application example, the control signal is adjusted toward the second reference signal by increasing or decreasing the adjustment amount of the level adjusting unit based on the comparison result between the control signal and the second reference signal. Therefore, the adjustment amount can be corrected with a simpler configuration. In the first period, the adjustment amount is corrected by a large increase / decrease amount, and in the second period, the adjustment amount is corrected by a small increase / decrease amount. Therefore, the correction of the adjustment amount can be performed more quickly and the correction accuracy of the adjustment amount can be further increased. As a result, display unevenness can be sufficiently and quickly suppressed.

[Application Example 2]
A video output device according to Application Example 1,
The first period is a period until the reference signal reaches the second reference signal, and the second period is a period after the arrival.

  The adjustment amount is corrected by a large increase / decrease amount before the reference signal reaches the second reference signal, and the adjustment amount is corrected by a small increase / decrease amount after the reference signal reaches the second reference signal. Therefore, the first period in which the adjustment amount is corrected with a large increase / decrease amount can be further shortened. For this reason, it is possible to correct the adjustment amount with high accuracy more quickly.

[Application Example 3]
A video output device according to Application Example 2,
The adjustment amount correction unit includes a signal comparator that compares each of the reference signals with the second reference signal and determines a magnitude relationship between the reference signal and the second reference signal.
The increase / decrease reduction unit determines that the reference signal has reached the second reference signal when the magnitude relationship between the reference signal and the second reference signal determined by the signal comparator is inverted. A video output device that reduces the increase / decrease amount.

  According to this application example, it is possible to determine whether or not the reference signal has reached the second reference signal by using the signal comparator included in the adjustment amount correction unit. This makes it easier to determine whether the control signal has reached the second reference signal. Further, by sharing the signal comparator, the configuration of the video output device can be further simplified.

[Application Example 4]
The video output device according to any one of Application Examples 1 to 3,
The increase / decrease amount is an integral multiple of the minimum correction amount that can be corrected as the adjustment amount,
The increase / decrease amount reduction unit reduces the increase / decrease amount by reducing a magnification with respect to the minimum correction amount.

  According to this application example, since the increase / decrease amount can be reduced digitally, the increase / decrease amount can be reduced more easily.

[Application Example 5]
A video output device according to Application Example 4,
The adjustment amount correction unit supplies a number of pulses corresponding to the magnification to the level adjustment unit,
The level adjustment unit increases or decreases the adjustment amount by the minimum correction amount for each input of the pulse.

  According to this application example, since the increase / decrease amount of the adjustment amount is determined by the number of pulses, the increase / decrease amount can be reduced more easily.

[Application Example 6]
A video output device according to Application Example 5,
The said increase / decrease amount reduction part reduces the said increase / decrease amount by making the said magnification 1/2 time before the said reach | attainment.

  According to this application example, since the number of pulses can be changed more easily, the magnification can be changed more easily and the amount of increase / decrease can be reduced more easily.

[Application Example 7]
The video output device according to any one of Application Examples 1 to 6,
Each of the level adjustment units
It has a digital / analog converter that converts a digital signal that is a video input signal into an analog signal,
The adjustment amount correction unit adjusts the level of the video signal by adjusting at least one of a gain and an offset in the digital / analog converter.

  According to this application example, a dedicated level adjustment amount correction circuit provided separately can be omitted, and the configuration of the video output apparatus can be further simplified.

[Application Example 8]
The video output device according to any one of Application Examples 1 to 7,
The non-display period includes a preparation period before display start in the liquid crystal display device,
Increase / decrease of the adjustment amount by the adjustment amount correction unit is executed a plurality of times during the preparation period.

  According to this application example, the adjustment amount can be increased or decreased in the preparation period before the display start in the liquid crystal display device. Therefore, the level adjustment amount can be corrected without affecting the display image displayed on the liquid crystal display device. Further, display irregularity at the start of display can be sufficiently suppressed by increasing or decreasing the adjustment amount a plurality of times during the preparation period.

[Application Example 9]
The video output device according to any one of Application Examples 1 to 8,
The non-display period includes a vertical blanking period.

  According to this application example, the adjustment amount can be increased or decreased during the vertical blanking period. Therefore, the level adjustment amount can be corrected without affecting the display image displayed on the liquid crystal display device.

  The present invention can be realized in various modes. For example, a video output device and a video output method, a control device and a control method for a video output device, and a projector and a display device using these devices and methods And a television program, a video output device, a control device, a projector, a display device, a computer program for realizing the functions of the television device, a recording medium on which the computer program is recorded, and the computer program including the computer program are embodied in a carrier wave. It can be realized in the form of a data signal.

A1. LCD display configuration:
FIG. 1 is a circuit diagram showing a configuration of a liquid crystal display 100 to which a video output device according to an embodiment of the present invention is connected. The liquid crystal display 100 employs an active matrix driving method. As shown in FIG. 1, the liquid crystal display 100 includes a liquid crystal panel 110 that displays an image, a scanning line driving circuit 120 that drives the liquid crystal panel 110, and a signal line driving circuit 130 that also drives the liquid crystal panel 110. With.

  The liquid crystal panel 110 includes an array substrate (not shown). The array substrate has a plurality of scanning lines 112 extending in the X direction (hereinafter also referred to as “horizontal direction”) and a plurality of signal lines 114 extending in the Y direction (hereinafter also referred to as “vertical direction”) in a matrix. A pixel electrode (pixel pattern) 116 made of a transparent electrode and a thin film transistor (TFT) 118 as a switching element are formed at the intersection. The gate electrode of the TFT 118 is connected to the scanning line 112, the source electrode is connected to the signal line 114, and the drain electrode is connected to the pixel electrode 116. Thus, an active matrix portion including the scanning line 112, the signal line 114, the pixel electrode 116, and the TFT 118 is formed on the substrate.

  In this embodiment, as shown in FIG. 1, a MOS type FET is used as the switching element (that is, TFT 118). However, various switching elements such as bipolar transistors can be used as the switching element. It is. The liquid crystal display 100 employs an active matrix driving method, but may employ other driving methods such as a simple matrix driving method.

  Although not shown, the liquid crystal panel 110 further includes a counter substrate in which a counter electrode facing the array substrate having the above structure is formed, and holds a liquid crystal material between the array substrate and the counter substrate via an alignment film. doing.

  The scanning line driving circuit 120 includes a Y direction scanning circuit 122. The Y direction scanning circuit 122 is connected to each scanning line 112 included in the liquid crystal panel 110. The Y-direction scanning circuit 122 receives the vertical start signal S8 and the vertical clock signal S9 sent from the outside of the liquid crystal display 100, and moves the active matrix portion in the vertical direction based on the vertical start signal S8 and the vertical clock signal S9. By sequentially scanning, the scanning lines 112 are sequentially selected.

  The signal line driving circuit 130 is connected to each signal line 114 included in the liquid crystal panel 110. The signal line driving circuit 130 includes an X-direction scanning circuit 140, an enable control unit 150, and a precharge driving circuit 160.

  The X-direction scanning circuit 140 receives a horizontal start signal S6 and a horizontal clock signal S7 sent from the outside of the liquid crystal display 100, and moves the active matrix portion in the horizontal direction based on the horizontal start signal S6 and the horizontal clock signal S7. By sequentially scanning the signal lines 114, the signal lines 114 are sequentially selected.

  The enable control unit 150 includes n (n is a plurality of positive numbers) AND circuits 151, 152,..., 15n, a first input terminal T1 of each AND circuit 151 to 15n, and an X-direction scanning circuit. The n output terminals Q1, Q2, and Qn included in 140 are connected to each other. The second input terminals T2 of the AND circuits 151 to 15n are connected to one line and connected to an enable signal terminal ENBX which is one of connection terminals of the liquid crystal display 100. The output terminals T3 of the AND circuits 151 to 15n are connected to an OR circuit (described later) of the precharge drive circuit 160.

  The precharge driving circuit 160 includes n OR circuits 161, 162,..., 16n arranged side by side, and the first input terminal T4 of each of the OR circuits 161 to 16n is connected to the output terminal T3 of the AND circuits 151 to 15n. Are connected to each other. The second input terminal T5 of each of the OR circuits 161 to 16n is connected to one line and is connected to a precharge timing signal terminal PreCHG which is one of connection terminals of the liquid crystal display 100.

  The output terminals T36 of the OR circuits 161 to 16n are branched into three lines, and the same TFT 170 as the switching element formed in the liquid crystal panel 110 is connected to each branch destination. Specifically, it is connected to the gate electrode of the TFT 170. The TFT 170 is referred to as a “scanning TFT” in order to distinguish it from the TFT 118 formed on the liquid crystal panel 110. The TFT 118 formed on the liquid crystal panel 110 is referred to as a “pixel TFT”.

  The drain electrode of the scanning TFT 170 is connected to each signal line 114 included in the liquid crystal panel 110. That is, the scanning TFTs 170 have the same number as the signal lines 114. Therefore, since the number of scanning TFTs 170 is 3 × n, the number of signal lines 114 is also 3 × n. In other words, n is 1/3 of the number of signal lines. That is, n is 1/3 of the number of signal lines in order to drive the liquid crystal panel 110 by dividing it into three in the horizontal direction.

  Each scanning TFT 170 can be divided into a first channel scanning TFT, a second channel scanning TFT, and a third channel scanning TFT for each group connected to the same OR circuits 161 to 16n. Each of the scanning TFTs for the same channel of the group is connected to one line, and each line of each group is connected to the analog video terminals VID1, VID2, and VID3 of the liquid crystal display 100.

  According to the liquid crystal display 100 having the above configuration, the scanning line 112 is selected by the Y-direction scanning circuit 1202 and the signal line 114 is selected by the X-direction scanning circuit 140, whereby the analog video terminal VID1 is connected to the desired pixel TFT 118. , VID2 and VID3 can be transmitted. As a result, in the liquid crystal display 100, only the liquid crystal in the region sandwiched between the pixel electrode corresponding to the pixel TFT 118 and the counter electrode changes its arrangement in response to the electric field between the electrodes, and the liquid crystal shutter for each pixel. Function as. Furthermore, according to the liquid crystal display 100, by receiving the horizontal write enable signal S4 from the enable signal terminal ENBX, the output signals from the output terminals Q1, Q2, and Qn of the X direction scanning circuit 140 can be validated. . Further, by receiving the precharge timing signal S5 from the precharge timing signal terminal PreCHG, a precharge voltage can be applied to each signal line 114 in the precharge period determined from the precharge timing signal S5.

A2. Configuration of video output device:
FIG. 2 is a circuit diagram showing a configuration of the video output device 10 to which the liquid crystal display 100 is connected. FIG. 3 is a block diagram illustrating a schematic configuration of the adjustment control unit 600 included in the video output device 10. The adjustment control unit 600 includes an adjustment mode signal generation unit 610, a channel switching signal generation unit 620, a correction signal generation unit 630, a correction amount determination unit 640, a polarity inversion detection unit 650, and two reference signal generation units 660. , 670.

  The adjustment control unit 600 is configured as a microcomputer including a CPU, a memory, and an input / output port (all not shown). The functions of the function units 610, 620, 630, 640, 650, 660, and 670 of the adjustment control unit 600 are realized by the CPU executing a program stored in the memory. However, the adjustment control unit 600 may be realized by hardware. Hereinafter, when the CPU of the adjustment control unit 600 executes a process in order to realize the function of a certain function unit, the function unit executes the process. The functions of the adjustment control unit 600 and each functional unit will be described later.

  The video output device 10 shown in FIG. 2 supplies a 3-channel video signal to the liquid crystal display 100. Specifically, the 3-channel video signal generators 200, 300, and 400 generate 3-channel analog video signals S1 to S3 from 3-channel digital video signals V1 to V3 output from a video processing circuit (not shown). The generated analog video signals S1 to S3 are output to the analog video terminals VID1 to VID3 of the liquid crystal display 100, respectively.

  The three-channel digital video signals V1 to V3 are converted into analog signals by the D / A converters 210, 310, and 410, respectively. Each of the D / A converters 210, 310, and 410 has current output type digital / analog converters (D / A converters) 212, 312, and 412. Note that two reference voltages for determining an output current value corresponding to the digital signal are supplied to the D / A converters 212, 312, and 412. Hereinafter, among these reference voltages, the reference voltage on the high voltage side is referred to as the “upper limit reference voltage”, and the reference voltage on the low voltage side is referred to as the “lower limit reference voltage”.

  Current signals output from the D / A converters 212, 312, and 412 are current-voltage converters (IV converters) 220 and 320 including operational amplifiers 222, 322, 422 and resistors 224, 324, 424, respectively. , 420 are converted into voltage signals. The analog video signals S1 to S3 converted into voltage signals are output to the analog video terminals VID1 to VID3 of the liquid crystal display 100. In the IV converters 220, 320, and 420, the ratio of the output voltage value to the input current value (IV conversion gain) is determined by the resistors 224, 324, and 424. Therefore, these resistors 224, 324, and 424 are identical in terms of standards.

  Each of the D / A converters 210, 310, and 410 includes gain adjusters 214, 314, and 414 that adjust gains (amplification factors) of the D / A converters 212, 312, and 412, and D / A converters 212, And offset adjustment units 216, 316, and 416 that adjust the offsets of 312 and 412. As described above, the levels of the analog video signals S1 to S3 output from the video signal generation units 200, 300, and 400 are adjusted by adjusting the gains and offsets of the D / A converters 212, 312, and 412. Therefore, hereinafter, the gain and the offset are also referred to as “adjustment amount”. Further, since the video signal generation units 200, 300, and 400 have a function of adjusting the level of the output signal, they can also be referred to as “level adjustment units”, respectively.

  In this embodiment, the gain adjusting units 214, 314, 414 and the offset adjusting units 216, 316, 416 are configured by an up / down counter and an R-2R type D / A converter. Then, the gain adjustment units 214, 314, and 414 adjust the gain by changing the upper limit reference voltages supplied to the corresponding D / A converters 212, 312, and 412, respectively. The offset adjustment units 216, 316, and 416 adjust the offset by changing the lower limit reference voltages supplied to the corresponding D / A converters 212, 312, and 412, respectively. Therefore, the gain and the offset are corrected by an amount corresponding to the number of input pulses, as will be described later. Note that the configurations of the gain adjustment units 214, 314, and 414 and the offset adjustment units 216, 316, and 416 are different as long as the gain and offset of the D / A converters 212, 312, and 412 can be changed. It is also possible. Depending on the configuration of the gain adjusting units 214, 314, 414 and the offset adjusting units 216, 316, 416, the gain, offset, input signal voltage, and pulse width can be set directly. In this case, the correction amount between the gain and the offset can be set to a value other than an integer multiple of the predetermined minimum correction amount. However, the configuration of the gain adjusting units 214, 314, 414 and the offset adjusting units 216, 316, 416 is further simplified, and correction is performed with an amount corresponding to the number of pulses in that the correction amount can be easily changed. Is more preferable. Thus, the correction amount can be changed digitally by setting the correction amount to an integral multiple of the minimum correction amount.

  Input changeover switches 510, 520, and 530 are provided in front of the D / A conversion units 210, 310, and 410. The input change-over switches 510, 520, and 530 receive the adjustment amount correction mode signal Cal supplied from the adjustment mode signal generation unit 610 (FIG. 3) of the adjustment control unit 600, and input to each D / A conversion unit 210, 310, and 410. Switch the signal to send. When the adjustment amount correction mode signal Cal is at the low level (image display mode), the input changeover switches 510, 520, and 530 supply the digital video signals V1 to V3 to the D / A conversion units 210, 310, and 410, respectively. On the other hand, when the adjustment amount correction mode signal Cal is at a high level (adjustment amount correction mode), the input changeover switches 510, 520, 530 are the first reference signal generated by the first reference signal generation unit 660 of the adjustment control unit 600. The signal Vref1 is supplied to each D / A converter 210, 310, 410.

  The outputs of the IV converters 220, 320, and 420 are connected to the output changeover switch 604. The output changeover switch 604 corresponds to the three channel designation signals CH1 to CH3 supplied from the channel switching signal generation unit 620 (FIG. 3) of the adjustment control unit 600 and one analog video signal from the analog video signals S1 to S3. Select Sx. For example, when the channel designation signal CH1 becomes high level, the first analog video signal S1 is selected. The analog video signal Sx selected by the output changeover switch 604 is supplied to a voltage comparator (comparator) 602.

  The voltage comparator 602 is supplied with the analog video signal Sx selected by the output changeover switch 604 and the second reference signal Vref2 generated by the second reference signal generator 670 of the adjustment controller 600. The voltage comparator 602 compares the voltage levels of the analog video signal Sx and the second reference signal Vref2, and outputs a comparison output signal Vcomp. The comparison output signal Vcomp output from the voltage comparator 602 is supplied to the polarity inversion detection unit 650 (FIG. 3) and the correction signal generation unit 630 of the adjustment control unit 600. The correction signal generation unit 630 stores the comparison output signal Vcomp in a storage unit (not shown), and adjusts the comparison output signal Vcomp stored in the storage unit in synchronization with each falling edge of the channel designation signals CH1 to CH3. Output as UP / DOWN. Note that the analog video signal Sx is a signal to be compared with the second reference signal Vref, and thus can also be referred to as a “reference signal”.

  In general, a liquid crystal display may be deteriorated such as image sticking by continuously applying a DC voltage. Therefore, in this embodiment, in order to suppress the deterioration of the liquid crystal display, the video signal generation units 200, 300, and 400 alternately switch the polarities of the analog video signals S1 to S3 at the falling timing of the vertical synchronization signal Vsync. . In accordance with this, the second reference signal generator 670 switches the polarity of the second reference signal Vref2. The voltage comparator 602 determines the output level of the comparison output signal Vcomp in accordance with such polarity switching. For example, when a general comparator is used as the voltage comparator 602, the comparison output signal Vcomp is obtained by inverting the output of the comparator during a period in which the polarities of the analog video signals S1 to S3 and the second reference signal Vref2 are inverted. Is generated.

  The gain adjustment units 214, 314, and 414 correct the gains of the D / A converters 212, 312, and 412 based on the timing signals TG 1 to TG 3 and the adjustment information UP / DOWN supplied from the adjustment control unit 600. Specifically, the gain correction direction is determined from the adjustment information UP / DOWN, and the gains of the D / A converters 212, 312, and 412 are corrected at timings corresponding to the timing signals TG1 to TG3. For example, when the voltages of the analog video signals S1 to S3 are higher than the voltage of the reference signal Vref2, the correction direction is determined to decrease, and the gain is decreased by one step at the rising edge of the timing signals TG1 to TG3. On the other hand, when the voltages of the analog video signals S1 to S3 are lower than the voltage of the reference signal Vref2, the correction direction is determined to be an increasing direction, and the gain is increased by one step at the rising edge of the timing signals TG1 to TG3. Therefore, the analog video signals S1 to S3 are adjusted toward the reference signal Vref2 at the rise of the timing signals TG1 to TG3. In the following, a period in which the channel 1 timing signal TG1 is output, that is, a period in which the channel designation signal CH2 designating the next channel (channel 2) of the channel 1 is at a high level is referred to as “channel 1 gain”. It is also called “correction period”, and the other channels are called in the same way.

  The offset adjustment units 216, 316, and 416 correct the offsets of the D / A converters 212, 312, and 412 based on the timing signals TO1 to TO3 and the adjustment information UP / DOWN supplied from the adjustment control unit 600. Specifically, the offset correction direction is determined from the adjustment information UP / DOWN, and the offsets of the D / A converters 212, 312, and 412 are corrected at timings corresponding to the timing signals TO1 to TO3. For example, when the voltages of the analog video signals S1 to S3 are higher than the voltage of the reference signal Vref2, the correction direction is determined to decrease, and the offset is decreased by one step at the rising edge of the timing signals TO1 to TO3. On the other hand, when the voltages of the analog video signals S1 to S3 are lower than the voltage of the reference signal Vref2, the correction direction is determined to increase and the offset is increased by one step at the rising edge of the timing signals TO1 to TO3. Accordingly, the analog video signals S1 to S3 are adjusted toward the reference signal Vref2 at the rise of the timing signals TO1 to TO3. In the following, a period in which the timing signal TO1 of the channel 1 is output, that is, a period in which the channel designation signal CH2 designating the next channel (channel 2) of the channel 1 is at a high level is referred to as “channel 1 offset. It is also called “correction period”, and the other channels are called in the same way.

  As described above, when the gain adjustment units 214, 314, 414 and the offset adjustment units 216, 316, 416 are configured by the up / down counter and the D / A converter, the adjustment information UP / DOWN is raised and lowered by the up / down counter. By supplying the timing signals TG1 to TG3 and TO1 to TO3 to the clock input of the up / down counter by supplying them to the control input, the functions of these gain adjusting unit and offset adjusting unit can be realized.

  The adjustment control unit 600 includes gain adjustment units 214, 314, 414, offset adjustment units 216, 316, 416 based on the comparison output signal Vcomp supplied from the voltage comparator 602 and the clock signal CLK supplied from the outside. To control. As described above, the resistors 224, 324, and 424 used in the IV converters 220, 320, and 420 are the same in the standard, but their resistance values differ depending on individual differences and the ambient temperature. There is a possibility. The operational amplifiers 222, 322, and 422 used in the IV converters 220, 320, and 420 also have zero offset (output voltage when the two inputs + and-are at the same potential) due to individual differences and ambient temperature. May be different. Therefore, the IV conversion gain and offset of the IV converters 220, 320, and 420 may be different for each channel. Therefore, the adjustment control unit 600 controls the gain adjustment units 214, 314, 414 and the offset adjustment units 216, 316, 416, thereby reducing the influence of the difference in IV conversion gain and offset for each channel.

  Specifically, the polarity inversion detection unit 650 (FIG. 3) inverts the magnitude relationship between the analog video signal Sx and the second reference signal Vref2 from the comparison output signal Vcomp supplied from the voltage comparator 602 (polarity inversion). And the detection result is supplied to the correction amount determination unit 640 (FIG. 3). The correction amount determination unit 640 determines a correction amount (that is, an increase / decrease amount of the adjustment amount) based on the detection result of polarity inversion. The correction signal generation unit 630 (FIG. 3) outputs, as the timing signals TG1 to TG3 and TO1 to TO3, pulse signals corresponding to the correction amounts determined by the correction amount determination unit 640, the gain adjustment units 214, 314, 414, and the offset. The data is sent to the adjustment units 216, 316, and 416. The determination of the correction amount by the correction amount determination unit 640 and the generation of the timing signals TG1 to TG3 by the correction signal generation unit 630 will be described later. As will be described later, the correction amount determination unit 640 reduces the correction amount based on the detection result of polarity reversal, and thus can also be referred to as a “correction amount reduction unit”. In the present embodiment, the polarity inversion detection unit 650 detects the polarity inversion from the comparison output signal Vcomp supplied from the voltage comparator 602. However, the analog video signal Sx and the second video signal from the separate voltage comparator are detected. The determination result of the magnitude relationship with the reference signal Vref2 may be acquired.

  In this way, by correcting the gain and offset, the voltages of the analog video signals S1 to S3 are substantially matched with the voltage of the reference signal Vref2. Therefore, when the same input signal is input to the video signal generators 200, 300, and 400, the voltages of the analog video signals S1 to S3 are substantially equal, and unevenness caused by the difference in the voltages of the analog video signals S1 to S3 occurs. Occurrence can be suppressed.

  The video output device 10 also includes a reset generation circuit 800. The reset generation circuit 800 outputs a reset signal Reset to the microcomputer constituting the adjustment control unit 600 in response to the input of the power supply voltage Vdd. In the present embodiment, the reset generation circuit 800 is provided in the video output device 10, but the reset signal Reset may be supplied from the outside if the reset signal Reset can be supplied to the adjustment control unit 600. Good.

  The video output device 10 also includes a display timing generation unit 900. The display timing generation unit 900 generates a horizontal write enable signal S4, a precharge timing signal S5, a horizontal start signal S6, a horizontal clock signal S7, a vertical start signal based on the clock signal CLK, the vertical synchronization signal Vsync, and the horizontal synchronization signal Hsync. S8, a vertical clock signal S9 is generated. Then, the generated signals S4 to S9 are output to predetermined terminals ENBX, PreCHG, DX, CLX, DY, and CLY of the liquid crystal display 100.

A3. Adjustment amount correction processing:
FIG. 4 is a flowchart showing an adjustment amount correction process executed by the adjustment control unit 600 (FIG. 3). In the adjustment amount correction process of this embodiment, the correction amount is changed separately for each adjustment amount. FIG. 5 is a flowchart showing a correction execution process for changing the correction amount for each adjustment amount. FIG. 6 is a timing chart showing how the adjustment amount is corrected in this embodiment.

  In step S <b> 110 of FIG. 4, the adjustment control unit 600 determines whether the reset state has been released based on the reset signal Reset supplied from the reset generation circuit 800. When it is determined that the reset state is not released, step S110 is repeatedly executed until the reset state is released. On the other hand, when it is determined that the reset state is released, the process proceeds to step S120, and the adjustment amount is corrected. As will be described later, the adjustment amount is corrected by repeating the correction of all the adjustment amounts (the gains and offsets of the three channels) a plurality of times. Hereinafter, a series of processing periods in which all adjustment amounts are corrected is also referred to as a correction cycle.

  In step S120, the adjustment control unit 600 sets the adjustment amount correction mode signal Cal output from the adjustment mode signal generation unit 610 to high level, and sets the video output device 10 to the adjustment amount correction mode.

  In step S600, the correction amount determination unit 640 of the adjustment control unit 600 initializes the correction amount. Specifically, initial values (for example, 4 steps) of correction amounts are set for the respective adjustment amounts (the gains and offsets of the three channels). The initial value of the correction amount is stored in a storage unit (not shown) provided in the correction amount determination unit 640.

  Next, in step S610, the first reference signal generator 660 outputs black reference data as the first reference signal Vref1, and the second reference signal generator 670 outputs the black reference voltage as the second reference signal Vref2. Is output. When the first reference signal generator 660 outputs black reference data, the black reference data is input to the D / A converters 212, 312, and 412 via the input changeover switches 510, 520, and 530. In the example of FIG. 6, at time t21 when the reset signal Reset becomes high level (reset release), the adjustment amount correction mode signal Cal is switched from low level to high level (step S120), and the D / A converters 212, 312, 412 are switched. Input signals VC1 to VC3 are black reference data (step S610).

  In step S620, the adjustment control unit 600 corrects the offset of the channel 1. Specifically, the correction execution process shown in FIG. 5 is executed.

  In step S710 of FIG. 5, the polarity inversion detection unit 650 determines whether the polarity of the offset of the channel 1 has been inverted. If polarity inversion is detected, the process proceeds to step S720. On the other hand, if polarity inversion is not detected, the process proceeds to step S730. In any channel, in the first offset correction immediately after the initialization of the correction amount (step S600), the determination in step S710 is not performed, and the process proceeds to step S730.

  In step S720, correction amount determination unit 640 reduces the correction amount of the offset of channel 1. For example, when the correction amount is 4 steps, the correction amount is reduced to 2 steps, and when the correction amount is 2 steps, the correction amount is reduced to 1 step. When the correction amount is 1 step, the correction amount is reduced to 0 step. After the offset correction amount is reduced in step S720, the process proceeds to step S730.

  In step S730, it is determined whether or not the correction amount is 0 step. If the correction amount is 0 steps, the correction execution process is terminated, and the process returns to the adjustment amount correction process of FIG. On the other hand, if the correction amount is not 0 step, that is, if the correction amount is 1 step or more, the process proceeds to step S740.

  In step S740, the correction signal generator 630 outputs the timing signal TO1 according to the offset correction amount of the channel 1. Specifically, as shown in FIG. 6, the channel switching signal generator 620 outputs the analog video signal S1 of channel 1 by the output selector switch 604 at the rising timing of the waveform of the channel designation signal CH1 corresponding to channel 1. select. The voltage comparator 602 outputs a comparison output signal Vcomp based on the analog signal S1 of the channel 1 and the reference signal Vref2. The correction amount determination unit 640 reduces the correction amount based on the output of the polarity inversion detection unit 650. The correction signal generation unit 630 stores the comparison output signal Vcomp as adjustment information UP / DOWN in a storage unit (not shown), and generates a timing signal TO1 based on the correction amount determined by the correction amount determination unit 640. The correction signal generator 630 outputs the timing signal TO1 and the adjustment information UP / DOWN at the falling timing of the channel designation signal CH1. The offset adjustment unit 216 corrects the offset of the channel 1 so that the voltage of the analog video signal S1 approaches the black reference voltage based on the timing signal TO1 output from the adjustment control unit and the adjustment information UP / DOWN. Thus, the correction execution process shown in FIG. 5 is completed, and the control is returned to the adjustment amount correction process of FIG.

  In the example of FIG. 6, the adjustment information UP / DOWN is at a high level indicating that the voltage of the analog video signal S1 is higher than the black reference voltage in the correction cycle tc1. For this reason, the offset adjustment unit 216 of the channel 1 lowers the offset by 4 steps. On the other hand, when the voltage of the analog video signal S1 is lower than the black reference voltage and the adjustment information UP / DOWN is at a low level, the offset is increased by 4 steps.

  Also, the polarity inversion detection unit 650 detects the polarity inversion of the offset of the channel 1. Specifically, the polarity inversion detection unit 650 is a period during which the black reference signal is input to the D / A converters 212, 312, and 412 and the channel designation signal CH1 is at a high level (hereinafter referred to as “channel 1 offset”). A change in the level of the comparison output signal Vcomp in the “inversion detection period” and also in other channels is also detected. In the example of FIG. 6, the comparison output signal Vcomp is at the high level in any offset inversion detection period of the first correction cycle tc1 and the second correction cycle tc2. Therefore, in the first correction cycle tc1 and the second correction cycle tc2, there is no change in the level of the comparison output signal Vcomp in the offset inversion detection period of the channel 1, and polarity inversion is detected in the offset of the channel 1 in the correction cycle tc2. Not.

  When the control is returned from the correction execution process of FIG. 5 to the adjustment amount correction process of FIG. 4, the adjustment control unit 600 corrects the offset of the channel 2 in step S <b> 630. Next, in step S640, the adjustment control unit 600 corrects the offset of the channel 3. Note that the processing executed in steps S630 and S640 is the same as the correction execution processing (FIG. 5) executed in step S620.

  In step S650, the first reference signal generator 660 outputs the white reference data as the first reference signal Vref1, and the second reference signal generator 670 outputs the white reference voltage as the second reference signal Vref2. To do. When the first reference signal generator 660 outputs the white reference data, the white reference data is input to the D / A converters 212, 312, and 412 via the input changeover switches 510, 520, and 530. As a result, as shown in FIG. 6, the input signals VC1 to VC3 to the D / A converters 212, 312, and 412 become white reference data.

  Next, in step S660, the adjustment control unit 600 corrects the gain of the channel 1.

  In step S710 of FIG. 5, the correction amount determination unit 640 determines whether or not the gain of the channel 1 is inverted in polarity. If polarity inversion is detected, the process proceeds to step S720. On the other hand, if polarity inversion is not detected, the process proceeds to step S730. In any channel, in the first gain correction immediately after the initialization of the correction amount (step S600), the determination in step S710 is not performed, and the process proceeds to step S730.

  In step S720, the correction amount determination unit 640 reduces the gain correction amount of the channel 1. For example, when the correction amount is 4 steps, the correction amount is reduced to 2 steps, and when the correction amount is 2 steps, the correction amount is reduced to 1 step. When the correction amount is 1 step, the correction amount is reduced to 0 step. After reducing the gain correction amount in step S720, the process proceeds to step S730.

  In step S730, it is determined whether or not the correction amount is 0 step. If the correction amount is 0 steps, the correction execution process is terminated, and the process returns to the adjustment amount correction process of FIG. On the other hand, if the correction amount is not 0 step, that is, if the correction amount is 1 step or more, the process proceeds to step S740.

  In step S740, the correction signal generation unit 630 outputs the timing signal TG1 according to the gain correction amount of the channel 1. Specifically, as shown in FIG. 6, the channel switching signal generator 620 outputs the analog video signal S1 of channel 1 by the output selector switch 604 at the rising timing of the waveform of the channel designation signal CH1 corresponding to channel 1. select. The voltage comparator 602 outputs a comparison output signal Vcomp based on the analog signal S1 of the channel 1 and the reference signal Vref2. The correction amount determination unit 640 reduces the correction amount based on the output of the polarity inversion detection unit 650. The correction signal generation unit 630 stores the comparison output signal Vcomp as adjustment information UP / DOWN in a storage unit (not shown) and generates the timing signal TG1 based on the correction amount determined by the correction amount determination unit 640. The correction signal generator 630 outputs the timing signal TG1 and the adjustment information UP / DOWN at the falling timing of the channel designation signal CH1. Based on the timing signal TG1 output from the adjustment control unit and the adjustment information UP / DOWN, the gain adjustment unit 214 corrects the gain of the channel 1 so that the voltage of the analog video signal S1 approaches the white reference voltage. Thus, the correction execution process shown in FIG. 5 is completed, and the control is returned to the adjustment amount correction process of FIG.

  In the example of FIG. 6, the adjustment information UP / DOWN is at a low level indicating that the voltage of the analog video signal S1 is lower than the white reference voltage in the correction cycle tc1. Therefore, the gain adjustment unit 214 of channel 1 increases the gain by 4 steps. On the other hand, when the voltage of the analog video signal S1 is lower than the white reference voltage and the adjustment information UP / DOWN is at a high level, the gain is lowered by 4 steps.

  The polarity inversion detection unit 650 detects the polarity inversion of the gain of the channel 1. Specifically, the polarity reversal detection unit 650 is a period during which the white reference data (white reference signal) is input to the D / A converters 212, 312, and 412 and the channel designation signal CH1 is at a high level (hereinafter, referred to as “the reference signal CH1”). A change in the level of the comparison output signal Vcomp is detected in the “channel 1 gain inversion detection period” and also in the other channels. In the example of FIG. 6, both the comparison output signals Vcomp are at the low level during the gain inversion detection period of the channel 1 of each of the two correction cycles tc1 and tc2. Therefore, in the first correction cycle tc1 and the second correction cycle tc2, there is no change in the level of the comparison output signal Vcomp in the gain inversion detection period of the channel 1, and polarity inversion is detected in the gain of the channel 1 in the correction cycle tc2. Not.

  When the control is returned from the correction execution process of FIG. 5 to the adjustment amount correction process of FIG. 4, the adjustment control unit 600 corrects the gain of the channel 2 in step S670. Next, in step S680, the adjustment control unit 600 corrects the gain of the channel 3. Note that the processing executed in steps S670 and S680 is the same as the correction execution processing (FIG. 5) executed in step S660.

  After the correction of each adjustment amount in steps S610 to S680, in step S690, the adjustment control unit 600 determines whether or not all the adjustment amounts have been corrected. Whether or not the correction of all the adjustment amounts has been completed can be determined based on whether or not the correction amounts for all the adjustment amounts are 0 steps. When the correction amounts for all the adjustment amounts are 0 steps, it is determined that all the adjustment amounts have been corrected, and the process proceeds to step S510. On the other hand, when the correction amount for at least one adjustment amount is not 0 step, it is determined that the correction of all the adjustment amounts has not been completed, and the process returns to step S610. Then, steps S610 to S690 are repeatedly executed until it is determined that the correction of all adjustment amounts has been completed.

  In the following, the process from the start of the adjustment amount correction process until the correction of all the adjustment amounts is completed will be described based on the timing chart shown in FIG. As described above, the adjustment amount correction processing is started at the rising timing (time t21) of the reset signal Reset. When the adjustment amount correction process (FIG. 4) is started, the correction amount of each adjustment amount is set to 4 steps (step S600). Then, four-step correction is performed for each adjustment amount (steps S610 to S680).

  In the example of FIG. 6, the level (low level) of the comparison output signal Vcomp in the offset inversion detection period of the channel 3 in the fourth correction cycle tc4 is the level of the comparison output signal Vcomp in the offset inversion detection period of the third correction cycle tc3. (High level) is different. That is, in the example of FIG. 6, the fourth correction is performed with respect to the polarity of the potential difference between the reference signal Vref2 and the analog signal S3 input to the voltage comparator 602 during the offset inversion detection period of the channel 3 in the third correction cycle tc3. This indicates that the polarity of the potential difference between the reference signal Vref2 and the analog signal S3 input to the voltage comparator 602 during the offset inversion detection period of the channel 3 in the cycle tc4 is different. Therefore, it is determined that polarity inversion is detected at the offset correction start time t23 of the channel 3 in the correction cycle tc4 (step S710 in FIG. 5), and the correction amount of the offset of the channel 3 is changed to two steps (step S720). ).

  Thus, by changing the offset correction amount of channel 3 to two steps, two pulses are output as timing signal TO3 in the offset correction period following the offset inversion detection period of channel 3 starting from time t23. . Similarly, in the gain correction period following the gain inversion detection period of channel 2 starting from time t24, since polarity inversion has occurred after the previous correction, two pulses are output as the timing signal TG2.

  On the other hand, with respect to other adjustment amounts (offsets of channels 1 and 2 and gains of channels 1 and 3) in which polarity inversion does not occur in the correction cycle tc4, each offset inversion detection period of the fourth correction cycle tc4 follows. In the offset correction period, four pulses are output as timing signals TO1, TO2, TG1, and TG3. In the fifth correction cycle tc5, polarity inversion occurs in these adjustment amounts, and the correction amount is changed to two steps.

  In the correction cycle tc6, polarity inversion occurs between the offset of the channel 3 and the gain of the channel 2. Therefore, each correction amount of the offset of channel 3 and the gain of channel 2 is changed to one step. On the other hand, with respect to other adjustment amounts (channel 1 and 2 offset and channel 1 and 3 gain) in which polarity inversion does not occur in the correction cycle tc6, the correction amount is not changed, and correction is performed in two steps. Is called.

  Next, in the seventh correction cycle tc7, polarity inversion occurs for other adjustment amounts (offsets of channels 1 and 2 and gains of channels 1 and 3), and the correction amount is changed to one step. The correction amount is one step.

  Thereafter, in the eighth correction cycle tc8, none of the adjustment amounts are inverted in polarity, all the adjustment amounts are corrected one step at a time, and in the ninth correction cycle tc9, polarity inversion occurs for all the adjustment amounts. Therefore, in each correction period of this correction cycle tc9, the correction amount of all adjustment amounts is changed to 0 steps.

  In this way, at the end time t29 of the correction cycle tc9 in which the correction amount of the total adjustment amount is changed to 0 step, it is determined that the correction of the total adjustment amount is completed (step S690 in FIG. 4), and the adjustment amount correction mode signal Cal is changed to a low level (step S510), and the adjustment amount correction process is terminated.

  FIG. 7 is an explanatory diagram showing how the voltage difference (error voltage) between the analog video signal and the second reference signal Vref2 is reduced by correcting the offset. The horizontal axis in FIG. 7 indicates the elapsed time from the start of correction, and the vertical axis indicates the error voltage. The unit of the elapsed time is a time (unit correction time) tc for one correction cycle in which the offset and gain of the three channels are corrected, that is, a time for executing steps S610 to S680 in FIG. 4 once. The unit of the vertical axis is mV.

  In FIG. 7, the graph indicated by a circle shows an example in which this embodiment is applied. A graph indicated by a triangle indicates an example in which the initial correction amount is two steps, and a graph indicated by a square indicates an example in which the correction amount is not changed. In the example of FIG. 7, the initial error voltage (before offset correction) is −43 mV. Then, the offset changes by 2 mV by one-step offset correction. Therefore, the offset is changed by 4 mV by the offset correction of 2 steps, and the offset is changed by 8 mV by the offset correction of 4 steps. Note that the graph of FIG. 7 shows how offset correction for one channel is performed. For the sake of simplicity, it is illustrated that the polarity of other adjustment amounts is reversed similarly to the offset of the channel.

  When this embodiment is applied, four-step offset correction is performed until 6 tc elapses from the start of correction. That is, steps S610 to S680 are repeated six times. During this period, the offset increases and the error voltage increases. Then, after 6 tc has elapsed from the start of correction, polarity inversion is detected and the correction amount is changed to two steps. At this time, the level of the comparison output signal Vcomp is inverted from the initial stage (tc = 0). Therefore, the offset correction direction is reversed, the offset is lowered, and the error voltage is lowered. When this two-step offset correction is performed for 2 tc (when steps S610 to S680 are repeated twice), polarity inversion is detected. When one-step offset correction is further performed for 2 tc (when steps S610 to S680 are repeated twice), the offset increases, the error voltage increases, and polarity inversion is detected. Thus, when this embodiment is applied, the error voltage of −43 mV is corrected to a range of 2 mV in width during the period of 10 tc. Hereinafter, when the error voltage falls within the range of the correction amount (basic correction amount) of 2 mV per step in this way is referred to as “convergence”.

  On the other hand, as shown in the graph indicated by the triangle in FIG. 7, when the initial correction amount is 2 steps, it takes 12 tc to converge. Furthermore, as shown in the graph shown by the square, when the correction amount is set to one step without changing the correction amount, it takes 22 tc to converge.

  As described above, in this embodiment, when polarity inversion occurs in the adjustment amount, that is, when the output signals S1 to S3 of the video signal generation units 200, 300, and 400 reach the reference signal Vref2, they are within the unit correction time. The amount of offset and gain correction is reduced. Therefore, the offset and gain correction time, that is, the preparation period shown in FIG. 6 can be shortened while maintaining the offset and gain correction accuracy sufficiently high. For this reason, it is possible to sufficiently and quickly suppress display unevenness.

  In this embodiment, the output signals S1 to S3 of the three-channel video signal generation units 200, 300, and 400 are directly compared in the voltage comparator 602, thereby determining the offset and gain correction directions. Therefore, the circuit scale can be made smaller than when the correction amount is determined using an A / D converter or the like, and the entire apparatus of the video output apparatus 10 can be further simplified. By further simplifying the entire apparatus in this way, the entire apparatus can be easily reduced in size or made into one chip.

  In this embodiment, the correction amount is sequentially reduced twice from the initial four steps to two steps and one step, but the number of correction amounts and the reduction pattern are not necessarily limited to this. The number of correction amount reductions can be any number greater than or equal to one. For example, the initial correction amount may be two steps, and then the correction amount may be one step. Further, the correction amount may be reduced step by step from 4 steps to 1 step. However, it is more preferable that the correction amount after the reduction is ½ of the correction amount before the reduction in that the correction amount can be reduced more easily. In particular, when the adjustment amount is corrected with the number of pulses corresponding to the correction amount as in the present embodiment, the number of pulses can be reduced by increasing the number of stages of the flip-flop circuit that passes the pulse signal. It is more preferable that the correction amount after reduction is ½ of the correction amount before reduction.

  In this embodiment, the correction amount is changed for each adjustment amount as described above, so that the correction can be performed without interruption until the polarity inversion occurs in all the adjustment amounts. For this reason, the adjustment amount can be corrected in a shorter time.

B. Variations:
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

B1. Modification 1:
In the above embodiment, the liquid crystal display 100 is driven by dividing the screen into three channels, but the number of channels dividing the screen is an arbitrary number (2, 6, 12, etc.) as long as it is an integer of 2 or more. can do. In this case, the video output device is provided with the number of video signal generation units corresponding to the number of channels, and the configuration of the video output device and the content of the adjustment amount correction process are appropriately changed according to the number of channels. In each of the above embodiments, the screen division direction of the liquid crystal display is the horizontal direction, but the screen division direction may be the vertical direction.

B2. Modification 2:
In the above embodiment, a normally black type liquid crystal display 100 is used, but a normally white type liquid crystal display can also be used. In this case, the gain is adjusted when the black reference signal is output, and the offset is adjusted when the white reference signal is output.

B3. Modification 3:
In the above embodiment, the second reference signal generation unit 670 of the adjustment control unit 600 outputs the second reference signal Vref2, but the analog video signal of any one of a plurality of channels is used as the second reference signal. It can also be used as a signal. In this case, the voltage comparator 602 compares the analog video signal of the reference channel with the analog video signal of the other channel, and outputs a comparison output signal Vcomp. For example, when the reference channel is channel 1, the analog video signal S1 and a video signal selected from the analog video signal S2 and the analog video signal S3 are input to the voltage comparator 602. Then, the offset and gain are adjusted for channel 2 and channel 3. This also makes it possible to adjust the adjustment levels of a plurality of channels. However, it is more preferable to adopt the configuration of the above embodiment in that the offset and gain can be adjusted to more appropriate values.

B4. Modification 4:
In the above embodiment, as shown in FIG. 6, the adjustment amount is not corrected after the adjustment amount correction process in the power-on preparation period. However, the adjustment amount is corrected during a period in which no video is displayed. If so, it can be appropriately performed. For example, the adjustment amount may be corrected at the time of the vertical blanking period, switching of the input video signal, or returning from the standby mode (standby mode).

  Note that when the adjustment amount is corrected in the vertical blanking period after the adjustment amount correction process in the preparation period, it is considered that there is no large variation in the adjustment amount, and the adjustment is reliably completed during the vertical blanking period. It is more preferable to perform one-step correction without changing the correction amount. It is also possible to correct the adjustment amount only in the vertical blanking period. In this case, in order to complete the correction of the adjustment amount more quickly, it is preferable that the correction amount adjustment process is performed with the initial correction amount set to 2 steps or more (for example, 4 steps) as in the above embodiments.

  On the other hand, when returning from the standby mode, preparation operations for displaying video such as setting of various registers are performed, so that a sufficient preparation period can be taken. Further, the adjustment amount may be largely changed or initialized during the standby mode. Therefore, when returning from the standby mode or the like, it is preferable to perform the above-described correction amount adjustment processing with the initial correction amount set to two steps or more (for example, four steps).

B5. Modification 5:
In the above embodiment, the correction amount is reduced when the polarity inversion occurs in the adjustment amount. However, the correction amount does not necessarily have to be reduced when the polarity inversion occurs. For example, the adjustment amount may be increased or decreased by a large correction amount in a predetermined period immediately after the start of correction of the adjustment amount, and the adjustment amount may be increased or decreased by a smaller correction amount after the predetermined period has elapsed. Further, the adjustment amount may be increased or decreased with a large correction amount during the preparation period when the power is turned on or when returning from the standby mode, and the adjustment amount may be increased or decreased with a smaller correction amount during the vertical blanking period. In general, it is only necessary that the correction amount in the later period is smaller than the correction amount in the previous period in the period in which the adjustment amount is corrected. Even in this case, the adjustment amount is increased / decreased by a large correction amount in the previous period, and the adjustment amount is increased / decreased by a small correction amount in the subsequent period. It is possible to increase the correction accuracy. However, it is more preferable to reduce the correction amount when polarity inversion occurs in the adjustment amount because the period during which the adjustment amount is increased or decreased with a large correction amount can be shortened.

B6. Modification 6:
In the above embodiment, the gain and offset of the D / A converters 212, 312, and 412 are adjusted to correct the adjustment amount for adjusting the levels of the output signals (analog video signals) S1 to S3. The adjustment amount may be corrected by correcting only one of the gain and the offset.

B7. Modification 7:
In the above embodiment, the gain and offset of the D / A converters 212, 312, and 412 are corrected to correct the adjustment amount for adjusting the levels of the output signals S1 to S3. If it is possible to correct the adjustment amount of the level adjustment in S3, other configurations can be adopted. For example, it is possible to adjust the level of the output signal using a level adjustment unit that receives an analog video signal. In this case, the gain can be adjusted by an analog multiplier, a programmable gain amplifier, or the like, and the offset can be adjusted by an analog adder constituted by an operational amplifier.

B8. Modification 8:
It is also possible to use the liquid crystal display 100 and the video output device 10 in the above embodiment for a projector. By using the liquid crystal display 100 as a liquid crystal panel that modulates light in the projector and supplying a video signal from the video output device 10 to the liquid crystal panel, both miniaturization of the projector and suppression of display unevenness in the projected video are achieved. Therefore, it is possible to shorten the preparation period until the video is displayed or to improve the correction accuracy of the adjustment amount.

B9. Modification 9:
In the above embodiment, the liquid crystal display 100 is used, but the present invention is a display device in which the optical state of each pixel is determined according to the level of the video signal, and one screen is divided into a plurality of channels and driven. If there is, it can be applied to any display device. The present invention can also be applied to, for example, an organic EL (Electro-Luminescence) display or a plasma display.

  In the above embodiment, a part of the configuration realized by hardware may be replaced by software, and conversely, a part of the configuration realized by software may be replaced by hardware. Good.

1 is a circuit diagram showing a configuration of a liquid crystal display to which a video output device as one embodiment of the present invention is connected. The circuit diagram which shows the structure of the video output apparatus to which a liquid crystal display is connected. The block diagram which shows schematic structure of the adjustment control part with which a video output device is provided. The flowchart which shows the adjustment amount correction process performed by the adjustment control part. The flowchart which shows the correction execution process performed in step S620. 6 is a timing chart illustrating changes in signals inside the video output device when the adjustment control unit is executing adjustment amount correction processing. Explanatory drawing which shows a mode that the voltage difference of an analog video signal and a 2nd reference signal is reduced by correct | amending offset.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Video output device 100 ... Liquid crystal display 110 ... Liquid crystal panel 112 ... Scanning line 114 ... Signal line 116 ... Pixel electrode 118 ... Pixel TFT
DESCRIPTION OF SYMBOLS 120 ... Scan line drive circuit 122 ... Y direction scan circuit 130 ... Signal line drive circuit 140 ... X direction scan circuit 150 ... Enable control part 151-15n ... AND circuit 160 ... Precharge drive circuit 161-16n ... OR circuit 170 ... Scan TFT
200, 300, 400 ... Video signal generation unit 210, 310, 410 ... D / A conversion unit 212, 312, 412 ... D / A converter 214, 314, 414 ... Gain adjustment unit 216, 316, 416 ... Offset adjustment unit 220, 320, 420 ... IV converters 222, 322, 422 ... operational amplifiers 224, 324, 424 ... resistors 510, 520, 530 ... input changeover switch 600 ... adjustment control unit 602 ... voltage comparator 604 ... output changeover switch 610 ... adjustment mode signal generator 620 ... channel switching signal generator 630 ... correction signal generator 640 ... correction amount determiner 650 ... polarity inversion detector 660 ... first reference signal generator 670 ... second reference signal generator 800 ... Reset generation circuit 900 ... Display timing generator CLK ... Clock signal ENBX ... Enable Signal terminal PreCHG: precharge timing signal terminals VID1 to VID3: analog video terminals Vsync ... vertical synchronization signal Hsync ... horizontal synchronization signal Cal ... adjustment amount correction mode signal Vref1 ... first reference signal Vref2 ... second reference signal CH1- CH3 ... Channel designation signal V1 to V3 ... Digital video signal VC1 to VC3 ... Input signal S1 to S3 ... Analog video signal S4 ... Enable signal S5 ... Precharge timing signal S6 ... Horizontal start signal S7 ... Horizontal clock signal S8 ... Vertical start signal S9: Vertical clock signal Sx: Analog video signal Vcomp: Comparison output signal TG1-TG3: Timing signal TO1-TO3: Timing signal UP / DOWN ... Adjustment information Reset ... Reset signal Vdd ... Power supply voltage

Claims (9)

A video output device that outputs a video signal to a display device that is driven by dividing one screen into a plurality of channels,
A plurality of level adjustment units provided for each of the plurality of channels, for adjusting a level of a video signal input for each channel and outputting the level to the display device;
In a non-display period in which the video signal is not output to the display device, a reference signal input unit that inputs a first reference signal to each of the level adjustment units;
Each of the reference signals output from the level adjustment unit when the first reference signal is input is compared with a second reference signal corresponding to the first reference signal, and the reference signal is the first reference signal. An adjustment amount correction unit that increases or decreases each adjustment amount of the level adjustment unit so as to be adjusted toward the reference signal of 2;
Increase / decrease amount that makes the increase / decrease amount of the adjustment amount in the second period after the first period smaller than the increase / decrease amount of the adjustment amount in the first period in the period in which the adjustment amount is corrected. With a reduction section,
The first period is a period until said control signal reaches the second reference signal, the second period of time, Ri period der after the arrival,
The adjustment amount correction unit includes a signal comparator that compares each of the reference signals with the second reference signal and determines a magnitude relationship between the reference signal and the second reference signal.
The increase / decrease reduction unit determines that the reference signal has reached the second reference signal when the magnitude relationship between the reference signal and the second reference signal determined by the signal comparator is inverted. The video output device in which the increase / decrease amount in each of the first and second periods is constant until the increase / decrease amount is reduced and the magnitude relationship is reversed . The video output device according to claim 1 Symbol placement,
The increase / decrease amount is an integral multiple of the minimum correction amount that can be corrected as the adjustment amount,
The increase / decrease amount reduction unit reduces the increase / decrease amount by reducing a magnification with respect to the minimum correction amount. The video output device according to claim 2 ,
The adjustment amount correction unit supplies a number of pulses corresponding to the increase / decrease amount to the level adjustment unit,
The level adjustment unit increases or decreases the adjustment amount by the minimum correction amount for each input of the pulse. The video output device according to claim 3 ,
The said increase / decrease amount reduction part reduces the said increase / decrease amount by making the said magnification 1/2 time before the said reach | attainment. The video output device according to any one of claims 1 to 4 ,
Each of the level adjustment units
It has a digital / analog converter that converts a digital signal that is a video input signal into an analog signal,
The adjustment amount correction unit adjusts the level of the video signal by adjusting at least one of a gain and an offset in the digital / analog converter. The video output device according to any one of claims 1 to 5 ,
The non-display period includes a preparation period before display start in the display device,
Increase / decrease of the adjustment amount by the adjustment amount correction unit is executed a plurality of times during the preparation period. The video output device according to any one of claims 1 to 6 ,
The non-display period includes a vertical blanking period. A projector having a display device that is driven by dividing one screen into a plurality of channels, and a video output device that outputs a video signal to the display device,
The video output device
A plurality of level adjusters provided for each of the plurality of channels, for adjusting a level of a video signal output to the display device;
In a non-display period in which the video signal is not output to the display device, a reference signal input unit that inputs a first reference signal to each of the level adjustment units;
Each of the reference signals output from the level adjustment unit when the first reference signal is input is compared with a second reference signal corresponding to the first reference signal, and the reference signal is the first reference signal. An adjustment amount correction unit that increases or decreases each adjustment amount of the level adjustment unit so as to be adjusted toward the reference signal of 2;
Increase / decrease amount that makes the increase / decrease amount of the adjustment amount in the second period after the first period smaller than the increase / decrease amount of the adjustment amount in the first period in the period in which the adjustment amount is corrected With a reduction section,
The first period is a period until said control signal reaches the second reference signal, the second period of time, Ri period der after the arrival,
The adjustment amount correction unit includes a signal comparator that compares each of the reference signals with the second reference signal and determines a magnitude relationship between the reference signal and the second reference signal.
The increase / decrease reduction unit determines that the reference signal has reached the second reference signal when the magnitude relationship between the reference signal and the second reference signal determined by the signal comparator is inverted. Then, the increase / decrease amount in each of the first and second periods is constant until the increase / decrease amount is reduced and the magnitude relationship is reversed . A video output method for outputting a video signal to a display device that is driven by dividing one screen into a plurality of channels,
In a non-display period in which the video signal is not output to the display device, a first reference is provided to each of the plurality of level adjustment units that are provided for each of the plurality of channels and adjust the level of the video signal output to the display device. Input signal,
Each of the reference signals output from the level adjustment unit when the first reference signal is input is compared with a second reference signal corresponding to the first reference signal, and the reference signal is the first reference signal. Increasing or decreasing the respective adjustment amount of the level adjustment unit so that the adjustment is performed toward the reference signal of 2;
Of the period in which the adjustment amount is corrected, the increase / decrease amount of the adjustment amount in the first period, which is the period until the reference signal reaches the second reference signal, in the period after the arrival. Decrease the increase / decrease amount of the adjustment amount in a second period ,
The video output method , wherein the increase / decrease amount of the adjustment amount in the first period is constant, and the increase / decrease amount of the adjustment amount in the second period is constant .

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