JP5549602B2 - Liquid crystal display device and driving method thereof - Google Patents

Description

  The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, a reflective liquid crystal that drives a liquid crystal display element with an analog voltage obtained by digital-analog conversion (hereinafter referred to as DA conversion) of a digital video signal using a ramp signal. The present invention relates to a liquid crystal display device used for a projector apparatus and the like and a driving method thereof.

  In recent years, a liquid crystal on silicon (LCOS) type liquid crystal display device is often used as a central part for projecting an image in a projector device or a projection television. In the display method of the liquid crystal display device such as LCOS, an analog video signal is conventionally input to a semiconductor element such as a CMOS (Complementary Metal Oxide Semiconductor), and the signal is held as it is on the pixel electrode of the liquid crystal display element for each pixel. A method of changing the orientation of the liquid crystal, a method of applying a video signal that has been subjected to pulse width modulation (PWM) by a digital signal to the pixel electrode of the liquid crystal display element, and driving by switching the orientation of the liquid crystal over time. there were. Among them, the method of directly applying an analog signal to the pixel electrode has a problem that liquid crystal burn-in easily occurs.

  In order to solve the problem, the present applicant firstly intersects each of a plurality of data lines each including two data lines (column signal lines) and a plurality of gate lines (row scanning lines). Each pixel is disposed in a portion, and in each of the pixels, a positive video signal and a negative video signal are separately sampled and held in two holding capacitors, and then the holding voltage is alternately applied to the pixel electrode to liquid crystal A liquid crystal display device in which the display element is AC driven has been proposed (see, for example, Patent Document 1).

  In this liquid crystal display device, as shown in FIG. 7, the positive electrode monotonously increases in a period of one horizontal scanning period (1H) from the digital data value “00” (black level) to the digital data value “FF” (white level). And a negative ramp signal RAMP1- that monotonously decreases in one horizontal scanning period (1H) from the digital data value “00” (black level) to the digital data value “FF” (white level). A common number of video switches are simultaneously supplied to a number of video switches corresponding to the number of pixels in one line. Here, each set of video switches includes a positive video switch supplied with a positive ramp signal RAMP1 + and a negative video switch supplied with a negative ramp signal RAMP1-.

  Then, after all the video switches are turned on all at the start of the horizontal scanning period, the counter value indicating the gradation obtained by counting the clocks synchronized with the ramp signals RAMP1 + and RAMP1- by the counter and the pixels of the digital video signal A comparator that compares the values in units of pixels of one line outputs a coincidence pulse when they coincide with each other, and simultaneously turns off a set of video switches provided corresponding to the pixels. The RAMP1 + and RAMP1- voltages are sampled and supplied to a positive holding capacitor and a negative holding capacitor in a pixel connected to a set of video switches that are turned off via a set of data lines. Then, sampling and holding of the signal voltage obtained by converting the digital video signal into the analog video signal is performed.

  The voltage of the ramp signal RAMP1 + corresponding to the pixel value of the positive video signal sampled and held in the positive holding capacitor and the ramp corresponding to the pixel value of the negative video signal sampled and held in the negative holding capacitor The voltage of the signal RAMP1- is alternately switched at a predetermined cycle shorter than the vertical scanning frequency and applied to the pixel electrode of the liquid crystal display element. The liquid crystal display element has a structure in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode provided to face each other. Here, when the voltage of the ramp signal RAMP1 + sampled and held in the positive holding capacitor is applied to the pixel electrode, the common electrode voltage at the level indicated by Vcom1 + in FIG. When the voltage of the ramp signal RAMP1- sampled and held in the capacitor is applied to the pixel electrode, the common electrode voltage at the level indicated by Vcom1- in FIG. 7 is applied to the common electrode.

  Accordingly, the voltage applied to the liquid crystal layer is the difference voltage between the applied voltage of the pixel electrode and the applied voltage of the common electrode, and therefore the voltage of the ramp signal RAMP1 + sampled and held in the positive holding capacitor is applied to the pixel electrode. When the voltage of the ramp signal RAMP1- sampled and held in the negative holding capacitor is applied to the pixel electrode, the voltage is indicated by Vm1 in FIG. Although the direction is reversed, the same applied voltage is applied to the liquid crystal layer with the same data. By switching this at high speed, the brightness displayed in the case of the same data does not change, but the pixel electrode and the common electrode Since the voltage applied to is opposite in polarity, it is possible to make it difficult for image sticking to occur.

  In this liquid crystal display device, the voltage applied to the pixel electrode can be held in the holding capacitor for positive polarity and the holding capacitor for negative polarity for one frame period, respectively. Regardless of the frequency, it can be set freely in the inversion control cycle in the pixel circuit. As a result, according to this liquid crystal display device, the AC drive frequency can be set to be extremely higher than the vertical scanning frequency, thereby preventing burn-in and preventing deterioration in display quality such as reliability, stability, and spots. In addition, it is possible to obtain features such as that the gradation can be correctly expressed by the digital PWM method.

JP 2009-223289 A

  However, in the above-described liquid crystal display device, each pixel outputs two ramp signal voltages held in two holding capacitors through two source follower circuits, which are alternately selected by switching transistors and applied to the pixel electrodes. Therefore, a variation in the threshold voltage Vth of the transistor of the source follower circuit occurs for each pixel, which becomes a problem.

  That is, the voltage of the ramp signal RAMP1 + sampled and held in the positive holding capacitor is the voltage indicated by Vp1 in FIG. 7, but when the Vth of the transistor in the positive source follower circuit is higher than the average value, FIG. As shown in FIG. 5, the voltage is increased by Vlv1 corresponding to the error and applied to the pixel electrode. In this case, the pixel state is brighter than the correct brightness.

  On the other hand, the voltage of the ramp signal RAMP1- sampled and held in the negative holding capacitor is the voltage indicated by Vm1 in FIG. 7, but when the Vth of the transistor in the source follower circuit on the negative polarity side is higher than the average value, FIG. As shown in FIG. 7, the voltage is increased by Vlv2 corresponding to the error and applied to the pixel electrode. In this case, the pixel state is darker than the correct brightness. As described above, if there is an error in which the Vth of the transistor of the source follower circuit on the positive polarity side in each pixel and the Vth of the transistor of the source follower circuit on the negative polarity side deviate from the normal values, the correct brightness is obtained. The shifted state is displayed.

  When the positive pixel electrode voltage and the negative pixel electrode voltage are switched, for example, at a cycle of 2 kHz, the brightness of the liquid crystal display element when these pixel electrodes are applied is averaged. Bright fixed pattern noise (FPN) or dark FPN occurs due to the difference between the average of the pixel electrode voltage and the negative pixel electrode voltage.

  Here, the brightness Xp of the liquid crystal display element when the positive pixel electrode voltage shown in FIG. 7 is applied is expressed by the following equation.

Xp = fp × (Vp1 + Vlv1) (1)
In the equation (1), fp is a function for calculating the display brightness when voltage is applied, Vp1 is an input voltage of the positive side holding capacitor in the pixel, and Vlv1 is a variation voltage of the positive side source follower circuit of the pixel. is there. Further, the brightness Xm of the liquid crystal display element when the negative pixel electrode voltage shown in FIG. 7 is applied is expressed by the following equation.

Xm = fm × (Vm1−Vlv2) (2)
In the equation (2), fm is a function for calculating display brightness when voltage is applied, Vm1 is an input voltage of the negative side holding capacitor in the pixel, and Vlv2 is a variation voltage of the negative side source follower circuit of the pixel. is there. The brightness seen by the observer is the average of the above brightness Xp and Xm, giving a feeling of roughness.

  In addition, the liquid crystal display device has a problem in that defective pixels such as bright spots and black spots are likely to occur because the number of devices used in the pixel circuit is large.

  The present invention has been made in view of the above points, and by suppressing variations in pixels, a liquid crystal display device that can reduce FPN in a display image, improve display quality, and suppress luminescent spots, black spots, etc. to some extent. And it aims at providing the driving method.

In order to achieve the above object, the liquid crystal display device of the present invention has a plurality of data lines provided at intersections where a plurality of sets of data lines and a plurality of row scanning lines intersect each other. Each of the pixels
When the display element in which the liquid crystal layer is sandwiched between the opposing pixel electrode and the common electrode, and the pixel value of the input digital data coincide with the reference gradation data whose level changes monotonically in the horizontal scanning cycle, a set The voltage of the positive ramp signal that monotonously increases in level in synchronization with the reference grayscale data supplied through one of the two data lines is sampled to the first holding capacitor for a certain period. The first sampling and holding means to be held, and the reference floor supplied via the other data line of the set of two data lines when the pixel value of the input digital data matches the reference gradation data Second sampling and holding means for sampling the voltage of the negative polarity ramp signal having a polarity opposite to that of the positive polarity ramp signal and monotonously decreasing in synchronization with the tone data and holding the voltage in the second holding capacitor for a certain period of time , The first storage capacitor and the holding voltage of the second storage capacitor, read alternately in a short predetermined period than the vertical scanning period, the voltage read from the first storage capacitor through the first source follower circuit, voltage read from the second storage capacitor through the second source follower circuit, and holding the voltage reading means applied to the pixel electrode, and the normal state of the same data value and the display should do digital data data, a digital to be displayed a data input means for the input of the inverting an inverted state of the data value of the data and data as input digital data by switching alternately frame by frame, by holding the voltage reading means, corresponding to the pixel values of the data in a normal state positive during sexual ramp signal and negative ramp signal reading of the pixel held in the first and second storage capacitors, read from the first storage capacitor Out and the first common electrode voltage of the first potential is applied to the common electrode during the application of the first hold voltage of the pixel electrode of positive polarity ramp signal, and negative lamp read from the second storage capacitor When a second holding voltage of a signal is applied to the pixel electrode, a second common electrode voltage having a second potential higher than the first potential is applied to the common electrode, and corresponds to the pixel value of the inverted data. When reading out a pixel in which the positive and negative ramp signals are held in the first and second holding capacitors, the pixel electrode of the third holding voltage of the positive ramp signal read out from the first holding capacitor is read. common electrode voltage is applied to the common electrode, and, first upon application to the pixel electrode of the fourth holding voltage of the negative polarity ramp signal read from the second storage capacitor third of a second potential upon application of Apply the fourth common electrode voltage of the potential to the common electrode Common electrode voltage input means, a first holding capacitor holding a positive ramp signal corresponding to the pixel value of normal data, and a negative ramp signal corresponding to the pixel value of normal data. The first storage capacitor in which the positive-polarity ramp signal corresponding to the pixel value of the inverted data is held alternately by switching the readout order with the second storage capacitor in units of normal data input periods; A plurality of readout order switching means for alternately switching the readout order with respect to the second storage capacitor in which the negative ramp signal corresponding to the pixel value of the inverted data is held, in units of the inverted data input period ; the brightness of the display screen by the pixels, and characterized in that the average of the first to brightness corresponding to the fourth holding voltage applied to the pixel electrode and through the first or the second source follower circuit That.

In order to achieve the above object, a driving method of a liquid crystal display device according to the present invention includes an intersection where a plurality of sets of data lines and a plurality of row scanning lines intersect each other. Each of the plurality of pixels provided in the
When the display element in which the liquid crystal layer is sandwiched between the opposing pixel electrode and the common electrode, and the pixel value of the input digital data coincide with the reference gradation data whose level changes monotonically in the horizontal scanning cycle, a set The voltage of the positive ramp signal that monotonically increases in synchronization with the reference grayscale data supplied via one of the two data lines is sampled for a first period of time. When the pixel value of the input digital data and the reference gradation data match with the first sampling and holding means held in the capacitor, the first sampling and holding means is supplied via the other data line of the set of two data lines. A second sampling in which the voltage of a negative ramp signal having a polarity that is monotonously decreased in synchronization with the reference gradation data and having a polarity opposite to that of the positive ramp signal is sampled and held in the second storage capacitor for a certain period; And lifting means, the first storage capacitor and the holding voltage of the second storage capacitor, read alternately in a short predetermined period than the vertical scanning period, the voltage read from the first storage capacitor first source follower A voltage read from the second storage capacitor through the circuit is supplied to the pixel electrode through the second source follower circuit .
Normal data having the same data value as the digital data to be displayed and inverted data obtained by inverting the data value of the digital data to be displayed are alternately switched in units of one frame and supplied to the pixel as input digital data. a data input step of, by the holding voltage reading means, at the time of reading the pixel to which a positive polarity ramp signal and negative ramp signal corresponding to the pixel value of data held in the first and second storage capacitors in a normal state, the The first common electrode voltage of the first potential is applied to the common electrode when the positive holding ramp signal of one holding capacitor is applied to the pixel electrode, and the negative polarity of the second holding capacitor first and second common conductive applying a second common electrode voltage of the second potential of higher than the first potential when applied to the pixel electrode of the second holding voltage of the ramp signal to the common electrode A voltage input step, at the time of reading the pixel to which a positive polarity ramp signal corresponding to the pixel values of the data of the inverted state and the negative polarity ramp signal is held by the first and second storage capacitors, a positive polarity of the first storage capacitor Applying the third common electrode voltage of the second potential to the common electrode when the third holding voltage of the ramp signal is applied to the pixel electrode, and the fourth holding of the negative polarity ramp signal of the second holding capacitor A third common electrode voltage input step for applying a fourth common electrode voltage of a first potential to the common electrode when a voltage is applied to the pixel electrode, and a positive polarity corresponding to the pixel value of the data in the normal state The reading order of the first holding capacitor in which the ramp signal is held and the second holding capacitor in which the negative polarity ramp signal corresponding to the pixel value of the data in the normal state is set as the unit of the input period of the data in the normal state First to switch alternately A reading order switching step, a first holding capacitor holding a positive ramp signal corresponding to a pixel value of inverted data, and a first holding capacitor holding a negative ramp signal corresponding to a pixel value of inverted data. And a second reading order switching step of alternately switching the reading order with respect to the storage capacitor in units of the input period of the inverted data, and the brightness of the display screen by the plurality of pixels is set to the first or second The brightness is averaged according to the first to fourth holding voltages applied to the pixel electrode through the source follower circuit .

  According to the present invention, it is possible to reduce the FPN in the display image and improve the display quality by suppressing the pixel variation without changing the basic pixel circuit, and to some extent bright spots, black spots, etc. Can be suppressed.

1 is a system configuration diagram of an embodiment of a liquid crystal display device of the present invention. It is a schematic block diagram of one Embodiment of the liquid crystal panel drive element in FIG. FIG. 2 is an equivalent circuit diagram of an example of one pixel constituting the pixel unit in FIG. 1. It is a figure which shows the combination of the input data of a frame unit and common electrode voltage in embodiment of FIG. FIG. 2 is a diagram illustrating a relationship among inverted data, a ramp signal, and a common electrode voltage input to the liquid crystal panel driving element in FIG. 1. It is a figure which shows the relationship between the input data of a frame unit in Embodiment of FIG. 1, and a common electrode voltage. It is a figure which shows the relationship between the data of a normal state input into a liquid crystal panel drive element, a ramp signal, and a common electrode voltage.

  Next, embodiments of the present invention will be described with reference to the drawings.

  Problems with conventional liquid crystal display devices are mainly caused by Vth variation of the transistors of the source follower circuit for each pixel, so it is conceivable to perform correction for each pixel. It is difficult to realize.

  The first problem is that when the correction circuit is configured in the pixel of the liquid crystal panel driving element, it is necessary to increase the number of elements, and when the pixel pitch is narrow, it is difficult to realize the correction circuit. A second problem is that when a correction memory is provided outside the liquid crystal panel driving element, a memory for a frame is required and the system becomes large. In addition, it is difficult to accurately import correction data using a camera or the like. The third problem is that in a liquid crystal display device having a storage capacitor for each of a positive signal voltage and a negative signal voltage in one pixel, the amount of data increases, and two types of data are required for accurate correction. This means that it is necessary to input data and high-speed data input is required.

  However, the variation in Vth of the transistor of the source follower circuit on the positive polarity side of the pixel and that of the transistor of the source follower circuit on the negative polarity side are considered when the difference from the Vth of the transistor of the average source follower circuit of each pixel is considered. Although there is an influence of the substrate effect, it is shifted in the same direction for any input voltage with respect to a correct signal level, and its state is hardly changed.

  Therefore, in the liquid crystal display device of the present embodiment described below, paying attention to this point, the feeling of roughness is improved without using the above correction method.

  FIG. 1 shows a system configuration diagram of an embodiment of a liquid crystal display device according to the present invention. As shown in FIG. 1, the liquid crystal display device 10 according to the present embodiment includes a panel drive external drive circuit 11 and a liquid crystal panel drive element 12. The panel driving external drive circuit 11 generates n-bit digital data (digital video signal), a V shift clock, a pixel selection signal, and a common electrode voltage of the liquid crystal display element, and supplies it to the liquid crystal panel drive element 12. Supply.

  When n bits are 8 bits, n bit digital data uses “00” to “FF”, “00” is the darkest data and “FF” is the brightest data (hereinafter, this data is referred to as “normal”. State data) and “00” is the brightest data and “FF” is the darkest data (hereinafter, this data is referred to as “inverted data”). The panel drive external drive circuit 11 supplies the normal state data and the inverted state data alternately to the liquid crystal panel drive element 12 in units of one frame. Since the inverted data is inverted from the normal data, the inverted data “00” is “FF” in the normal data value and the inverted data “FF”. Is “00” in the data value of the normal state.

  The V shift clock is a clock for selecting a horizontal line for writing n-bit digital data for each horizontal line of the pixel portion in the liquid crystal panel driving element 12. The pixel selection signal is a signal for selecting whether to read the signal voltage held in the positive-side storage capacitor to the pixel electrode or to read the signal voltage held in the negative-side storage capacitor to the pixel electrode. . Further, the common electrode voltage is a voltage applied to the common electrode of the liquid crystal display element, and changes to one of two voltage values in synchronization with the pixel selection signal.

  FIG. 2 shows a schematic block diagram of an embodiment of the liquid crystal panel driving element 12. As shown in the figure, the liquid crystal panel driving element 12 includes a horizontal shift register and comparator 121, a horizontal driving circuit (such as a video switch) 122, a pixel portion 123 in which a plurality of pixels are arranged in a two-dimensional matrix, The configuration includes a vertical shift register 124 and a pixel selection circuit 125.

  Each of the plurality of pixels constituting the pixel portion 123 may be the same as the pixel described in Patent Document 1 and may be configured by the equivalent circuit shown in FIG. In FIG. 3, source follower P-channel MOS transistors (hereinafter referred to as PMOS transistors) Tr3 and Tr4 have gates of holding capacitors C1 and C2 and pixel selection N-channel MOS transistors (hereinafter referred to as NMOS transistors) Tr1 and Tr2. The source of the switching PMOS transistors Tr5 and Tr6 is connected to the drain of the constant current PMOS transistor Tr7 through the drain and source of the switching PMOS transistors Tr5 and Tr6. Each connection point of the transistors Tr5, Tr6, and Tr7 is connected to the pixel electrode PE. The liquid crystal display element LC has a structure in which a liquid crystal layer LCM is sandwiched between a pixel electrode PE and a common electrode CE that are arranged to face each other, and a common electrode voltage Vcom is applied to the common electrode CE.

  The i-th column positive data line Di + is connected to the drain of the NMOS transistor Tr1, and the i-th column negative data line Di- is connected to the drain of the NMOS transistor Tr2. The gates of the NMOS transistors Tr1 and Tr2 are commonly connected to a j-th row scanning line (gate line) Gj. Note that the drains of the NMOS transistors Tr1 and Tr2 of each pixel in the same i-th column are also connected to the data lines Di + and Di-. The gates of the NMOS transistors Tr1 and Tr2 of each pixel in the same j-th row are also connected to the row scanning line Gj.

  In this pixel, the positive and negative analog signals (the ramp signal) input via the data lines Di + and Di− are sampled by the NMOS transistors Tr1 and Tr2 and held in the holding capacitors C1 and C2. . At the time of subsequent reading, the PMOS transistors Tr5 and Tr6 are alternately turned on at a predetermined cycle shorter than the vertical scanning cycle by the switching signals 2k and 2kb, and hold the positive polarity holding voltage and the negative polarity holding held in the holding capacitors C1 and C2. The voltage is alternately applied to the pixel electrode PE through the source follower PMOS transistors Tr3 and Tr4. Further, the liquid crystal common electrode voltage Vcom is applied to the common electrode CE of the liquid crystal display element LC from the panel drive external drive circuit 11 of FIG. In the present embodiment, as will be described later, there are four types of liquid crystal common electrode voltages Vcom: Vcom1 +, Vcom1-, Vcom2 +, and Vcom2-.

  Returning to FIG. The vertical shift register 124 receives the V-shift clock from the panel drive external drive circuit 11, and within one vertical scanning period, each pixel of the pixel unit 123 is moved from the first horizontal line to the final horizontal line for one horizontal scanning period (1H ), A row selection signal for sequentially selecting the pixels of each horizontal line from the top to the bottom is output to the row scanning line.

  The pixel selection circuit 125 receives a pixel selection signal from the panel drive external drive circuit 11 and sets the switching PMOS transistors Tr5 and Tr6 shown in FIG. 3 of each pixel to be shorter than one vertical scanning cycle when reading out the pixel unit 123. Switching signals (2k and 2 kb in FIG. 3) that are alternately turned on and off at a cycle (for example, a cycle of 2 kHz) are output to the pixel unit 123.

  Next, the operation of the liquid crystal panel driving element 12 in FIG. 2 will be described.

  During pixel writing, n-bit digital data is input from the panel drive external drive circuit 11 of FIG. 1 to the horizontal shift register of FIG. As described above, the n-bit digital data is data synthesized in time series by switching the normal state data and the inverted state data alternately every frame. FIG. 4A schematically shows n-bit digital data input to the horizontal shift register.

  The horizontal shift register develops one line of input normal state data or inverted state data, temporarily holds it, and supplies it to the horizontal shift register and the comparator in the comparator 121. N comparators are provided for each column corresponding to n sets of data lines (column signal lines). The n comparators are commonly supplied with reference gradation data from a counter (not shown) in which a plurality of gradation values change stepwise at regular intervals within a horizontal scanning period from, for example, a minimum value to a maximum value. On the other hand, the image data held by the shift register is supplied in units of n pixels of one line, compared with each other, and when the two match, a matching pulse is supplied to the horizontal drive circuit 122.

  The horizontal drive circuit 122 includes a video switch for positive polarity connected to one data line Di + of a set of two data lines (column signal lines) Di + and Di−, and a negative electrode connected to the other data line Di−. N video switches for each data line (column signal line) unit are provided in total, and are matched with the corresponding comparators among the n comparators in the shift register and comparator 121 described above. In this configuration, pulses are supplied.

  All the video switches are turned on all at the same time at the start of the horizontal scanning period, and then the counter value indicating the gradation obtained by counting the clock synchronized with the ramp signal by the gradation counter and the input digital data (normal state) Provided in correspondence with the comparator that outputs the coincidence pulse only when the coincidence pulse is output from the comparator that compares the pixel value of the pixel data of the data or the inversion state) in pixel units of one line. A set of video switches are simultaneously turned off by the coincidence pulse input, and the voltages of the positive polarity ramp signal and the negative polarity ramp signal at this time are supplied to the set of video switches that are turned off as a set of data lines. Is supplied to the positive holding capacitor C1 and the negative holding capacitor C2 in the pixels connected via the vias, and sampling holding is performed.

  Here, at the time of writing data in the normal state to the pixel, the positive polarity ramp signal RAMP + is RAMP1 + shown in FIG. 7, and the negative polarity ramp signal RAMP− is RAMP1− shown in FIG. . Accordingly, the writing of data in the normal state to the pixels is performed in the same manner as the pixel writing of the conventional liquid crystal display device.

  When the normal state data for one frame is written to the pixel, the normal state data written to the pixel is read in a cycle shorter than one vertical scanning cycle (for example, a cycle of 2 kHz). In the present embodiment, there are two kinds of combinations of the data reading method in the normal state in relation to the voltage applied to the pixel electrode PE and the common electrode voltage Vcom applied to the common electrode CE. The first type of combination is shown as “combination 1” in FIGS. 4A and 4B, and the odd-numbered voltage applied to the pixel electrode PE is the positive electrode held in the positive-polarity holding capacitor C1. Normal state data (specifically, sampled positive polarity ramp signal RAMP1 +), and the common electrode voltage Vcom at that time is Vcom1 + in FIG. 7 as shown at a low level in FIG. The even-numbered voltage applied to the pixel electrode PE is the negative polarity normal state data held in the negative polarity holding capacitor C2 (specifically, the sampled negative polarity). The common electrode voltage Vcom at this time is a high-level common electrode voltage indicated by Vcom1- in FIG. 7, as shown at a high level in FIG. 4B.

  The second type of combination is shown as “combination 3” in FIGS. 4A and 4B and is in the reverse order of combination 1, and the odd-numbered voltage is applied to the pixel electrode PE. Normal state data (specifically, sampled negative polarity ramp signal RAMP1-), and even numbers are positive polarity normal state data (specifically, sampled positive polarity ramp signal RAMP1 +). In addition, the common electrode voltage is also in the order of Vcom1- and Vcom1 + corresponding to the voltage applied to the pixel electrode PE. Here, it is assumed that reading by the example of combination 1 is performed.

  Subsequently, writing of inverted data for the next one frame to the pixel is started. As shown in FIG. 5, the writing of the data in the inverted state monotonically increases in a cycle of 1H from the value “00” (white level) to the value “FF” (black level) of the data in the inverted state. The positive polarity ramp signal RAMP2 + and the negative polarity ramp signal RAMP2- that monotonously decreases in a 1H cycle from the value "00" (white level) to the value "FF" (black level) in the inverted state are shown in FIG. The signals are supplied simultaneously to a number of sets of video switches corresponding to the number of pixels in one line in the horizontal drive circuit 122. Here, each set of video switches includes a positive video switch to which a positive ramp signal RAMP2 + is supplied and a negative video switch to which a negative ramp signal RAMP2- is supplied.

  Then, after all the video switches are turned on all at the start of the horizontal scanning period, the counter value indicating the gradation obtained by counting the clocks synchronized with the ramp signals RAMP2 + and RAMP2- by the counter and the pixels of the digital video signal A comparator that compares the values in units of pixels of one line outputs a coincidence pulse when they coincide with each other, and simultaneously turns off a set of video switches provided corresponding to the pixels. Each of the voltages of RAMP2 + and RAMP2- is sampled, and a positive-capacitance holding capacitor (in a pixel connected to a pair of video switches turned off via a pair of data lines (Di +, Di- in FIG. 3)) It is supplied to and held in C1) of FIG. 3 and a holding capacitor for negative polarity (C2 of FIG. 3).

  When the inverted data for one frame is written to the pixel, the inverted data written to the pixel is read at a cycle of 2 kHz, for example. In the present embodiment, the data reading method in the inverted state is also related to the voltage applied to the pixel electrode PE and the common electrode voltage Vcom applied to the common electrode CE, similarly to the data reading method in the normal state. There are two types of combinations. The first type of combination is shown as “Combination 2” in FIGS. 4A and 4B, and the odd-numbered voltage applied to the pixel electrode PE is the positive electrode held in the positive-polarity holding capacitor C1. , And the common electrode voltage Vcom at that time is Vcom2 + in FIG. 5 as shown at a high level in FIG. 4B. The even-numbered voltage applied to the pixel electrode PE is the negative polarity inversion state data held in the negative polarity holding capacitor C2 (specifically, the sampled negative polarity). The common electrode voltage Vcom at this time is the low-level common electrode voltage indicated by Vcom2- in FIG. 5, as indicated by the low level in FIG. 4B.

  The second type of combination is shown as “combination 4” in FIGS. 4A and 4B, and is in the reverse order to combination 2. The odd-numbered voltage applied to the pixel electrode PE is negative. Inverted state data (specifically, sampled negative polarity ramp signal RAMP2−), and even numbers are positive polarity inversion state data (specifically, sampled negative polarity ramp signal RAMP2 +). In addition, the common electrode voltage is also in the order of Vcom2- and Vcom2 + corresponding to the voltage applied to the pixel electrode PE. Here, it is assumed that reading by the example of the combination 2 is performed.

  The reading of the inverted data will be described in more detail.

  When the voltage of the ramp signal RAMP2 + sampled and held in the positive holding capacitor C1 is applied to the pixel electrode PE, the common electrode voltage at the level indicated by Vcom2 + in FIG. When the voltage of the ramp signal RAMP2- sampled and held in the capacitor C2 is applied to the pixel electrode PE, the common electrode voltage at a level indicated by Vcom2- in FIG. 5 is applied to the common electrode CE.

  Accordingly, the voltage applied to the liquid crystal layer LCM of the liquid crystal display element LC is a difference voltage between the applied voltage of the pixel electrode PE and the applied voltage of the common electrode CE, and therefore the lamp sampled and held in the positive holding capacitor C1. When the voltage of the signal RAMP2 + is applied to the pixel electrode, the voltage is indicated by Vp2 in FIG. 5, and when the voltage of the ramp signal RAMP2- sampled and held in the negative holding capacitor C2 is applied to the pixel electrode PE, FIG. 5, the voltage application direction is reversed, but the same applied voltage is applied to the liquid crystal layer LCM with the same data. By switching this at a high speed, the data in the normal state described above can be obtained. As with reading, the brightness displayed for the same data does not change, but the voltages applied to the pixel electrode PE and the common electrode CE have opposite polarities. It can be to difficult to state which is generated with trees.

  Here, the voltage of the ramp signal RAMP2 + sampled and held in the holding capacitor for positive polarity is the voltage indicated by Vp2 in FIG. 5, but Vth of the transistor in the source follower circuit on the positive polarity side (PMOS transistor Tr3 in FIG. 3). Is higher than the average value, as shown in FIG. 5, the voltage is increased by Vlv1 corresponding to the error and applied to the pixel electrode PE. In this case, the pixel state is darker than the correct brightness.

  On the other hand, the voltage of the ramp signal RAMP2- sampled and held in the negative holding capacitor is the voltage indicated by Vm2 in FIG. 5, but the Vth of the transistor (PMOS transistor Tr4 in FIG. 3) in the source follower circuit on the negative polarity side. Is higher than the average value, as shown in FIG. 5, the voltage is increased by Vlv2 corresponding to the error and applied to the pixel electrode PE. In this case, the pixel state is brighter than the correct brightness. As described above, if there is an error in which the Vth of the transistor of the source follower circuit on the positive polarity side in each pixel and the Vth of the transistor of the source follower circuit on the negative polarity side deviate from the normal values, the correct brightness is obtained. The display of the shifted state is the same as in the normal state data reading described with reference to FIG.

  Here, the brightness Xp2 of the liquid crystal display element when the positive pixel electrode voltage shown in FIG. 5 is applied is expressed by the following equation.

Xp2 = fp × (Vp2−Vlv1) (3)
In the equation (3), fp is a function for calculating display brightness when voltage is applied, Vp2 is an input voltage of data in the inverted state of the positive side holding capacitor in the pixel, and Vlv1 is a positive side source follower of the pixel. It is the variation voltage of the circuit. Further, the brightness Xm2 of the liquid crystal display element when the negative polarity pixel electrode voltage shown in FIG. 5 is applied is expressed by the following equation.

Xm2 = fm × (Vm2 + Vlv2) (4)
In the equation (4), fm is a function for calculating display brightness when voltage is applied, Vm2 is an input voltage of data in the inverted state of the negative side holding capacitor in the pixel, and Vlv2 is a negative side source follower of the pixel. It is the variation voltage of the circuit.

  Next, referring back to FIG. In the liquid crystal panel drive element 12 of FIG. 2, normal state data and inverted state data are alternately supplied in units of one frame from the panel drive external drive circuit 11, and the positive ramp signal is supplied as described above. And the negative polarity ramp signal are converted into an analog signal voltage and written in the positive polarity holding capacitor and the negative polarity holding capacitor in each pixel. In FIG. 2, the normal state data of the next frame is being sequentially written from the top of the pixel portion 123 to each line in the downward direction in the inverted data writing portion already written in the pixel portion 123. Indicates the state. In FIG. 2, 126A represents a normal data writing portion in the middle of writing, and 126B represents an inverted data writing portion that has already been written to the pixel portion 123 and has not yet been overwritten.

  That is, the normal state data and the inverted state data are alternately switched and input every frame, but after the writing of the data for one frame to all the pixels is completed, the data for the next frame is completed. The data of the next frame is written to each pixel of the line while reading the data of the writing portion where writing has been completed halfway through the screen.

  After normal data or inverted data is written, the written data is read at high speed in a predetermined cycle (for example, a 2 kHz cycle). In this embodiment, as shown in FIGS. 4A and 4B, this reading is performed by combining the combination of the written data in units of frames and the common electrode voltage, as described above. There are types. In the present embodiment, reading is cyclically switched in units of one frame in the order of combination 1 → combination 2 → combination 3 → combination 4 → combination 1 →.

  In any of the above four types of combinations, the common electrode voltage is a positive common electrode voltage (Vcom1 + or Vcom2 +) and a negative common electrode voltage (Vcom1- or Vcom2-) with a period of 2 kHz during reading. It is switched alternately, but depending on whether it is normal state data or inverted state data to be read from the holding capacitor, and whether to read from the positive holding capacitor or the negative holding capacitor, that is, the above-mentioned It is necessary to select whether to read from the positive common electrode voltage or the negative common electrode voltage according to the four types of combinations.

  Therefore, in this embodiment, although not shown in FIG. 2, a circuit is used that generates a flag according to the shift state of the vertical shift register 124 and changes the selection of the positive and negative common electrode voltages. . FIG. 6 shows the relationship between the input data and the common electrode voltage. In FIG. 6A, “+ side” indicates a case where normal state data or inverted state data is read from the positive polarity holding capacitor, and “− side” indicates a case where the negative polarity holding capacitor is read. In FIG. 6B, “Low” indicates Vcom1 + or Vcom2− where the common electrode voltage is a low level side voltage, and “High” indicates Vcom1− or Vcom2 + where the common electrode voltage is a high level side voltage. Indicates.

  In this way, according to the present embodiment, since all four types of combinations are displayed in time series, the brightness X of the display screen is the average of the four types of combinations, and the expressions (1) to (4) ) Is expressed by the following equation.

X = (Xm + Xm2 + Xp + Xp2) / 4
= (Fm × (Vm1 + Vlv2 + Vm2−Vlv2)
+ Fp × (Vp1 + Vlv1 + Vp2−Vlv1) ) / 4
= (Fm × (Vm1 + Vm2) + fp × (Vp1 + Vp2) ) / 4 (5)
Here, in the case of the same pixel, fm = fp = f, Vm1 = Vm2 = Vp1 = Vp2 = V
Therefore, the equation (5) is expressed by the following equation.

X = f × V (6)
Therefore, according to the present embodiment, as can be seen from the equation (6), the brightness X can be set to a brightness in which variation in Vth of the transistors of the source follower circuit for each pixel is suppressed. However, since the pixel variation slightly differs depending on the signal voltage, it cannot be completely canceled out, but can be suppressed.

  As a result, according to the present embodiment, FPN caused by variations in Vth of transistors of the source follower circuit for each pixel can be reduced, and display quality can be improved. Further, according to the present embodiment, a certain degree of suppression can be expected even when an incorrect voltage such as a bright spot or a black spot is applied to the pixel electrode in the same manner as pixel variations.

DESCRIPTION OF SYMBOLS 10 Liquid crystal display device 11 Panel drive external drive circuit 12 Liquid crystal panel drive element 121 Horizontal shift register and comparator 122 Horizontal drive circuit (video switch etc.)
123 Pixel portion 124 Vertical shift register 125 Pixel selection circuit 126A Normal data writing portion 126B Inverted data writing portion Tr1, Tr2 Pixel selection NMOS transistor Tr3, Tr4 Source follower PMOS transistor Tr5, Tr6 Switching PMOS transistor Tr7 constant PMOS transistor for current load LC Liquid crystal display element PE Pixel electrode CE Common electrode LCM Liquid crystal layer

Claims (2)

Each of a plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of row scanning lines intersect each other with two data lines as one set,
A display element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other;
The reference supplied via one data line of the two data lines when a pixel value of input digital data coincides with reference gradation data whose level changes monotonically in a horizontal scanning cycle. First sampling and holding means for sampling the voltage of the positive polarity ramp signal that monotonously increases in level in synchronization with the gradation data and holding it in the first holding capacitor for a certain period;
When the pixel value of the input digital data coincides with the reference gradation data, the monotone is synchronized with the reference gradation data supplied through the other data line of the set of two data lines. Sampling and holding means for sampling the voltage of the negative polarity ramp signal having a polarity opposite to that of the positive polarity ramp signal and holding the same in the second holding capacity for a certain period;
The holding voltages of the first holding capacitor and the second holding capacitor are alternately read at a predetermined cycle shorter than the vertical scanning cycle, and the voltage read from the first holding capacitor is a first source follower circuit. A voltage read from the second storage capacitor is applied to the pixel electrode through a second source follower circuit ;
And data of the normal state of the same data value and the display should do digital data, and the data of the inverted an inverted state of the data values of the digital data to be the display as said input digital data by switching alternately frame by frame Data input means,
At the time of reading out the pixels in which the positive ramp signal and the negative ramp signal corresponding to the pixel value of the data in the normal state are read by the holding voltage reading means, the first and second holding capacitors are read . A first common electrode voltage of a first potential is applied to the common electrode when a first holding voltage of the positive-polarity ramp signal read from one holding capacitor is applied to the pixel electrode, and the second When the second holding voltage of the negative ramp signal read from the holding capacitor is applied to the pixel electrode, a second common electrode voltage having a second potential higher than the first potential is applied to the common electrode. When the pixel having the positive ramp signal and the negative ramp signal corresponding to the pixel value of the data in the inverted state held in the first and second holding capacitors is read, the first holding is performed. Yong A third common electrode voltage of the second potential is applied to the common electrode to the time of application to the pixel electrode of the third holding voltage of the positive polarity ramp signal read from, and, from the second storage capacitor Common electrode voltage input means for applying a fourth common electrode voltage of the first potential to the common electrode when a fourth holding voltage of the read negative ramp signal is applied to the pixel electrode;
The first holding capacitor in which the positive polarity ramp signal corresponding to the pixel value of the normal state data is held, and the first holding capacitor in which the negative polarity ramp signal corresponding to the pixel value of the normal state data is held. The first holding capacitor in which the positive polarity ramp signal corresponding to the pixel value of the data in the inverted state is held alternately by switching the reading order with the two holding capacitors in units of the normal state data input period. And a reading order switching for alternately switching the reading order of the second holding capacitor in which the negative ramp signal corresponding to the pixel value of the inverted data is held in units of the input period of the inverted data Means and
And the brightness of the display screen by the plurality of pixels is averaged according to the first to fourth holding voltages applied to the pixel electrodes through the first or second source follower circuit. A liquid crystal display device. Each of a plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of row scanning lines intersect each other with two data lines as one set,
A display element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other;
The reference supplied via one data line of the two data lines when a pixel value of input digital data coincides with reference gradation data whose level changes monotonically in a horizontal scanning cycle. First sampling and holding means for sampling the voltage of the positive polarity ramp signal that monotonously increases in level in synchronization with the gradation data and holding it in the first holding capacitor for a certain period;
When the pixel value of the input digital data coincides with the reference gradation data, the monotone is synchronized with the reference gradation data supplied through the other data line of the set of two data lines. Sampling and holding means for sampling the voltage of the negative polarity ramp signal having a polarity opposite to that of the positive polarity ramp signal and holding the same in the second holding capacity for a certain period;
The holding voltages of the first holding capacitor and the second holding capacitor are alternately read at a predetermined cycle shorter than the vertical scanning cycle, and the voltage read from the first holding capacitor is a first source follower circuit. A voltage read from the second storage capacitor is applied to the pixel electrode through a second source follower circuit ;
For a liquid crystal display device comprising
The normal data having the same data value as the digital data to be displayed and the inverted data obtained by inverting the data value of the digital data to be displayed are alternately switched in units of one frame as the input digital data. A data input step for supplying the pixel;
At the time of reading out the pixels in which the positive ramp signal and the negative ramp signal corresponding to the pixel value of the data in the normal state are read by the holding voltage reading means, the first and second holding capacitors are read . A first common electrode voltage of a first potential is applied to the common electrode when a first holding voltage of the positive-polarity ramp signal read from one holding capacitor is applied to the pixel electrode, and the second When the second holding voltage of the negative ramp signal read from the holding capacitor is applied to the pixel electrode, a second common electrode voltage having a second potential higher than the first potential is applied to the common electrode. First and second common electrode voltage input steps to be applied to
When reading out the pixels in which the positive ramp signal and the negative ramp signal corresponding to the pixel value of the data in the inverted state are held in the first and second holding capacitors, they are read from the first holding capacitor. The third common electrode voltage having a second potential is applied to the common electrode when the third holding voltage of the positive-polarity ramp signal is applied to the pixel electrode, and is read from the second holding capacitor. Third and fourth common electrode voltage input steps for applying a fourth common electrode voltage of the first potential to the common electrode when a fourth holding voltage of a negative ramp signal is applied to the pixel electrode;
The first holding capacitor in which the positive polarity ramp signal corresponding to the pixel value of the normal state data is held, and the first holding capacitor in which the negative polarity ramp signal corresponding to the pixel value of the normal state data is held. A first reading order switching step of alternately switching the reading order with respect to the holding capacity of 2 in units of the input period of the data in the normal state;
The first holding capacitor in which the positive ramp signal corresponding to the pixel value of the inverted data is held, and the first holding capacitor in which the negative ramp signal corresponding to the pixel value of the inverted data is held. A second reading order switching step of alternately switching the reading order with respect to the holding capacity of 2 in units of the input period of the inverted data;
And the brightness of the display screen by the plurality of pixels is determined by averaging the brightness according to the first to fourth holding voltages applied to the pixel electrode through the first or second source follower circuit. A method for driving a liquid crystal display device.

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