JP2012177822A - Liquid crystal display element and driving method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow image display of high quality by reducing image noise of so-called a misadjusted black level which is caused by distorting a ramp signal.SOLUTION: A ramp signal for positive polarity RAMP+ from a video switch for positive polarity omitted in Figure is supplied to a data line for positive polarity Di+, and a ramp signal for negative polarity RAMP- from a video switch for negative polarity omitted in Figure is supplied to a data line for negative polarity Di-. A switch SWi is provided between the data line for positive polarity Di+ and the data line for negative polarity Di- and is turned on once at timing immediately before simultaneous turning-on of two video switches in an i-th column, whereby the switch SWi has a function of neutralizing positive voltage charge and negative voltage charge charged in the data line for positive polarity Di+ and the data line for negative polarity Di-. Within a short period between the end of a ramp signal period and the start of a next horizontal scanning period, the switch SWi is turned on to cause a short-circuit between the data line for positive polarity Di+ and the data line for negative polarity Di-.

Description

  The present invention relates to a liquid crystal display device and a driving method thereof, and in particular, a positive video signal and a negative video signal obtained by DA conversion in each pixel are separately sampled and held in two holding capacitors and then held. The present invention relates to a liquid crystal display element that is alternately driven by applying a voltage to pixel electrodes and a driving method thereof.

  In recent years, a liquid crystal display element of LCOS (Liquid Crystal on Silicon) type is often used as a central part for projecting an image in a projector apparatus or a projection television. This LCOS liquid crystal display element has a structure in which a transparent electrode, a liquid crystal layer, a reflective electrode arranged in a matrix, a liquid crystal display element in which a liquid crystal driving circuit is formed on a silicon substrate, and the like overlap. In this liquid crystal display element, the digitization of the external circuit of the liquid crystal driving circuit is progressing with the progress of digital signal processing technology. Accordingly, it is becoming more convenient for the entire system to input a digital signal as a video signal to the liquid crystal driving circuit.

  Therefore, the applicant of the present application previously puts a pixel at each intersection of a plurality of data lines each having two data lines (column signal lines) and a plurality of gate lines (row scanning lines). The positive polarity video signal and the negative polarity video signal obtained by DA conversion from the digital video signal in each pixel are sampled and held in two holding capacitors, and then the holding voltages are alternately scanned vertically. A liquid crystal display device has been proposed in which a liquid crystal display element is AC-driven by alternately applying to a pixel electrode at a predetermined frequency higher than the frequency (see, for example, Patent Document 1).

  The liquid crystal display device described in Patent Document 1 includes a positive polarity video switch connected to one of the two data lines of each set and a negative polarity video switch connected to the other, and the positive polarity of each set. The video switch for sex and the video switch for negative polarity are turned on simultaneously at the start of the horizontal scanning period, and the pixel values of the video signal for positive polarity and the video signal for negative polarity obtained by DA conversion from the digital video signal are set. The positive polarity video switch and the negative polarity video switch provided corresponding to the pixel are turned off at the same time. Therefore, the timing of turning off the positive polarity video switch and the negative polarity video switch of each set differs depending on the set of the video signal and may be the same.

  Here, the DA conversion is performed as follows. A positive polarity lamp having a polarity of one horizontal scanning period (1H) that has a reverse polarity and monotonously changes from one level of the maximum gradation (white level) and the minimum gradation (black level) to the other level. The signal and the negative ramp signal are separately supplied to the positive video switch and the negative video switch. On the other hand, the 1H period gradation count value from the counter that counts the clock signal synchronized with the positive polarity ramp signal and the negative polarity ramp signal, respectively, and the pixel value of the digital video signal for each pixel unit of one line When the two values match, the comparator outputs a coincidence pulse to turn off the positive polarity video switch and the negative polarity video switch corresponding to the pixel. Ramp signal for negative polarity and ramp signal for negative polarity are sampled and held separately in two holding capacitors of the corresponding pixel via two data lines connected separately to the video switch for positive polarity and the video switch for negative polarity Let Here, the positive polarity ramp signal and the negative polarity ramp signal immediately before the video switch is turned off correspond to the positive polarity video signal and the negative polarity video signal which have been DA-converted.

  In the liquid crystal display device described in Patent Document 1, a positive video signal and a negative video signal are sampled and held in two holding capacitors simultaneously in parallel, and the positive and negative voltages held in the holding capacitors are expressed as follows. By performing a switching operation that alternately applies to the pixel electrode at a frequency higher than one vertical scanning frequency before the video signal of the frame is written, the AC drive frequency of the liquid crystal display element can be positive or negative regardless of the vertical scanning frequency. It can be set freely according to the driving voltage switching period, and the liquid crystal driving frequency can be dramatically increased compared to conventional liquid crystal display elements, thereby preventing deterioration in display quality such as reliability, stability, and stains. The features of can be obtained.

JP 2009-223289 A

  However, in the above conventional liquid crystal display device, as described above, every set of positive polarity video switches and negative polarity video switches is turned on at the start of each horizontal scanning period, and each set of positive polarity video switches is turned on. Gradually charge and discharge the parasitic capacitance of the first gate line connected to the switch and the second gate line connected to the video switch for negative polarity, and the comparator performs gradation count value and digital video for each pixel. The pixel value of the signal is compared, and the video switch is turned off at the timing when both coincide with each other, whereby the positive and negative ramp signal voltages are written in the holding capacitor in the pixel.

  For this reason, when the digital video signal has a high gradation, that is, when the gradation count value is large, the voltage written in the previous line remains on the data line, and at the moment when the video switch is turned on next time, the data line The current flows back to the ramp signal input side through the video switch, and the original ramp signal is distorted.

  This will be described with reference to FIG. In FIG. 5A, one video switch is turned on at the start time t1 of the horizontal scanning period, and the video switch is turned off when the coincidence pulse is input at time t2, and the next horizontal scanning period starts. It shows that it is turned on again at time t3. Thus, the positive polarity shown in FIG. 5B is passed through the video switch having the on / off timing shown in FIG. 5A and another video switch of the same set that is turned on / off in synchronization with the video switch. The ramp signal and the negative polarity lamp shown in FIG. 5C hold the voltage at the time t2 as shown by the dotted line on two data lines of the same set.

  Subsequently, when the video switch connected to the same data line enters the operation of the next line and is turned on at the start time t3 of the next horizontal scanning period, it is held as shown by the dotted lines in FIGS. The voltage of the data line thus made flows backward to the ramp signal input side through the video switch, and at time t3, the voltage of the positive polarity ramp signal temporarily rises, and the voltage of the negative polarity ramp signal drops. As described above, if the ramp signal immediately after the video switch is turned on is distorted, there is a time during which the original ramp signal voltage value when the video switch is turned off cannot be supplied to the data line (X period in FIG. 5). A phenomenon occurs in which the gradation indicated by the ramp signal voltage is different from the pixel value of the digital video signal. This phenomenon is particularly pronounced when each pixel of a line has high gradation and each pixel of the next line has low gradation, and is called so-called “black floating” in which the low gradation line floats slightly brightly. Generate image noise.

  The present invention has been made in view of the above points, and a liquid crystal display element capable of reducing so-called “black floating” image noise caused by distorting a lamp signal and displaying a high-quality image, and a driving method thereof The purpose is to provide.

In order to achieve the above object, the liquid crystal display element of the first invention is provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other. Each of the plurality of pixels
A display element in which a liquid crystal layer is sandwiched between an opposing pixel electrode and a common electrode, a pixel value of input image data, and a gradation value indicated by reference gradation data whose value changes monotonically in a horizontal scanning cycle When they match, the maximum gradation value is obtained from the voltage indicating the minimum gradation value within the horizontal scanning period in synchronization with the reference gradation data supplied via one data line of the set of two data lines. First sampling and holding means for sampling the voltage of the positive polarity ramp signal that monotonically increases to the indicated voltage and holding it in the first holding capacitor for a certain period, the pixel value of the input image data and the reference gradation data When the grayscale value indicated by is matched, the minimum grayscale value is indicated within the horizontal scanning period in synchronization with the reference grayscale data supplied via the other data line of the set of two data lines. Monotonically from the voltage to the voltage indicating the maximum gradation value. A second sampling and holding means for sampling the voltage of the negative polarity ramp signal having a polarity opposite to that of the positive polarity ramp signal and holding the voltage in the second holding capacitance for a certain period of time; Holding voltage reading means for alternately applying the first holding voltage and the second holding voltage of the second holding capacitor to the pixel electrode at a predetermined cycle shorter than the vertical scanning cycle;
The next horizontal scanning period from the end of the ramp signal period in which the positive polarity ramp signal and the negative polarity ramp signal reach the voltage indicating the maximum gradation value within the horizontal scanning period and then return to the voltage indicating the minimum gradation value. The switch means for short-circuiting between a set of two data lines within a period up to the start point of the above is provided in units of two data lines.

In order to achieve the above object, a liquid crystal display element according to a second aspect of the invention includes a display element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other, and a pixel value of input image data. Is synchronized with the reference gradation data supplied via one of the two data lines when the gradation value indicated by the reference gradation data whose value changes in the horizontal scanning period coincides with the reference gradation data. Then, the voltage of the positive polarity ramp signal that monotonically increases from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value within the horizontal scanning period is sampled and held in the first holding capacitor for a certain period. When the first sampling and holding means matches the pixel value of the input image data and the gradation value indicated by the reference gradation data, the first sampling and holding means is supplied via the other data line of the set of two data lines. Within the horizontal scanning period in synchronization with the reference gradation data Sampling the voltage of the negative polarity ramp signal having a polarity opposite to that of the positive polarity ramp signal, which monotonically decreases from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value, and holds the second for a certain period The second sampling and holding means held in the capacitor, the first holding voltage of the first holding capacitor, and the second holding voltage of the second holding capacitor alternately with a predetermined cycle shorter than the vertical scanning cycle. Holding voltage reading means for applying to the pixel electrode,
The next horizontal scanning period from the end of the ramp signal period in which the positive polarity ramp signal and the negative polarity ramp signal reach the voltage indicating the maximum gradation value within the horizontal scanning period and then return to the voltage indicating the minimum gradation value. In the period up to the start time of the first, the potential of one data line of the set of two data lines is connected to the first voltage source of the voltage indicating the minimum gradation value of the positive polarity ramp signal. And a second switch means for connecting the potential of the other data line to the second voltage source of the voltage indicating the minimum gradation value of the negative polarity ramp signal. It is characterized by having.

In order to achieve the above object, a driving method of a liquid crystal display element according to a third aspect of the present invention includes a display element in which a liquid crystal layer is sandwiched between an opposing pixel electrode and a common electrode, and a pixel value of input image data. And a reference gradation supplied via one data line of a set of two data lines when the gradation value indicated by the reference gradation data whose value monotonously changes in the horizontal scanning cycle matches. The voltage of the ramp signal for positive polarity that monotonically increases from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value within the horizontal scanning period in synchronization with the data is sampled for the first holding capacitor for a certain period. When the pixel value of the input image data and the gradation value indicated by the reference gradation data match, the first sampling and holding means held in the second image line are connected via the other data line. Horizontally synchronized with the reference gradation data supplied Sampling the voltage of the negative polarity ramp signal of the opposite polarity to the positive polarity ramp signal, which decreases monotonically from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value within the inspection period, and for a certain period The second sampling and holding means held in the second holding capacitor, the first holding voltage of the first holding capacitor, and the second holding voltage of the second holding capacitor are predetermined shorter than the vertical scanning cycle. For a liquid crystal display element comprising holding voltage reading means that is alternately applied to the pixel electrode at a period of
The next horizontal scanning period from the end of the ramp signal period in which the positive polarity ramp signal and the negative polarity ramp signal reach the voltage indicating the maximum gradation value within the horizontal scanning period and then return to the voltage indicating the minimum gradation value. The method includes a short-circuiting step of short-circuiting between the two data lines of each group for each group within a period up to the start time of each.

Furthermore, in order to achieve the above object, a driving method of a liquid crystal display element according to a fourth aspect of the present invention includes a display element in which a liquid crystal layer is sandwiched between an opposing pixel electrode and a common electrode, and a pixel value of input image data. And a reference gradation supplied via one data line of a set of two data lines when the gradation value indicated by the reference gradation data whose value monotonously changes in the horizontal scanning cycle matches. The voltage of the ramp signal for positive polarity that monotonically increases from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value within the horizontal scanning period in synchronization with the data is sampled for the first holding capacitor for a certain period. When the pixel value of the input image data and the gradation value indicated by the reference gradation data match, the first sampling and holding means held in the second image line are connected via the other data line. Horizontally synchronized with the reference gradation data supplied Sampling the voltage of the negative polarity ramp signal of the opposite polarity to the positive polarity ramp signal, which decreases monotonically from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value within the inspection period, and for a certain period The second sampling and holding means held in the second holding capacitor, the first holding voltage of the first holding capacitor, and the second holding voltage of the second holding capacitor are predetermined shorter than the vertical scanning cycle. For a liquid crystal display element comprising holding voltage reading means that is alternately applied to the pixel electrode at a period of
The next horizontal scanning period from the end of the ramp signal period in which the positive polarity ramp signal and the negative polarity ramp signal reach the voltage indicating the maximum gradation value within the horizontal scanning period and then return to the voltage indicating the minimum gradation value. In the period up to the start time of the first, the potential of one of the two data lines in each set is connected to the first voltage source of the voltage indicating the minimum gradation value of the positive polarity ramp signal. At the same time as the connecting step and the first connecting step, the potential of the other data line of the two data lines in each set is used as the second voltage source of the voltage indicating the minimum gradation value of the negative polarity ramp signal. And a second connection step of connecting.

  According to the present invention, the gray scale voltage of the ramp signal written to the data line in the previous line flows backward to the ramp signal input side at the start of the horizontal scanning period of the next line, which is caused by distorting the ramp signal. Reduces “black floating” image noise and enables high-quality image display.

It is a block diagram of the liquid crystal display device which has 1st Embodiment of the liquid crystal display element of this invention. It is a circuit diagram of the principal part of 1st Embodiment of the liquid crystal display element of this invention. 3 is a timing chart for explaining the operation of FIGS. 1 and 2. It is a circuit diagram of the principal part of 2nd Embodiment of the liquid crystal display element of this invention. It is a figure explaining generation | occurrence | production of the black floating noise in the conventional liquid crystal display element.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram of a liquid crystal display device having a first embodiment of a liquid crystal display element according to the present invention. The liquid crystal display device 100 includes a shift register and comparator 101 to which image data that is a digital video signal is supplied, a horizontal drive circuit 102 including a video switch, and a total of n sets (n is 2 or more). (Natural number) data lines (column signal lines) Di +, Di- (i = 1, 2, 3,..., N) and a total of m (m is a natural number of 2 or more) gate lines (row scanning lines) ) It is composed of a total of m × n pixels 103 _{11 to} 103 _mn arranged in a matrix at each intersection with G 1 to G m, a vertical drive circuit 14, and n switches SW 1 to SWn. This embodiment is characterized in that n noise reducing switches SW1 to SWn are provided.

  The shift register and comparator 101 holds the input image data for one line by the shift register and then supplies it to the comparator. N shift registers and comparators in the comparator 101 are provided for each column corresponding to n sets of data lines. The n comparators are commonly supplied with reference gradation data (gradation count value) that changes stepwise for every predetermined period within the horizontal scanning period from the minimum gradation value to the maximum gradation value, for example. On the other hand, the image data held by the shift register is supplied for each pixel unit of n pixels of one line and compared with each other. When the two match, a coincidence pulse is provided correspondingly in the horizontal drive circuit 102. To the video switch.

  The horizontal drive circuit 102 includes a positive video switch connected to a positive data line Di + and a negative data line D− out of a set of two data lines (column signal lines) Di + and Di−. A total of n sets of connected video switches for negative polarity are provided for each set of data lines, and coincide with comparators provided correspondingly among the n comparators in the shift register and comparator 101 described above. In this configuration, pulses are supplied.

  In addition, of the video switch for positive polarity and the video switch for negative polarity in each set in the horizontal drive circuit 102, the video switch for positive polarity has a maximum gradation from the minimum gradation value (black level) of video within 1H. A positive-polarity ramp signal RAMP +, which is a periodic sweep signal whose level monotonously increases to a value (white level), is supplied. On the other hand, the video switch for negative polarity has an inversion relation with respect to the positive polarity ramp signal RAMP + with respect to a predetermined potential, and the level varies from the minimum gradation value (black level) to the maximum gradation value (white level) within 1H. A negative ramp signal RAMP− which is a monotonically decreasing periodic sweep signal is supplied. The positive polarity ramp signal RAMP + and the negative polarity ramp signal RAMP- are synchronized with each other in the horizontal scanning period of the input image data and the clock supplied to the counter for generating the grayscale count value.

The vertical drive circuit 104, among the pixel portion composed of pixels 103 ₁₁ 10 @ 2 to 10 @ 3 _mn, each line one horizontal scanning period (1H) rows each to the connected gate line G1~Gm to n pixels (lines) A selection signal is supplied to select pixels in each line in order from top to bottom.

The switch SW1~SWn is in each set units corresponding to the n sets of data lines, between the pixel portion and the horizontal driving circuit 102 comprising pixels 103 ₁₁ ~103 _mn, 2 pieces of positive polarity in each set The data line for use and the data line for negative polarity are provided so as to be short-circuited or opened. That is, the switches SW1 to SWn are provided in common for m pixels in each column of the pixel portion.

FIG. 2 shows a circuit diagram of a main part of the first embodiment of the liquid crystal display element according to the present invention. FIG. 2 shows an embodiment in which one pixel 103 _{ji in} j row and i column of the pixel portion and one switch SWi provided between two data lines Di + and Di− in the i set. The main part of the liquid crystal display element is shown.

The pixel 103 _ji has pixel selection transistors Q1 and Q2 each having a gate connected to the gate line Gj, one end connected to each source of the pixel selection transistors Q1 and Q2, and the other end connected in common to the common electrode line 7. Buffer amplifiers A1 and A2 whose input ends are connected to the connection point between the storage capacitors (capacitors) C1 and C2, the pixel selection transistor Q1 and the storage capacitor C1, and the connection point between the pixel selection transistor Q2 and the storage capacitor C2, respectively. And switching switches S1 and S2 having one ends connected to the output ends of the buffer amplifiers A1 and A2, and a liquid crystal connected between the common connection point at each other end of the switching switches S1 and S2 and the common electrode line 7. The driving storage capacitor C3 and the pixel electrode 4 having light reflectivity and conductivity are included. The pixel electrode 4 is disposed so as to be spaced apart from a common electrode having light transmittance and conductivity (not shown), and a liquid crystal layer is sandwiched therebetween to form a display element having a known configuration. Note that the storage capacitor C3 can be omitted.

  The drains of the pixel selection transistors Q1 and Q2 are separately connected to a positive data line Di + and a negative data line Di-. A positive switch and a negative switch voltage are held in the positive polarity data line Di + and the negative polarity data line Di-, respectively, and the changeover switch is set at an arbitrary cycle during one frame period until the video signal of the next frame is written. By switching the positive and negative drive voltages by S1 and S2, it becomes possible to perform AC drive of the liquid crystal at high speed. A positive polarity ramp signal RAMP + from a positive polarity video switch (not shown) in the horizontal driving circuit 102 is supplied to the positive polarity data line Di +, and a negative polarity data line Di− is indicated in the horizontal driving circuit 102. The negative polarity ramp signal RAMP− is supplied from the negative polarity video switch.

  The switch SWi is provided between the positive polarity data line Di + and the negative polarity data line Di−, and is turned on only once at the timing immediately before the two video switches in the i-th column are turned on simultaneously. The voltage charged in the sex data line Di + and the negative data line Di- has a function of neutralizing positive and negative voltages.

  Next, the operation of the liquid crystal display device of FIG. 1 and the circuit of the liquid crystal display element of the present embodiment of FIG. 2 will be described with reference to the timing chart of FIG.

  First, all the n video switches in the horizontal drive circuit 102 are simultaneously turned on at the start time t11 of the horizontal scanning period. FIG. 5A shows the on / off timing of the i-th positive polarity video switch or the negative polarity video switch among the n sets of video switches, and is turned on at time t11 as schematically shown at a high level. The The on / off timing of the positive video switch and the negative video switch in the same group is the same.

  When the video switch in the i-th column is turned on, the level of the positive polarity data line Di + is changed from the minimum gradation value (black level) to the maximum gradation value (white level) within 1H shown in FIG. A monotonically increasing positive polarity ramp signal RAMP + is supplied, and the negative polarity data line Di- is supplied from the minimum gradation value (black level) to the maximum gradation value within 1H shown in FIG. A ramp signal RAMP− for negative polarity whose level monotonously decreases to (white level) is supplied. As shown in FIGS. 3C and 3D, the positive ramp signal RAMP + and the negative ramp signal RAMP- are 1H which returns to the original level at time t11 after a predetermined period of time within 1H. It is a periodic waveform.

  On the other hand, as described above, the comparator in the shift register 101 compares the image data with the gradation count value, and the i-th pixel value of the first line of the j-th line in the image data is the gradation counter value. And the video switch in the i-th column provided corresponding to the pixel in the i-th column by the coincidence pulse output from the comparator at the time t12 is schematically illustrated at a low level in FIG. As shown, it is turned off at time t12. As a result, the voltage V1 at time t12 of the positive polarity ramp signal RAMP + shown in FIG. 3C supplied to the positive polarity data line Di + is sampled by the pixel selection transistor Q1 and held in the holding capacitor C1. . At the same time, the voltage V2 at time t12 of the negative ramp signal RAMP- shown in FIG. 3D supplied to the negative data line Di- is sampled by the pixel selection transistor Q2 and stored in the holding capacitor C2. Retained. The voltages V1 and V2 are analog voltages obtained by DA converting image data. The voltage V1 is also held in the parasitic capacitance of the positive data line Di + and the voltage V2 is also held in the parasitic capacitance of the negative data line Di− (the threshold voltages of the transistors Q1 and Q2 are ignored for convenience of explanation). To do).

  Since the switches S1 and S2 are alternately turned on / off at a frequency higher than the vertical scanning frequency, the voltage V1 held in the holding capacitor C1 is applied to the pixel electrode 4 during the on period of the switch S1, and the holding capacitor C2 The voltage V2 held at is applied to the pixel electrode 4 during the ON period of the switch S2, so that the liquid crystal display element is AC driven at a high frequency. Although not shown in FIG. 2, a common electrode voltage is applied to the common electrode (transparent electrode) disposed to face the pixel electrode 4. The common electrode voltage is low during the period when the voltage held in the storage capacitor C1 is applied to the pixel electrode, and is high during the period when the voltage held in the storage capacitor C2 is applied to the pixel electrode. Switching is performed in synchronization with switching of the holding voltage. As a result, the voltage application direction to the liquid crystal layer is reversed, but when the voltages V1 and V2 of the same gradation are applied, the voltage to the liquid crystal layer has the same value and the same brightness. .

  Subsequently, the positive polarity ramp signal RAMP + and the negative polarity ramp signal RAMP- reach the level indicating the maximum gradation value and then return to the level indicating the original minimum gradation value (that is, the ramp signal period). 1) and a time period from time t <b> 13 to time t <b> 14 within a short period from the start time t <b> 15 of the next horizontal scanning period to the switches SW <b> 1 to SW <b> 1 in FIG. SWn is turned on simultaneously. Accordingly, the switch SWi is also controlled to be turned on during the period from the time t13 to the time t14 as schematically shown at a high level in FIG.

  When the switch SWi is turned on, the positive polarity data line Di + and the negative polarity data line Di- are short-circuited, so that the positive polarity data line Di + is connected to the positive polarity data line Di + as shown by the dotted lines in FIGS. The positive polarity data line Di + and the negative polarity data are neutralized to a voltage substantially equal to the intermediate voltage (V1 + V2) / 2 between the held voltage V1 and the negative polarity data line Di−. Held on line Di-.

  The potentials of the positive polarity data line Di + and the negative polarity data line Di- are maintained at the intermediate voltage even when the switch SWi is turned off at time t14, and at the start time t15 of the next horizontal scanning period. When all the video switches are turned on simultaneously, the potentials of the positive polarity ramp signal RAMP + and the negative polarity ramp signal RAMP- are restored.

  At this time, as shown by dotted lines in FIGS. 5C and 5D, the ramp signal is passed through the video switch in which the intermediate voltage held in the positive data line Di + and the negative data line Di− is turned on. As a result, the positive polarity ramp signal RAMP + temporarily rises, and the negative polarity ramp signal RAMP- voltage rises temporarily.

  However, in the present embodiment, at the time t15 when the next horizontal scanning period starts, the positive polarity data line Di + and the negative polarity as shown by the dotted lines in FIGS. 5C and 5D by turning on the switch SWi. Since the voltage held on the data line Di- has returned to the intermediate voltage, the voltage level of the positive polarity ramp signal RAMP + and the voltage level of the negative polarity ramp signal RAMP- are raised. It is almost half.

  Accordingly, a period during which the so-called black floating image noise is generated, in which the deviation from the desired gradation occurs in the input image data due to distortion in the ramp signal, as indicated by Y in FIG. 3 in the present embodiment. In addition, since it can be shorter than the conventional period X and the waveform distortion of the ramp signals RAMP + and RAMP− can be suppressed to a small extent, according to the present embodiment, it is possible to reduce the floating image noise. it can.

  Further, the brighter the gradation written in the previous line, that is, the higher the sampled voltage in the positive polarity ramp signal RAMP +, and the lower the sampled voltage in the negative polarity ramp signal RAMP-, the more the black floating noise becomes. It gets bigger. Conversely, when the gradation written in the previous line is dark, the black floating noise is reduced. As described above, the change in the black floating degree of the next line due to the gradation written in the previous line also causes image noise. However, in the present embodiment, the switches SWi to SWn neutralize the potential between the two data lines Di + and Di- in each group, so that the switches do not depend on the gradation of the previous line. Since the potentials of the two data lines Di + and Di− in each set after turning on SWi to SWn are always the same value, there is also an effect that a stable high quality image can be obtained.

(Second Embodiment)
Next, a second embodiment of the liquid crystal display element according to the present invention will be described. The basic configuration of a liquid crystal display device including the liquid crystal display element of the present embodiment is the same as that shown in FIG. In the liquid crystal display element of the present embodiment, instead of the switches SW1 to SWn, a first switch is provided for each positive polarity data line Di + and a second polarity for the negative polarity data line Di−. The switch is provided. That is, in the present embodiment, two switches are provided separately for each pair of two data lines. Therefore, although this embodiment has a larger number of switches than the first embodiment, the desired effect can be obtained.

  FIG. 4 shows a circuit diagram of a main part of the second embodiment of the liquid crystal display element according to the present invention. In the figure, the same components as those in FIG. In FIG. 4, the first switch SWA is connected between the positive polarity data line Di + and the voltage source having the GND potential, and the second switch SWB is connected between the negative polarity data line Di− and the voltage source having the potential VDD. Connected between. The switches SWA and SWB are provided in common for m pixels in each column of the pixel portion.

  The above switches SWA and SWB operate in conjunction with each other, and are turned on only once within a period after the end of the ramp signal period, immediately before the two video switches in the i-th column are turned on at the same time. That is, the switches SWA and SWB are simultaneously turned on only during a short period from the end time of the ramp signal period in each horizontal scanning period to the time when the next horizontal scanning period starts.

  For example, if the switch SWA is turned on during the period from time t13 to time t14 shown in FIG. 3, the potential of the positive polarity data line Di + is equal to the original positive polarity ramp signal RAMP + when the video switch is turned on. When connected to a voltage source of GND potential indicating the minimum gradation value and the switch SWB is turned on, the potential of the negative polarity data line Di− is the minimum level of the original negative polarity ramp signal RAMP− when the video switch is turned on. It is connected to a voltage source of VDD potential indicating the adjustment value.

  However, in this embodiment, even if the switches SWA and SWB are actually turned on at time t13, the potential of the positive polarity data line Di + does not immediately become the GND potential, but gradually becomes the GND potential according to a certain time constant. And immediately after time t15, the potential becomes GND. Similarly, the potential of the negative polarity data line Di− does not immediately become VDD, but gradually rises toward the VDD potential according to a certain time constant, and becomes VDD potential immediately after time t15. Therefore, in the present embodiment, the dependency on the gradation of the previous line remains slightly, but as in the first embodiment, the period during which so-called black floating image noise is generated can be made shorter than before. As a result, it is possible to reduce the image noise of floating black.

100 Liquid crystal display device 101 Register and comparator 102 Horizontal drive circuit (video switch, etc.)
103 _{11 to} 103 _mn pixels 104 Vertical drive circuit SW1 to SWn, SWA, SWB Noise reduction switch Di + Data line for positive polarity (column signal line)
Di- Data line for negative polarity (column signal line)
G1 to Gm gate lines (row scanning lines)
Q1, Q2 Pixel selection transistor C1, C2, C3 Retention capacitance (capacitor)
A1, A2 Buffer amplifier S1, S2 selector switch

Claims (4)

Each of a plurality of pixels provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other with a set of two data lines,
A display element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other;
When the pixel value of the input image data coincides with the gradation value indicated by the reference gradation data whose value changes monotonously in the horizontal scanning cycle, it passes through one data line of the set of two data lines. Sampling the voltage of the positive polarity ramp signal that monotonically increases from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value within the horizontal scanning period in synchronization with the reference gradation data supplied First sampling and holding means for holding in the first holding capacity for a certain period of time;
When the pixel value of the input image data matches the gradation value indicated by the reference gradation data, the reference gradation data supplied via the other data line of the set of two data lines The voltage of the negative polarity ramp signal having a polarity opposite to that of the positive polarity ramp signal, monotonically decreasing in level from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value within the horizontal scanning period. Sampling and holding means for sampling and holding in the second holding capacitor for a certain period;
Holding voltage reading means for alternately applying the first holding voltage of the first holding capacitor and the second holding voltage of the second holding capacitor to the pixel electrode at a predetermined cycle shorter than the vertical scanning cycle. And
The positive ramp signal and the negative ramp signal reach the voltage indicating the maximum gradation value within a horizontal scanning period and then return to the voltage indicating the minimum gradation value. A liquid crystal display element comprising switch means for short-circuiting a pair of the two data lines in a unit of the two data lines within a period up to a start time of a horizontal scanning period. Each of a plurality of pixels provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other with a set of two data lines,
A display element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other;
When the pixel value of the input image data coincides with the gradation value indicated by the reference gradation data whose value changes monotonously in the horizontal scanning cycle, it passes through one data line of the set of two data lines. Sampling the voltage of the positive polarity ramp signal that monotonically increases from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value within the horizontal scanning period in synchronization with the reference gradation data supplied First sampling and holding means for holding in the first holding capacity for a certain period of time;
When the pixel value of the input image data matches the gradation value indicated by the reference gradation data, the reference gradation data supplied via the other data line of the set of two data lines The voltage of the negative polarity ramp signal having a polarity opposite to that of the positive polarity ramp signal, monotonically decreasing in level from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value within the horizontal scanning period. Sampling and holding means for sampling and holding in the second holding capacitor for a certain period;
Holding voltage reading means for alternately applying the first holding voltage of the first holding capacitor and the second holding voltage of the second holding capacitor to the pixel electrode at a predetermined cycle shorter than the vertical scanning cycle. And
The positive ramp signal and the negative ramp signal reach the voltage indicating the maximum gradation value within a horizontal scanning period and then return to the voltage indicating the minimum gradation value. Within the period up to the start of the horizontal scanning period, the first voltage of the voltage indicating the minimum gradation value of the positive polarity ramp signal is used as the potential of the one data line of the set of the two data lines. First switch means for connecting to the source, and second switch means for connecting the potential of the other data line to the second voltage source of the voltage indicating the minimum gradation value of the negative polarity ramp signal, A liquid crystal display element having the set of two data lines. Each of a plurality of pixels provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other with a set of two data lines,
A display element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other;
When the pixel value of the input image data coincides with the gradation value indicated by the reference gradation data whose value changes monotonously in the horizontal scanning cycle, it passes through one data line of the set of two data lines. Sampling the voltage of the positive polarity ramp signal that monotonically increases from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value within the horizontal scanning period in synchronization with the reference gradation data supplied First sampling and holding means for holding in the first holding capacity for a certain period of time;
When the pixel value of the input image data matches the gradation value indicated by the reference gradation data, the reference gradation data supplied via the other data line of the set of two data lines The voltage of the negative polarity ramp signal having a polarity opposite to that of the positive polarity ramp signal, monotonically decreasing in level from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value within the horizontal scanning period. Sampling and holding means for sampling and holding in the second holding capacitor for a certain period;
Holding voltage reading means for alternately applying the first holding voltage of the first holding capacitor and the second holding voltage of the second holding capacitor to the pixel electrode at a predetermined cycle shorter than the vertical scanning cycle. For a liquid crystal display device comprising
The positive ramp signal and the negative ramp signal reach the voltage indicating the maximum gradation value within a horizontal scanning period and then return to the voltage indicating the minimum gradation value. A method for driving a liquid crystal display element, comprising: a short-circuiting step of short-circuiting the two data lines of each group for each group within a period up to a start time of a horizontal scanning period. Each of a plurality of pixels provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other with a set of two data lines,
A display element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other;
When the pixel value of the input image data coincides with the gradation value indicated by the reference gradation data whose value changes monotonously in the horizontal scanning cycle, it passes through one data line of the set of two data lines. Sampling the voltage of the positive polarity ramp signal that monotonically increases from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value within the horizontal scanning period in synchronization with the reference gradation data supplied First sampling and holding means for holding in the first holding capacity for a certain period of time;
When the pixel value of the input image data matches the gradation value indicated by the reference gradation data, the reference gradation data supplied via the other data line of the set of two data lines The voltage of the negative polarity ramp signal having a polarity opposite to that of the positive polarity ramp signal, monotonically decreasing in level from the voltage indicating the minimum gradation value to the voltage indicating the maximum gradation value within the horizontal scanning period. Sampling and holding means for sampling and holding in the second holding capacitor for a certain period;
Holding voltage reading means for alternately applying the first holding voltage of the first holding capacitor and the second holding voltage of the second holding capacitor to the pixel electrode at a predetermined cycle shorter than the vertical scanning cycle. For a liquid crystal display device comprising
The positive ramp signal and the negative ramp signal reach the voltage indicating the maximum gradation value within a horizontal scanning period and then return to the voltage indicating the minimum gradation value. Within the period up to the start of the horizontal scanning period, the first voltage of the voltage indicating the minimum gradation value of the positive polarity ramp signal is used as the potential of the one data line of the two data lines of each set. A first connection step of connecting to a source;
Simultaneously with the first connection step, the potential of the other data line of the two data lines in each set is connected to the second voltage source of the voltage indicating the minimum gradation value of the negative polarity ramp signal. And a second connection step. A method for driving a liquid crystal display element.

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