JP5316265B2 - Liquid crystal display device and driving method thereof - Google Patents

Description

  The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly to a liquid crystal display device used for a reflective liquid crystal projector device and the like, which is driven after converting an input digital video signal into an analog video signal, and a driving method thereof.

  In recent years, a liquid crystal display device of LCOS (Liquid Crystal on Silicon) type is often used as a central part for projecting an image in a projector device or a projection television. This LCOS liquid crystal display device has a structure in which a transparent electrode, a liquid crystal layer, a reflective electrode arranged in a matrix, a liquid crystal display device in which a liquid crystal driving circuit is formed on a silicon substrate, and the like overlap.

  In this liquid crystal display device, an analog video signal is input and the liquid crystal is driven, so that the light transmittance can be continuously controlled and good gradation characteristics can be obtained. On the other hand, with the advancement of digital signal processing technology, digitization of external circuits of liquid crystal elements is progressing. Accordingly, it is becoming more convenient for the entire system to input a digital signal as a video signal to the liquid crystal element, and the digital video signal is converted into an analog video signal pixel by pixel using a ramp waveform. A liquid crystal display device to be driven has been proposed (see, for example, Patent Document 1).

  The liquid crystal device described in Patent Document 1 is a drive circuit for an active matrix type liquid crystal panel, and has a simple 1H period ramp waveform having all video signal components from black to white as shown in FIG. While supplying to the video switch, the counter is counted up with a clock synchronized with the ramp waveform. Then, the count value and each horizontal pixel value latched in the line buffer are compared in pixel units in the comparator, and when the count value becomes the same value as the pixel value latched in the line buffer, The video switch corresponding to the pixel is turned off, and the voltage of the ramp waveform at this time is held in the pixel connected to the video switch that is turned off, whereby conversion to an analog video signal is performed.

  The video switches are turned on all at once by the latch clock signal and start the sampling operation for the parasitic capacitance or the holding capacitance. Then, when a signal when the counter value matches the counter value is output from the comparator, the video switch is turned off to start a voltage ramp holding operation immediately before that, and the voltage value is also stored in the storage capacitor in the pixel. The written liquid crystal element is driven. This operation is performed in parallel with respect to pixels for one line. Usually, since the video signal is different for each pixel, the ON time of the video switch and the held voltage value are different for each pixel.

Japanese Patent Publication No. 7-50389

  In the conventional liquid crystal display device described in Patent Document 1 above, all the video switches are turned on first, and then the parasitic capacitance and the like are gradually charged and discharged, and turned off at a predetermined timing. This makes it difficult to generate voltage errors due to insufficient charge / discharge.

  However, if a uniform halftone screen (gray) is to be displayed on the above liquid crystal display device, all the video switches are used for a period until the corresponding video switch of the pixel column corresponding to the corresponding gradation level is turned off. The period during which is on continues. During this continuous ON period, the pixel data line on the output side of the video switch serves as a load for the reference lamp voltage power supply line. Therefore, according to the liquid crystal display device, when displaying a uniform halftone screen (gray), the reference lamp voltage waveform may be delayed by the load, and the luminance may be lower than the original gray.

  On the other hand, when displaying a picture in which gray and black are mixed in the horizontal direction, the video switch of the pixel column corresponding to black is turned off in advance, and the load on the reference lamp voltage supply line is cut off and reduced. The brightness of the gray part increases. Thus, according to the liquid crystal display device described above, the gray displayed on both sides of the black is brighter than the gray displayed uniformly over the entire horizontal direction, and has a so-called “lateral pull” shape as shown in FIG. Image noise will occur.

  In the display screen of the liquid crystal display device shown in FIG. 7, the upper and lower belt-like images I are gray images, and are lighter than the original gray as indicated by III on both sides of the black image II between them. This image is displayed as the above-mentioned “horizontal drawing” image noise.

  The present invention has been made in view of the above points, and generates corrected video data corrected so as not to depend on the number of gradation data existing below the gradation to be displayed, and the corrected video data An object of the present invention is to provide a digital signal input type liquid crystal display device which can display a high-quality image without horizontal noise by outputting a value of a ramp signal corresponding to the pixel value to the pixel, and a driving method thereof. .

  In order to achieve the above object, a liquid crystal display device of the present invention is provided at a crossing where a plurality of data lines and a plurality of gate lines intersect, and a pixel selection transistor and a holding circuit connected to the pixel selection transistor A plurality of pixels each including a capacitor and a liquid crystal element that performs display by applying a value held in the storage capacitor; a plurality of data lines provided corresponding to the plurality of data lines; A plurality of video switches that sequentially switch and supply analog signals indicating the value of each pixel in the horizontal direction, a vertical driving circuit that sequentially selects a plurality of gate lines, and an image of each pixel for one line in the digital video signal Based on the first holding means for holding data and the video data of each pixel for one line held in the first holding means, for each gradation, an image existing below that gradation is present. The calculation means for calculating the data occurrence frequency information and the video data of each pixel for one line held in the first holding means are multiplied by a predetermined correction coefficient for the occurrence frequency information of the video data. Corrected video data generating means for subtracting the obtained correction data to generate corrected video data for each pixel; second holding means for holding corrected video data for each pixel for one line; Comparing the corrected video data of each pixel for one line held by the second holding means with the count value whose value sequentially changes in one horizontal scanning period to detect whether or not they match. Means, a ramp signal generating means for generating a ramp signal that changes from one of the black level and white level to the other level at a constant period, and a plurality of signals at the beginning of one horizontal scanning period based on the comparison result from the comparing means. The bidet The switch is turned on at the same time, a signal of a predetermined level is output to the data line through the video switch, and then the comparison result among the pixels of one line of the corrected video data held in the second holding means The video switch corresponding to the pixel indicating the coincidence is controlled to be turned off, and the value of the ramp signal corresponding to the video data of the pixel immediately before the off is connected to the video switch that is controlled to be off of the pixel portion, and the vertical Conversion means for performing an operation of holding in a holding capacitor of a pixel connected to the gate line selected by the direction driving circuit.

  In order to achieve the above object, a driving method of a liquid crystal display device according to the present invention is provided at intersections where a plurality of data lines and a plurality of gate lines intersect with each other. Among a plurality of pixels including a storage capacitor connected to the transistor and a liquid crystal element that performs display by applying a value stored in the storage capacitor, video data of each pixel for one horizontal line is obtained. Based on the first step held in one holding means and the video data of each pixel for one line held in the first holding means, the video data existing below the gradation for each gradation The second step of calculating the occurrence frequency information of the image data, and the video data occurrence frequency information multiplied by a predetermined correction coefficient for each of the video data of each pixel for one line held in the first holding means. A third step of subtracting the obtained correction data to generate corrected video data for each pixel, and a fourth step of holding the corrected video data for each pixel for one line in the second holding means The step and the corrected video data of each pixel for one line held by the second holding means are compared with the count value whose value sequentially changes in one horizontal scanning period to determine whether or not they match. A fifth step of detecting, a sixth step of generating a ramp signal that changes from one of the black level and the white level to the other of the black level and the white level at a constant period; and a plurality of steps connected to the plurality of data lines, respectively. The video switch is controlled to be turned on simultaneously at the beginning of one horizontal scanning period based on the comparison result of the fifth step, and a signal at a predetermined level is output to the plurality of data lines through the plurality of video switches. And a video corresponding to a pixel whose comparison result is identical among the pixels of one line of the corrected video data held in the second holding means after the control of the plurality of video switches in the seventh step. The storage capacitor of the pixel connected to the selected video signal line that is connected to the video switch that is controlled to turn off the value of the ramp signal corresponding to the video data of the pixel immediately before the switch is turned off. And an eighth step to be held.

  According to the present invention, corrected video data that is corrected so as not to depend on the number of gradation data existing below the gradation to be displayed is generated, and a ramp signal corresponding to the pixel value of the corrected video data is generated. By outputting this value to the pixel, it is possible to display a high-quality image without horizontal noise.

It is a block diagram of one embodiment of the liquid crystal display device of the present invention. It is a block diagram of one Embodiment of the principal part of the horizontal direction drive circuit of the liquid crystal display device of this invention. It is a flowchart for operation | movement description of FIG. It is a circuit system diagram of one Embodiment of the conversion circuit part which is the other principal part of the horizontal direction drive circuit of the liquid crystal display device of this invention. 5 is a timing chart for explaining the operation of FIG. 4. It is explanatory drawing about the generation | occurrence | production mechanism of horizontal pulling noise, and operation | movement of one Embodiment of the principal part of the liquid crystal display device of this invention. It is a figure which shows an example of the horizontal pulling noise which generate | occur | produces with the conventional liquid crystal display device.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a configuration diagram of an embodiment of a liquid crystal display device according to the present invention. The liquid crystal display device 100 according to the present embodiment includes a horizontal direction driving circuit 10, a vertical direction driving circuit 20, a pixel unit 30, a controller 40, and the like. The horizontal driving circuit 10 constitutes a main part of the present embodiment, and m data lines (column signal lines) 6-1 to 6 through m video switches 1-1 to 1-m. -M sequentially outputs the video data obtained by converting the input digital video signal into an analog video signal within one horizontal scanning period. The configuration and operation of the horizontal driving circuit 10 that is a feature of the present embodiment will be described later.

  The vertical driving circuit 20 sequentially outputs selection signals to n gate lines (row scanning lines) 8-1 to 8-n within one vertical scanning period. The controller 40 generates various clock signals synchronized with the input digital video signal and supplies them to the horizontal direction driving circuit 10 and the vertical direction driving circuit 20, respectively, and generates a ramp signal and supplies it to the horizontal direction driving circuit 10. (Route not shown).

  The pixel portion 30 is provided at the intersection where the m data lines 6-1 to 6-m and the n gate lines 8-1 to 8-n cross each other, and a total of n · m pieces It consists of pixels 11 to nm. Each of the pixels 11 to nm has a pixel selection transistor 2, a signal holding capacitor 3 connected to the pixel selection transistor 2, and a liquid crystal element connected to the signal holding capacitor 3 as shown in FIG. And a reflective electrode (pixel drive electrode) 4 for driving the. The liquid crystal element includes a reflection electrode 4, a counter electrode (common electrode) facing the reflection electrode 4, and a liquid crystal layer (none of which is shown) disposed between the reflection electrode 4 and the counter electrode. Structure. The pixel selection transistor 2 has a gate connected to the gate line and a drain connected to the data line. The common electrode is connected to the common electrode line 7.

  In the liquid crystal display device 100, pixels at intersections of the data lines 6-1 to 6-m and the gate lines 8-1 to 8-n are detected by a horizontal scanning signal or a row selection signal synchronized with the input digital video signal. The pixel value is written into the signal holding capacitor 3 via the pixel selection transistor 2 in the pixel, and the liquid crystal layer is driven via the reflective electrode 4 connected to the signal holding capacitor 3 with the pixel value. Display as video.

  Although the display operation itself of the liquid crystal display device 100 is general, the present embodiment is characterized in that the horizontal direction driving circuit 10 is configured so that the above-described “horizontal drawing” -like image noise is not displayed. Hereinafter, the configuration and operation of the horizontal driving circuit 10 will be described in detail.

  FIG. 2 shows a block diagram of an embodiment of the main part of the horizontal driving circuit 10. The driver board 50 shown in FIG. 2 is provided in the horizontal driving circuit 10, but the synchronization signal generation unit 51 may be provided in the controller 40. The driver board 50 includes a synchronization signal generation unit 51, a line memory 52, a calculator 53, a subtractor 54, and a line memory 55. The driver board 50 plays a role of sending the input digital video signal to the liquid crystal element in a predetermined format and at a predetermined timing. The synchronization signal generation unit 51 shapes the synchronization signal of the digital video signal to generate a horizontal synchronization signal and a vertical synchronization signal, further generates various clock signals based on them, and outputs them, which will be described later. The other circuit units in the horizontal drive circuit 10 are driven and the vertical drive circuit 20 is driven.

  The circuit units other than the synchronization signal generating unit 51 in the driver board 50 are circuit units that perform video data correction processing for removing the above-described “horizontal drawing” -like image noise. The line memory 52 temporarily holds data for one line of an input 10-bit digital video signal, for example. For example, when performing full HD display of 1920 pixels in the horizontal direction and 1080 pixels in the vertical direction (that is, 1920 × 1080 pixels), a digital video signal (video data) of 1920 pixels for one line is held. Here, the video data output from the line memory 52 is displayed as LMa (x) (x is a horizontal address, here 0-1919).

  The computing unit 53 refers to the video data for one line stored in the line memory 52, predicts the degree of occurrence of horizontal noise, and calculates correction data for changing the video data for one line. To do. A method of calculating correction data by the calculator 53 will be described in detail with reference to the flowchart of FIG.

  First, the computing unit 53 shown in FIG. 2 includes a histogram H (k) calculated by the histogram computing unit 531 (k is gradation data, for example, 0 to 1023 in the case of 10-bit video data) and forward histogram integration. The forward histogram integration frequency Hsum (k) calculated by the frequency calculation unit 532 is initialized to “0” (step S1).

  Subsequently, the computing unit 53 acquires the video data LMa (x) stored in the line memory 52 (step S2). Next, the computing unit 53 uses the histogram computing unit 531 to generate each gradation (pixel value) based on all of the 1920-pixel video data LMa (0) to LMa (1919) obtained from the line memory 52. ) Histogram data H (LMa (x)) indicating the number of pixels is calculated (steps S3 to S5).

  Subsequently, based on the histogram data H (LMa (x)) calculated by the histogram calculator 531, the calculator 53 calculates the forward histogram cumulative frequency Hsum (k) in the forward histogram cumulative frequency calculator 532. (Steps S6 to S8). The forward histogram integration frequency Hsum (k) is the order of the histogram data H (LMa (x)) in order of gradation from gradation 0 to gradation 1023 represented by 10 bits because the input video data is 10 bits. Histogram data H (LMa (x)) of gradations that are arranged in the direction and that exist for each gradation until the gradation data H (LMa (x)) immediately before that gradation (less than the gradation). It is the data which shows the value which integrated the integrated value (occurrence frequency). Accordingly, the forward histogram integration frequency Hsum (k) indicates the minimum value at the minimum gradation, and increases as the gradation increases, and indicates the maximum value at the maximum gradation.

  Then, the calculator 53 uses the correction coefficient multiplication unit 533 to process one line for each of 1920 pixels of video data LMa (0) to LMa (1919) for one line of the forward histogram integration frequency Hsum (k). A value α (Hsum (LMa (x) −1)) obtained by multiplying the forward histogram integration frequency Hsum (LMa (x) −1) up to the pixel immediately before the corresponding pixel by the correction coefficient α is calculated as correction data. Here, α is a correction coefficient (a real number other than 0), which is determined by the load on the data line on the output side of the video switch, and is a value specific to the liquid crystal element. Therefore, the value of α is a value to be adjusted unique to the liquid crystal element, and the optimum value is determined while actually displaying an image.

  Next, the subtractor 54 subtracts the correction data α (Hsum (LMa (x) −1)) generated by the calculator 53 from the video data LMa (x) output from the line memory 52, and then The corrected video data LMb (x) represented by the equation is calculated (steps S9 to S11).

LMb (x) = LMa (x) −α (Hsum (LMa (x) −1)) (1)
As will be described later, since the influence of the horizontal noise depends on the number of gradation data existing below the gradation to be displayed, the input video data LMa (x) is corrected for LMb (x) in equation (1). Indicates the value to be.

  Then, the subtractor 54 outputs the corrected video data LMb (x) and stores it for one line in the line memory 55 (step S12). The line memory 55 sequentially outputs the accumulated 10-bit corrected video data LMb (x) for one line, and the latch circuit 62-in the conversion circuit section shown in FIG. 1 to 62-m is supplied via a terminal 73.

  The calculation by the arithmetic unit 53 can be accelerated by incorporating it as hardware in a drive board provided outside the element. Since the circuit portion shown in FIG. 2 temporarily stores video data for one line in the line memories 52 and 55, the display timing is slightly delayed with respect to the input of the video signal, but this is not a problem. Further, here, for convenience of explanation, the line memories 52 and 55 are described as separately existing, but the line memories 52 and 55 may be shared by one line memory.

  FIG. 4 shows a circuit system diagram of an example of the conversion circuit unit which is another main part in the horizontal driving circuit 10. 4 includes the video switches 1-1 to 1-m shown in FIG. 1 for convenience of illustration.

  In FIG. 4, the shift register 61 in m stages (m is a natural number of 2 or more and corresponds to the number of pixels in the horizontal direction of the pixel portion, which is 1920 in the above example) is synchronized with the clock signal (XCL) 72. Thus, the start pulse (XSP) 71 as shift data is sequentially shifted rightward.

  The latch circuits 62-1 to 62-m are provided in one-to-one correspondence with the m output terminals Q1 to Qm of the shift register 61, respectively. Each of the latch circuits 62-1 to 62-m is commonly supplied to a terminal 73 with bit data PD1 to PD10 of a digital video signal inputted in parallel from the line memory 55 shown in FIG. Bit data PD1 to PD10 are latched (temporarily held) when the corresponding data among the data output from Q1 to Qm is a predetermined value (logical value of XSP71). Here, since the m predetermined output data are sequentially output from the m output terminals Q1 to Qm of the shift register 61 within one horizontal scanning period (1H), the latch circuits 62-1 to 62-m are output. The bit data PD1 to PD10 are sequentially latched from left to right within 1H.

  The latch circuits 63-1 to 63-m are provided in a one-to-one correspondence with the latch circuits 62-1 to 62-m, and the first clock signal (LCL) 74 is commonly supplied to the LCL signal. When 74 becomes a predetermined logic value, a latch operation is performed simultaneously. Note that the latch circuits 63-1 to 63-m may be one line buffer.

  The comparators 64-1 to 64-m are provided in a one-to-one correspondence with the latch circuits 63-1 to 63-m, and 10-bit data output in parallel from the latch circuits 63-1 to 63-m. And the 10-bit count value output from the counter 65 are compared. The counter 65 counts the second clock signal (CLK) 75 and outputs a 10-bit count value to the latch circuits 63-1 to 63-m.

  The control circuits 66-1 to 66 -m are provided in a one-to-one correspondence with the comparators 64-1 to 64 -m, and the first clock signal (LCL) 74 is supplied in common and the comparators 66-1 to 66 -m Comparison results 64-1 to 64-m are supplied. The level shifters 67-1 to 67-m are provided in one-to-one correspondence with the control circuits 66-1 to 66-m, and perform switching control of the switches 68-1 to 68-m that are analog switches. The switches 68-1 to 68-m correspond to the analog switches 1-1 to 1-m shown in FIG. A ramp signal (Video signal) 77 is commonly supplied to the switches 68-1 to 68-m.

  The control circuits 66-1 to 66-m are initialized and output a high level signal when the LCL signal 74 becomes a predetermined logical value, and then input to the comparators 64-1 to 64-. When the m comparison output signals 78-1 to 78-m are at a low level indicating a comparison mismatch, a high level signal is continuously output, and when the comparison output signals 78-1 to 78-m are at a high level indicating a comparison match Outputs a low level signal. The control circuits 66-1 to 66-m hold the low level signal output state when the comparison output signals 78-1 to 78-m become low level after becoming high level. Such control circuits 66-1 to 66-m can be configured by exclusive OR circuits and flip-flops.

  Next, the operation of the conversion circuit unit of FIG. 4 will be described with reference to the timing chart of FIG.

  In accordance with the shift operation of the shift register 61, latch pulses are sequentially output from the output terminals Q1 to Qm of the shift register 61, and one line of pixel data PD1 to PD10 is sequentially supplied to the latch circuits 62-1 to 62-m. Is latched on. Immediately after the latching of the pixel data for one line, the 1H-cycle LCL signal 74 shown in FIG. 5A becomes a predetermined logical value (here, high level), and is supplied to each of the latch circuits 62-1 to 62-m. Each latched 10-bit pixel data is transferred to and latched in corresponding latch circuits 63-1 to 63-m. Subsequently, according to the shift operation of the shift register 61, the latch circuits 62-1 to 62-m move to an operation of taking in each pixel data of the digital video signal of the next line.

  On the other hand, the counter 65 counts the CLK signal 75 shown in FIG. 5C and outputs a 10-bit count value that is sequentially counted up. When the pixel data of the digital video signal 73 is 10 bits, the counter 65 is usually a binary counter that outputs a 10-bit counter value indicating a value from “0” to “1023” in decimal.

  The comparators 64-1 to 64-m match the 10-bit pixel data value output in parallel from the latch circuits 63-1 to 63-m and the 10-bit count value output in parallel from the counter 65. A comparison operation is performed in units of pixels. For example, high-level comparison output signals 78-1 to 78-m are output when they match, and low levels when they do not match. The comparators 64-1 to 64-m output a high-level coincidence signal when the counter value is any one of the counter values (for example, “0” to “1023”) in one cycle of the counter 65. The comparators 64-1 to 64-m supply the comparison output signals 78-1 to 78-m to the control circuits 66-1 to 66-m.

  In the control circuits 66-1 to 66-m, when the LCL signal 74 becomes a predetermined logical value (here, high level), the output signal becomes high level. The level shifters 67-1 to 67-m turn on the switches 68-1 to 68-m when a high level output signal is supplied from the control circuits 66-1 to 66-m.

  As a result, first, the switches 68-1 to 68-m are forcibly turned on at the same time. When the ramp signal (Video signal) 77 shown in FIG. Are output respectively. The black level video signals 77 output from the switches 68-1 to 68-m are output to the data lines 6-1 to 6-m of the pixel unit 30 shown in FIG. Writing is performed for pixels in one line selected by −1 to 8-n. Note that the Video signal 77 is a 1H cycle ramp signal that continuously changes from a predetermined off level to an on level (black level to white level) of the liquid crystal element.

  Next, the counter 65 starts counting the CLK signal 75 with a constant period shown in FIG. As a result, the 10-bit count value of the counter 65 increases as schematically shown in FIG. The comparators 64-1 to 64-m compare the 10-bit counter value from the counter 65 with the 10-bit pixel data value from the latch circuits 63-1 to 63-m. When they match, a high-level comparison output signal 78 is output and supplied to the control circuits 66-1 to 66 -m.

  The counter operation of the counter 65 in FIG. 4 proceeds and the counter value increases, and the comparator indicating that the comparison results match among the comparators 64-1 to 64-m outputs a high-level comparison output signal. As a result, the output signal of the control circuit provided correspondingly among the control circuits 66-1 to 66-m becomes low level, and the switch supplied as the switching signal through the corresponding level shifter is turned off. .

  Among the switches 68-1 to 68 -m, among the pixels arranged in the vertical direction in the pixel unit 30 connected to the switch turned off through the data line, the gate lines 8-1 to 8-1 at that time The signal holding capacitor 3 of the pixel selected in 8-n holds the voltage of the Video signal 77 output immediately before the switch that is turned off. The voltage of the video signal 77 held at this time corresponds to the pixel value (gradation level) of the digital video signal of the pixel. That is, 10-bit pixel data PD1 to PD10 of the input digital video signal is converted into an analog video signal and accumulated in the signal holding capacitor 3 of the pixel.

  Further, when the counter operation of the counter 65 in FIG. 2 advances and the counter value increases, a low-level comparison output signal indicating that the comparison result does not match is continuously output from the comparator indicating comparison match. The corresponding control circuit holds the low level output state as described above. As a result, the switch once turned off maintains the off state.

  Other switches are similarly controlled. As a result, the voltage of the video signal 77 immediately before the switches 68-1 to 68-m are turned off is held until the next frame by the signal holding capacitors of the respective pixels to drive the liquid crystal. FIG. 5E schematically shows that the switch 68-1 corresponding to, for example, the video switch 1-1 in FIG. 1 is turned off at the count value “2”. At this time, the voltage V2 of the Video signal 77 is It is held in the pixel connected to the video switch 1-1 (68-1). FIG. 5F schematically shows that the switch 68-3 corresponding to, for example, the video switch 1-3 in FIG. 1 is turned off at the count value “n”. At this time, the voltage of the Video signal 77 is Vn is held in the pixel connected to the video switch 1-3 (68-3).

  Since the switches 68-1 to 68-m (video switches 1-1 to 1-m in FIG. 1) are turned off according to the data (brightness) of each pixel, a plurality of pixels in the horizontal direction are simultaneously operated. The pixel may be turned off, or the pixel to be turned off may be zero depending on the count value.

  As described above, the switches 68-1 to 68-m are turned on from the time when the video signal 77 is at a low level, and signals are gradually accumulated in the pixels in accordance with the change in the signal level of the video signal 77. Therefore, while it is easy to secure a sufficient charge / discharge time, many of the switches 68-1 to 68-m are often turned on during a period when the count value is low (0, 1, 2, etc.).

  As described above, in the present embodiment, initialization by the LCL signal 74 (all switches 68-1 to 68-m are turned on) and the inconsistency period between the value of each pixel of the digital video signal and the counter value correspond to each other. When the pixel switch continues to be turned on and matches, the corresponding pixel switch is turned off and the video signal 77 is written to the signal holding capacitor of the corresponding pixel, and the switch is turned off for the subsequent mismatch period. As a result, a series of writing control of holding the pixel value written in the signal holding capacitor becomes possible.

  Next, the generation mechanism of the horizontal noise will be described with reference to FIG. FIG. 6A shows the waveform of the ramp signal (Video signal 77) when the liquid crystal display device according to this embodiment is to display an image of uniform intermediate gradation (gray) within one screen. .

  When an image having a uniform halftone (gray) is to be displayed, the corresponding one of the switches 68-1 to 68-m (corresponding to the video switches 1-1 to 1-m in FIG. 1) shown in FIG. The period in which all the video switches are in the on state continues until the corresponding video switch in the pixel column corresponding to the gradation level to be turned off. During this continuous ON period, the data line on the output side of the video switch serves as a load for the ramp signal (Video signal) feed line.

  In FIG. 6A, a dotted line c shows a waveform of an ideal ramp signal (Video signal 77 in FIG. 4) in a state where there is no load on the video switch output side. The timing at which the gray potential is fixed (timing at which the signals 78-1 to 78-m indicating comparison coincidence are output from the comparators 64-1 to 64-m when the gray level is gray) is denoted by t. At this time, the potential of the ideal ramp signal (that is, the converted pixel value output to the data line) is Vc.

  On the other hand, according to the conversion circuit unit shown in FIG. 4, when displaying an image having a uniform halftone (gray), the ramp signal waveform is delayed by the load on the video switch output side, and FIG. The potential of the ramp signal (converted pixel value) determined at the timing indicated by t when a uniform gray image is displayed becomes Va, which is higher than the ideal potential Vc. You can see that it is lower. For this reason, the luminance is lower than the original gray.

  In FIG. 6A, the ramp signal indicated by b (Video signal 77 in FIG. 4) indicates the waveform of the ramp signal in the case of displaying a picture in which gray and black are mixed in the horizontal direction. Here, the number of pixels corresponding to black is half of the total number of pixels in the horizontal direction. Since the video switch of the pixel row corresponding to black is turned off in advance and the load of the ramp signal power supply line is cut off and reduced, the delay of the ramp signal waveform displays a uniform grayscale image. About half of the delay time.

  Therefore, as shown in FIG. 6A, at the timing t at which gray writing is determined, the potential of the ramp signal is higher than Va in the case where uniform gray is displayed, and the ideal potential Vc. The potential Vb is lower than that. As a result, the brightness of the gray portion increases. Thus, according to the above conversion circuit unit, the gray displayed on both sides of the black is brighter than the gray displayed uniformly over the entire horizontal direction, and the so-called “horizontal drawing” shape as shown in FIG. Image noise occurs.

  Therefore, in order to remove the so-called “laterally-drawn” image noise, when video data for one line in which gray is displayed on both sides of black is input in this embodiment, as described above, After the calculation unit 531 shown in FIG. 2 calculates and calculates a histogram H (k) indicating a certain value in each gradation of the black level and the gray level in the histogram calculation unit 531 as shown in FIG. 6B. Then, the forward histogram integrated frequency calculation unit 532 calculates a histogram integrated frequency Hsum (k) as shown in FIG. 6C based on the histogram H (k) (here, the number of pixels corresponding to black). Is half the total number of pixels in the horizontal direction.)

  Subsequently, the computing unit 53 shown in FIG. 2 uses the correction coefficient multiplication unit 533 to output video data LMa (0) to LMa (1919) of 1920 pixels for one line out of the forward histogram integration frequency Hsum (k). In each line, a value α (Hsum (LMa (x) −1)) obtained by multiplying the forward histogram integration frequency Hsum (LMa (x) −1) up to the pixel immediately before the corresponding pixel in one line by the correction coefficient α. Calculated as correction data. Then, the computing unit 53 calculates and outputs the corrected video data LMb (x) represented by the above-described equation (1) in the subtractor 54.

  Here, since the waveform of the ramp signal (Video signal 77 in FIG. 4) when displaying a pattern in which gray and black are mixed in the horizontal direction is the waveform indicated by b in FIG. When the video data LMa (x) before correction is converted into an analog video signal using the ramp signal (Video signal 77) in the conversion circuit unit shown in FIG. 4, the lamp at the timing t at the moment when the gray potential is determined. The potential of the signal (converted pixel value) becomes Vb, and the above-described “horizontal drawing” image noise occurs.

  On the other hand, in the present embodiment, the corrected video data LMb (x) is a value obtained by subtracting the correction data from the uncorrected video data LMa (x) as shown in the equation (1). Therefore, when the corrected video data LMb (x) is converted into an analog video signal using the ramp signal (Video signal 77) in the conversion circuit unit shown in FIG. 4, the timing at the moment when the gray potential is determined. The potential (converted pixel value) of the ramp signal becomes Va as shown in FIG. Since this potential Va is equal to the potential Va in the case where uniform gray is displayed, there is no luminance difference between the gray on both sides of black and the surrounding gray. "-Like image noise can be prevented from being seen, and high-quality image display can be performed.

  Note that the present invention is not limited to the above-described embodiment. For example, the number of bits of a digital video signal is not limited to 10 bits.

1-1 to 1-m, 68-1 to 68-m Video switch 2 Pixel selection transistor 3 Signal holding capacitor 4 Reflective electrode 5 Horizontal signal lines 6-1 to 6-m Data line 7 Common electrode lines 8-1 to 8-8 -N Gate line 10 Horizontal direction drive circuit 20 Vertical direction drive circuit 30 Pixel unit 40 Controller 50 Driver board 51 Synchronization signal generation unit 52, 55 Line memory 53 Operation unit 54 Subtractor 61 Shift registers 62-1 to 62-m, 63 -1 to 63-m Latch circuit (line buffer)
64-1 to 64-m Comparator 65 Counter 66-1 to 66-m Control circuit 67-1 to 67-m Level shifter 74 First clock signal (LCL)
75 Second clock signal (CLK)
77 Ramp signal (Video signal)
78-1 to 78-m Comparison output signal 100 Liquid crystal display device 531 Histogram calculation unit 532 Forward histogram integration frequency calculation unit 533 Correction coefficient multiplication unit

Claims (2)

A pixel selection transistor, a storage capacitor connected to the pixel selection transistor, and a value stored in the storage capacitor are applied and displayed at intersections where a plurality of data lines and a plurality of gate lines intersect. A pixel portion in which a plurality of pixels each including a liquid crystal element for performing
A plurality of video switches provided corresponding to the plurality of data lines and sequentially supplying analog signals indicating values of respective pixels in the horizontal direction to the plurality of data lines;
A vertical driving circuit for sequentially selecting the plurality of gate lines;
First holding means for holding video data of each pixel for one line in the digital video signal;
Calculating means for calculating occurrence frequency information of the video data existing below the gradation for each gradation based on the video data of each pixel for the one line held in the first holding means; ,
Correction data obtained by multiplying the occurrence frequency information of the video data by a predetermined correction coefficient is subtracted from the video data of each pixel for one line held in the first holding means. Corrected video data generating means for generating corrected video data for each pixel;
A second holding means for holding the corrected video data of each pixel for one line;
The corrected video data of each pixel for one line held by the second holding means is compared with the count value whose value sequentially changes in one horizontal scanning period to detect whether or not they match. Comparing means to
Ramp signal generating means for generating a ramp signal that changes from one of the black level and the white level to the other level at a constant cycle;
Based on the comparison result from the comparison means, the plurality of video switches are simultaneously turned on at the beginning of the one horizontal scanning period, and a predetermined level signal is output to the data line through the video switch. Among the pixels of one line of the corrected video data held in the holding means 2, the video switch corresponding to the pixel whose comparison result indicates coincidence is controlled to be turned off, and The value of the ramp signal corresponding to video data is connected to the video switch controlled to be off of the pixel unit, and the pixel of the pixel connected to the gate line selected by the vertical driving circuit is used. A liquid crystal display device comprising: conversion means for performing an operation of holding in the holding capacitor. A plurality of data lines and a plurality of gate lines are provided at intersections, respectively, and a pixel selection transistor, a storage capacitor connected to the pixel selection transistor, and a value stored in the storage capacitor are applied. A first step of holding, in a first holding unit, video data of each pixel for one horizontal line among a plurality of pixels including a liquid crystal element that performs display;
Based on each video data of each pixel for one line held in the first holding means, second generation frequency information of the video data existing below the gray level for each gray level is calculated. Steps,
Correction data obtained by multiplying the occurrence frequency information of the video data by a predetermined correction coefficient is subtracted from the video data of each pixel for one line held in the first holding means. A third step of generating corrected video data for each pixel;
A fourth step of holding the corrected video data of each pixel for one line in a second holding unit;
The corrected video data of each pixel for one line held by the second holding means is compared with the count value whose value sequentially changes in one horizontal scanning period to detect whether or not they match. A fifth step to:
A sixth step of generating a ramp signal that changes from one of the black level and the white level to the other level at a constant period;
The plurality of video switches respectively connected to the plurality of data lines are controlled to be simultaneously turned on at the beginning of the one horizontal scanning period based on the comparison result in the fifth step, and a signal of a predetermined level is transmitted to the plurality of data lines. A seventh step of outputting to the plurality of data lines through a video switch;
After the control of the plurality of video switches in the seventh step, corresponding to the pixel in which the comparison result indicates coincidence among the pixels of one line of the corrected video data held in the second holding unit The video switch is turned off, and the value of the ramp signal corresponding to the video data of the pixel immediately before turning off is connected to the video switch controlled to be turned off, and the selected gate line is connected to the selected gate line. And an eighth step of holding in the holding capacitor of the connected pixel.

Images