JP2005309304A - Data line driving circuit, electro-optical device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption by changing over resolution. <P>SOLUTION: In a low resolution mode, a data bus latch 42 thins out a part of m pieces of data, and outputs i (m>i>1) pieces of gradation data to a data bus. An X shift register 40 produces i pieces of latch signals for specifying each fetch timing of the i pieces of gradation data. A 1st circuit unit 41a fetches one of the i pieces of gradation data outputted to the data bus at the timing specified by one of the i pieces of latch signals, and outputs a gradation signal according thereto to the data line X. A 2nd circuit unit 41b outputs a gradation signal corresponding to one of the i pieces of gradation data fetched by the 1st circuit unit 41a to the data line X. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data line driving circuit, an electro-optical device, and an electronic apparatus, and more particularly to resolution switching control.

For example, Patent Document 1 discloses an image display device that reduces power consumption by reducing the substantial transfer amount of digital gradation data. Specifically, the gradation data to be input this time is compared with the gradation data before one horizontal line (one pixel row). If they do not match, the current gradation data is supplied to the data line driving circuit as usual. In this case, the data line driving circuit performs D / A conversion on the current gradation data and outputs an analog gradation signal to the data line. On the other hand, if the two match, the state of the data bus is held and the transfer of the current gradation data is stopped. In this case, the data line driving circuit outputs a gradation signal to the data line based on the gradation data latched one horizontal line before.
JP 2003-44017 A

  However, in the above-described conventional technology, there is a problem that how much power consumption can be reduced depends on an object to be displayed. For example, in the case of image data, such as a natural image, in which the gradations of pixel rows tend to be equal, the frequency of data transfer stoppage is high, so that effective low power consumption can be expected. However, if this is not the case, since the frequency of data transfer stoppage is low, low power consumption cannot be expected so much. Further, since it is necessary to add a line memory, there is a problem that the cost of the display device is increased.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a novel control method for reducing power consumption by switching the resolution.

  In order to solve such a problem, a first invention provides a data line driving circuit including a holding circuit, a shift register, a first circuit unit, and a second circuit unit. The operation of the data line driving circuit is different between the high resolution mode and the low resolution mode having a lower resolution. In the high resolution mode, the holding circuit outputs m (m ≧ 2) pieces of gradation data serially supplied from the host device during a predetermined period to the data bus as they are. The shift register generates m latch signals that define the capture timing of each of the m grayscale data. The first circuit unit captures any of the m grayscale data output to the data bus at a capture timing defined by any of the m latch signals, and outputs a grayscale signal corresponding to this. Output to the data line. The second circuit unit captures any of the m grayscale data output to the data bus at a capture timing defined by any of the m latch signals, and outputs a grayscale signal corresponding to this. Output to a data line different from the output destination of the first circuit unit. On the other hand, in the low resolution mode, the holding circuit thins out a part of the m pieces of data and outputs i (m> i> 1) pieces of gradation data to the data bus. The shift register generates i latch signals that define the capture timing of i gradation data. The first circuit unit captures any of the i number of gradation data output to the data bus at a capture timing defined by any of the i number of latch signals, and outputs a gradation signal corresponding thereto. Output to the data line. The second circuit unit outputs a gradation signal corresponding to any of the i pieces of gradation data fetched in the first circuit unit to the data line.

  Here, in the first invention, the first circuit unit includes a first latch circuit having its own input terminal connected to the data bus, and its own input terminal connected to the output terminal of the first latch circuit. And a second latch circuit and an output circuit for outputting a gradation signal corresponding to the gradation data output from the output terminal of the second latch circuit to the data line. In this case, the second circuit unit includes a first latch circuit having its input terminal connected to the data bus, and one input terminal of the second circuit unit at the output terminal of the first latch circuit in the second circuit unit. The other input terminal is connected to the output terminal of the first latch circuit in the first circuit unit, and one input terminal or the other input terminal is selectively connected to the output terminal of the first circuit unit. The first selector to which the input terminal is connected to the output terminal of the first selector, and the gradation corresponding to the gradation data output from the output terminal of the second latch circuit And an output circuit for outputting a signal to the data line.

  In the first invention, the first circuit unit includes a first latch circuit having its own input terminal connected to the data bus, and its own input terminal connected to an output terminal of the first latch circuit. A second latch circuit and an output circuit for outputting a gradation signal corresponding to the gradation data output from the output terminal of the second latch circuit to the data line may be included. In this case, the second circuit unit includes a first latch circuit having its own input terminal connected to the data bus, and a second latch circuit having its own input terminal connected to the output terminal of the first latch circuit. One input terminal of the second latch circuit in the second circuit unit is connected to the output terminal of the second latch circuit, and the other input terminal of the second circuit unit is connected to the output terminal of the second latch circuit in the first circuit unit. A first selector that selectively connects one input terminal or the other input terminal to its own output terminal, and a gradation corresponding to the gradation data output from the output terminal of the first selector And an output circuit for outputting a signal to the data line.

  In the first invention, the shift register forms part of an m-stage shift register configuration, and generates a plurality of third latch circuits for generating a latch signal for the first circuit unit, and a third latch circuit; By providing them alternately, a part of the m-stage shift register configuration is formed, and a plurality of fourth latch circuits for generating a latch signal for the second circuit unit and a fourth latch circuit located in the previous stage are provided. One input terminal of the self is connected to the output terminal, the other input terminal of the self is connected to the output terminal of the third latch circuit located in the preceding stage, and the input terminal of the third latch circuit located in the subsequent stage. And a second selector for selectively connecting one input terminal or the other input terminal to the output terminal. In this case, in the high-resolution mode, the second selector connects the output terminal of the fourth latch circuit located in the preceding stage and the input terminal of the third latch circuit located in the succeeding stage, so that a plurality of the second selectors are connected. It is desirable that the three latch circuits and the plurality of fourth latch circuits cooperate to generate m latch signals. In the low resolution mode, the second selector connects the output terminal of the third latch circuit located in the preceding stage and the input terminal of the third latch circuit located in the succeeding stage, so that a plurality of It is desirable that the third latch circuit operates to generate i latch signals.

  In the first invention, it is preferable that the third latch circuit operates with a first clock signal and the fourth latch circuit operates with a second clock signal. In this case, in the high resolution mode, the first clock signal and the second clock signal are set to the same clock. In the low resolution mode, the first clock signal is set to a longer cycle than in the high resolution mode, and the second clock signal is maintained at a level for setting the fourth latch circuit to the non-operation state. Is done.

  According to a second aspect of the present invention, a plurality of scanning lines, a plurality of data lines, a display unit in which a plurality of pixels are arranged corresponding to the intersections of the plurality of scanning lines and the plurality of data lines, Provided is an electro-optical device having a scanning line driving circuit that sequentially selects scanning lines and a data line driving circuit that outputs gradation signals to a plurality of data lines in cooperation with the scanning line driving circuit. Here, the data line driving circuit is the data line driving circuit according to the first invention described above.

  In the second invention, a mode signal generation circuit for generating a mode signal instructing switching between the high resolution mode and the low resolution mode may be further provided. The mode signal generation circuit includes a register for holding an address of a designated area for performing low resolution display or high resolution display on the display unit, a horizontal counter for counting the number of data in the horizontal direction, and a vertical for counting the number of data in the vertical direction. The counter includes a comparison circuit that generates a mode signal by comparing the count value of the horizontal counter and the count value of the vertical counter with the address held by the register. In addition, the mode signal generation circuit may generate a mode signal according to the usage status or the remaining battery level.

  A third invention provides an electronic apparatus in which the electro-optical device according to the second invention described above is mounted.

  In the present invention, the operation of the data line driving circuit is switched between a case where high-resolution display is performed and a case where low-resolution display is performed. At the time of low resolution display, gradation data is thinned out by the holding circuit, and the number of latch signals necessary for operating the data line driving circuit is also reduced compared to that at the time of high resolution display. As a result, it is possible to reduce the power consumed by the shift register and the latch circuit as compared with the case where high-resolution display is uniformly performed.

(First embodiment)
FIG. 1 is a block diagram of the electro-optical device according to the present embodiment. The display unit 1 is an active matrix display panel in which a liquid crystal element is driven by a switching element such as a TFT (thin film transistor). In the display unit 1, pixels 2 for m (m ≧ 2) dots × n (n ≧ 2) lines are arranged in a matrix (two-dimensional planar). The display unit 1 includes n scanning lines Y1 to Yn each extending in the row direction (X direction) and m data lines X1 each extending in the column direction (Y direction). ... To Xm, and a plurality of pixels 2 are arranged correspondingly to these intersections. When the display unit 1 is a monochrome panel, one pixel that is the minimum display unit of an image corresponds to one pixel 2 shown in FIG. On the other hand, in the case of a color panel in which one pixel on the image is composed of three sub-pixels (RGB), one sub-pixel corresponds to one pixel 2 shown in FIG.

  FIG. 2 is an equivalent circuit diagram of a pixel using liquid crystal. One pixel 2 includes a TFT 21 that is a switching element, a liquid crystal capacitor 22, and a storage capacitor 23. The source of the TFT 21 is connected to one data line X, and its gate is connected to one scanning line Y. Regarding the pixels 2 arranged in the same column, the sources of the respective TFTs 21 are connected to the same data line X. For the pixels 2 arranged in the same row, the gates of the respective TFTs 21 are connected to the same scanning line Y. The drain of the TFT 21 is commonly connected to a liquid crystal capacitor 22 and a storage capacitor 23 provided in parallel. The liquid crystal capacitor 22 includes a pixel electrode 22a, a counter electrode 22b to which a voltage Vcom is applied, and a liquid crystal layer sandwiched between these electrodes 22a and 22b. The storage capacitor 23 is formed between the pixel electrode 22a and a common capacitor electrode (not shown), and is supplied with a voltage Vcs. The storage capacitor 23 suppresses the influence of leakage of charges accumulated in the liquid crystal. On the other hand, a data voltage V or the like is applied to the pixel electrode 22a side via the TFT 21, and the liquid crystal capacitor 22 and the storage capacitor 23 are charged and discharged according to this voltage level. Thereby, the transmittance of the liquid crystal layer is set according to the potential difference (applied voltage of the liquid crystal) between the pixel electrode 22a and the counter electrode 22b, and the gradation of the pixel 2 is set.

  The pixels 2 are driven by AC driving in which the voltage polarity is inverted every predetermined period in order to extend the life of the liquid crystal. The voltage polarity is defined based on the direction of the electric field acting on the liquid crystal layer, in other words, based on the forward and reverse of the voltage applied to the liquid crystal layer. In the present embodiment, common DC driving, which is one type of AC driving, that is, the voltage Vcom applied to the counter electrode 22b and the voltage Vcs applied to one electrode of the storage capacitor 23 are kept constant, and the pixel A driving method is employed in which the polarity on the electrode 22a side is reversed.

  The control circuit 5 generates various internal signals from external signals such as a vertical synchronization signal Vs, a horizontal synchronization signal Hs, and a dot clock signal DCLK input from a host device (not shown), and based on these internal signals, scan lines are generated. The drive circuit 3 and the data line drive circuit 4 are synchronously controlled. Under this synchronization control, the scanning line driving circuit 3 and the data line driving circuit 4 perform display control of the display unit 1 in cooperation with each other. Here, as the internal signals important in relation to the present embodiment, there are data line drive system signals DX, CLX, LP, POL, MODE. The start pulse DX defines the timing for starting to take in data for one pixel row. The clock signal CLX is a dot clock signal for writing data to the pixel. Note that clock signals CLX1 and CLX2, which will be described later, are generated based on the clock signal CLX. The latch pulse LP is a pulse signal output at the beginning of 1H, and rises in a pulse shape when the level of the clock signal CLY transitions, that is, when it rises and falls. The polarity instruction signal POL is a signal for instructing the voltage polarity when the liquid crystal is AC driven. The mode signal MODE is a signal for instructing switching between the high resolution mode and the low resolution mode, and is at the L level in the high resolution mode, and at the H level in the low resolution mode in which display is performed at a lower resolution. Respectively. The display resolution is preferably switched according to the type of object to be displayed. For example, the high resolution mode is applied to a display area displaying a natural image, and the low resolution mode is applied to a display area displaying text such as characters. Further, for example, the high resolution mode is applied to a display area displaying a high definition font in the text portion. The display resolution may be set in a stepwise manner according to the usage status and the remaining battery level. For example, the area to which the low resolution mode is applied is gradually expanded as the remaining amount of the battery decreases. Furthermore, the same resolution mode may be applied to the entire display area of the display unit 1, but the resolution that differs for each partial area of the display unit 1 using the method described in the third embodiment to be described later. A mode may be applied.

  The scanning line driving circuit 3 is mainly composed of a shift register, an output circuit, and the like, and performs line sequential scanning for sequentially selecting the scanning lines Y1 to Yn in a predetermined order. Specifically, a start pulse DY supplied at the beginning of one frame (1F), which is a display period of one image, is transferred according to the clock signal CLY, and thereby the scanning signal output to each scanning line Y1 to Yn. Is set. The scanning signal takes a binary level, the scanning line Y corresponding to the pixel row to which data is to be written is set to a high voltage level (hereinafter referred to as “H level”), and the other scanning lines Y It is set to a low voltage level (hereinafter referred to as “L level”). A period during which one scanning line Y is maintained at the H level, that is, a period during which the scanning line Y is selected is one horizontal scanning period (1H). Along with the sequential selection of the scanning lines Y1 to Yn, in 1F, pixel rows to which data is to be written are sequentially selected every 1H.

  FIG. 3 is a configuration diagram of the data line driving circuit 4 to which the gradation data Din is input. The data line driving circuit 4 includes an X shift register 40 mainly having an m-stage shift register configuration, m circuit units 41a and 41b provided in units of data lines, and a data bus provided on the data bus. The latch 42 is configured. Note that the thick line in the figure indicates a set of lines corresponding to the number of bits of the gradation data Din, that is, a bus. Accordingly, each of the circuit elements 45 to 48 connected to the thick line actually exists in parallel by the number of lines constituting the bus, in other words, by the number of bits of the gradation data Din. Please note that.

  The X shift register 40 has a configuration in which a plurality of alternately provided latch circuits 43a and 43b are mainly used and a plurality of selectors 44 are added to form an m-stage shift register configuration. The latch circuits 43a existing in odd stages are commonly controlled by the first clock signal CLX1, and output latch signals S1, S3, S5,... For the first circuit unit 41a described later. There are as many latch circuits 43a as there are first circuit units 41a, and the latch circuits 43a are provided corresponding to the respective circuit units 41a. The latch circuit 43b existing in the even-numbered stage is commonly controlled by a second clock signal CLX2 different from the first clock signal CLX1, and latch signals S2, S4, S6 for the second circuit unit 41b described later. , ... are output. There are as many latch circuits 43b as there are second circuit units 41b, and they are provided corresponding to the respective circuit units 41b.

  The latch circuit 43a located at the odd-numbered stage (2k + 1) has the following configuration except for the first stage. That is, its own input terminal (D terminal) is connected to the output terminal (Q terminal) of the latch circuit 43b of the previous stage (2k) via the upper selector 44. In addition, its own output terminal is directly connected to the input terminal of the subsequent stage (2k + 2) latch circuit 43b, and is also connected to the input terminal of the subsequent stage (2K + 3) latch circuit 43a via the lower selector 44. Has been. The signal output from its own output terminal is supplied not only to the circuit elements 43b and 44 in the X shift register 40 but also to the first circuit unit 41a corresponding to the data line X2k + 1 as the latch signal S2k + 1. Is done. Note that a start pulse DX serving as a base when the latch signal S is generated is supplied to the input terminal of the first-stage latch circuit 43a. On the other hand, the other latch circuit 43b located at the even-numbered stage (2k) has the following configuration. That is, its own input terminal is directly connected to the output terminal of the preceding stage (2k-1) latch circuit 43a. Further, its own output terminal is connected to the input terminal of the latch circuit 43a in the subsequent stage (2k + 1) via the lower selector 44. The signal output from its own output terminal is supplied not only to the circuit element 44 in the X shift register 40 but also to the second circuit unit 41b corresponding to the data line X2k as the latch signal S2k.

  The selector 44 is provided between the output terminal of the even-numbered stage (2k) latch circuit 43b and the input terminal of the odd-numbered stage (2k + 1) latch circuit 43a, and has two input terminals and one output terminal. And. One input terminal of the selector 44 is connected to the output terminal of the latch circuit 43b located in the preceding stage, and the other output terminal is connected to the output terminal of the latch circuit 43a located in the preceding stage. Has been. The output terminal of the selector 44 is directly connected to the input terminal of the latch circuit 43a at the subsequent stage. The selector 44 selectively connects one input terminal of the self or the other input terminal of the self to the output terminal of the self. All the selectors 44 included in the X shift register 40 are similarly controlled by the mode signal MODE. When the mode signal MODE is at L level, that is, in the high resolution mode, the output terminal of the latch circuit 43b in the previous stage of the selector 44 and the input terminal of the latch circuit 43a in the subsequent stage are connected. In this case, all the latch circuits 43a and 43b included in the X shift register 40 cooperate to generate m latch signals S1 to Sm. On the other hand, when the mode signal MODE is at the H level, that is, in the low resolution mode, the output terminal of the latch circuit 43a before the selector 44 and the latch circuit 43a at the subsequent stage are connected. In this case, since the latch circuit 43b is skipped and only the latch circuit 43a operates, i (m> i> 1) latch signals S1, S3, S5,... Corresponding to the number of latch circuits 43a. Is generated.

  The first circuit unit 41a corresponding to the latch circuit 43a includes three circuit elements 45 to 47. The first latch circuit 45 is latch-controlled by one of the latch signals S1, S3, S5,..., And has gradation data Din output from the data bus latch 42 to the data bus at its input end. 'Is supplied. The output terminal of the first latch circuit 45 is connected to the input terminal of the second latch circuit 46, and is also connected to the selector 48 provided in the adjacent circuit unit 41b. The second latch circuit 46 is latch-controlled by a latch pulse LP, and its output terminal is connected to an input terminal of a DAC 47 that is an output circuit. The DAC 47 D / A converts the grayscale data Din ′ from the second latch circuit 46 and outputs a grayscale signal having the polarity designated by the polarity designation signal POL to the data line X.

  On the other hand, the second circuit unit 41b corresponding to the latch circuit 43b is common to the first circuit unit 41a in that the circuit elements 45 to 47 are provided, but a selector having two input terminals and one output terminal. 48 is further included. One input end of the selector 48 is connected to the output end of the first latch circuit 45 in the same circuit unit 41b, and the other input end is the first end in the adjacent first circuit unit 41a. The output terminal of the latch circuit 45 is connected. The output terminal of the selector 48 is connected to the input terminal of the second latch circuit 46. The selector 48 is conduction-controlled by the mode signal MODE, and selectively connects one of its own input terminals or its other input terminal to its own output terminal. When the mode signal MODE is at the L level (in the high resolution mode), in other words, when all the latch circuits 43a and 43b in the X shift register 40 cooperate, the input terminal of the second latch circuit 46 has An output signal from the first latch circuit 45 in the same circuit unit 41b is supplied. On the other hand, when the mode signal MODE is at the H level (in the low resolution mode), in other words, when only the latch circuit 43a operates, the input terminal of the second latch circuit 46 is adjacent to the first An output signal from the first latch circuit 45 in the circuit unit 41a is supplied.

  The data bus latch 42 functions as a holding circuit that holds the gradation data Din, and receives gradation data Din ′ from the gradation data Din from the host device under the control of the first clock signal CLX1. Output to the data bus. The data bus latch 42 continues to output the gradation data Din captured when the clock signal CLX1 is at the H level as the gradation data Din ′ when the clock signal CLX1 is at the L level.

  FIG. 4 is a timing chart of the data line driving system. First, the operation in the high resolution mode (MODE = L level) will be described. In the high resolution mode, the clock signals CLX1 and CLX2 are set to the same clock (that is, a clock waveform having the same period and synchronized). At the same time, the adjacent latch circuits 43a and 43b are connected by the selector 44 controlled by the mode signal MODE, so that all the latch circuits 43a and 43b in the X shift register 40 cooperate. The X shift register 40 sequentially transfers the start pulse DX supplied at the beginning of 1H according to the clock signals CLX1 and CLX2 synchronized with each other, and sequentially sets the levels of the m latch signals S1 to Sm to the H level exclusively. To do. On the other hand, the data bus latch 42 outputs d1, d2, d3, d4,... Serially input as the gradation data Din to the data bus as gradation data Din ′.

  In the high resolution mode, the output of the first latch circuit 45 in the same circuit unit 41b is directly input to the second latch circuit 46 by the selector 48 controlled by the mode signal MODE. That is, the second circuit unit 41b operates in the same manner as the circuit unit 41a without receiving data from the adjacent first circuit unit 41a, and generates a gradation signal in a self-contained manner. The m circuit units 41a and 41b perform simultaneous output of gradation signals for pixel rows in which data is written at a certain 1H, and dot-sequential latches of gradation data Din ′ relating to pixel rows to be written in the next 1H. Do it at the same time. The operations of the respective circuit units 41a and 41b are the same except that the fetch timing of the gradation data Din ′ defined by the latch signals S1, S2, S3,. That is, the first latch circuit 45 corresponding to the data line X1 has the gradation at the capture timing defined by the latch signal S1 among the gradation data d1, d2, d3, d4,. Latch data d1. Then, Dout1 = d1 continues to be output until new gradation data d1 is fetched at the next 1H. The first latch circuit 45 corresponding to the data line X2 latches the gradation data d2 at the fetch timing defined by the latch signal S2. Dout2 = d2 continues to be output until new gradation data d2 is fetched at the next 1H. The same applies to the first latch circuits 45 corresponding to the subsequent data lines X3, X4,..., And Dout3 = d3, Dout4 = d4,.

  The second latch circuit 46 in each of the circuit units 41a and 41b simultaneously captures and latches the outputs Dout1, Dout2,... Of the first latch circuit 45 at the capture timing defined by the latch pulse LP. . At the same time, the gradation data d1, d2,... In the next 1H are newly latched in the first latch circuit 45. The d1, d2, d3, d4,... Output from the respective second latch circuits 46 are subjected to D / A conversion by the DAC 47 and are converted into corresponding data lines X1, X2,. Output simultaneously to X3, X4,.

  Next, the operation in the low resolution mode (MODE = H level) will be described. In the low resolution mode, the first clock signal CLX1 is set to a longer cycle (in this embodiment, twice the cycle) than in the high resolution mode. At the same time, the second clock signal CLX2 is maintained at a level that sets the latch circuit 43b to the non-operating state, that is, the L level. In this case, the latch circuit 43b is skipped by the selector 44 controlled by the mode signal MODE, and the latch circuits 43a are connected to each other. As a result, the X shift register 40 has an i-stage shift register configuration that is substantially smaller than the m-stage in the high resolution mode. The X shift register 40 transfers the start pulse DX supplied at the beginning of 1H one by one according to the long-cycle clock signal CLX1, and sequentially sets the levels of the i latch signals S1, S3, S5,. Set to H level exclusively. On the other hand, the data bus latch 42 skips d1, d2, d3, d4,... Serially input as gradation data Din and skips them one by one to obtain d1, d3,. Output to the data bus.

  In the low resolution mode, unlike the high resolution mode, the output of the first latch circuit 45 in the adjacent first circuit unit 41 a becomes the input of the second latch circuit 46 by the selection of the selector 48. That is, the second circuit unit 41b receives data from the adjacent first circuit unit 41a and generates a gradation signal based on the data. Therefore, for example, regarding the circuit units 41a and 41b corresponding to the data lines X1 and X2, Dout1 = Dout2 = d1, and the same gradation signal is output to the data lines X1 and X2. For the circuit units 41a and 41b corresponding to the data lines X3 and X4, Dout3 = Dout4 = d3, and the same gradation signal is output to the data lines X3 and X4. Since other operations are the same as those in the high resolution mode, description thereof is omitted here.

  Thus, in the present embodiment, the operation of the data line driving circuit 4 is switched between the high resolution mode and the low resolution mode. In the low resolution mode, the data bus latch 42 thins out the gradation data Din, thins out the first clock signal CLX1, and stops the second clock signal CLX2. Then, the data line driving system is operated using i latch signals S1, S3, S5,... Less than in the high resolution mode. This makes it possible to reduce the power consumed by the shift register 40 and the first latch circuit 45 as compared to the case where the high resolution mode is uniformly applied.

  In this embodiment, the display control of the low resolution area is performed by thinning the clock on the data line driving circuit 4 side. Therefore, it is necessary to largely change the data transfer timing of the upper circuit that supplies the input signal thereto. Disappears. As a result, low power consumption can be realized without complicating the configuration of the upper circuit.

(Second Embodiment)
FIG. 5 is a circuit diagram of the data line driving circuit 4 according to the present embodiment. The data line driving circuit 4 is different from the configuration shown in FIG. 3 in the connection relationship of the circuit elements 45 to 48 in the second circuit unit 41b. That is, the output terminal of the first latch circuit 45 is connected to the input terminal of the second latch circuit 46. The selector 48 includes two input terminals and one output terminal. One input terminal of the selector 48 is connected to the output terminal of the second latch circuit 46 in the second circuit unit 41b, and the other input terminal is the second terminal in the adjacent first circuit unit 41a. The output terminal of the latch circuit 46 is connected. The output terminal of the selector 48 is connected to the input terminal of a DAC 47 that is an output circuit. The DAC 47 outputs a gradation signal corresponding to the gradation data output from the output terminal of the selector 48 to the data line X. Since the configuration other than this is the same as the configuration shown in FIG. 3, the same reference numerals are given and description thereof is omitted here. Further, the operation of the data line driving circuit 4 shown in FIG. 5 is the same as the timing chart shown in FIG.

  According to this embodiment, power consumption can be reduced for the same reason as in the first embodiment described above.

(Third embodiment)
The mode signal MODE instructing switching between the high resolution mode and the low resolution mode may be directly supplied from a CPU or LCD controller which is an upper circuit, but the command is generated by the mode generation circuit 6 provided in the electro-optical device. It may be generated on a base basis. As shown in FIG. 6, the command to be input to the mode generation circuit 6 includes four addresses HS, HE, VS, and VE to specify a designated area (area indicated by hatching) whose resolution is to be changed. Here, HS is a horizontal start address, and HE is a horizontal end address. VS is a vertical start address, and VE is a vertical end address.

  FIG. 7 is a block configuration diagram of the mode generation circuit 6. The mode generation circuit 6 includes a register 60, a horizontal counter 61, a vertical counter 62, and a comparison circuit 63. The register 60 holds addresses HS, HE, VS, and VE of designated areas for performing low resolution display or high resolution display on the display unit 1. The horizontal counter 61 counts the number of data in the horizontal direction based on the clock signal CLX. The count value counted by the horizontal counter 61 is reset by the input of the start pulse DX. The vertical counter 62 counts the number of data in the vertical direction based on the clock signal CLY. The comparison circuit 63 compares the count value obtained by the horizontal counter 61 and the count value obtained by the vertical counter 62 with the addresses HS, HE, VS, and VE held by the register 60, thereby determining whether or not the designated area. In the designated area, the mode signal MODE signal is set to, for example, the H level (low resolution mode).

  According to the present embodiment, the power consumption can be reduced for the same reason as the above-described embodiments, and the resolution mode can be switched on a command basis.

  In each of the above-described embodiments, the case where a liquid crystal element is used has been described as an example. However, the present invention is not limited to this, and an organic EL element, a digital micromirror device (DMD), or an FED ( It can also be applied to field emission display (SED) and surface-conduction electron-emitter display (SED).

  Further, the electro-optical device according to each of the above-described embodiments can be mounted on various electronic devices including, for example, a television, a projector, a mobile phone, a mobile terminal, a mobile computer, a personal computer, and the like. FIG. 8 is an external perspective view of the mobile phone 10 on which the electro-optical device according to each of the above-described embodiments is mounted as an example. The mobile phone 10 includes the above-described display unit 1 together with the earpiece 12 and the mouthpiece 13 in addition to the plurality of operation buttons 11. When the above-described electro-optical device is mounted on these electronic devices, the commercial value of the electronic devices can be further increased, and the product appeal of electronic devices in the market can be improved.

Block diagram of electro-optical device Equivalent circuit diagram of pixel using liquid crystal 1 is a configuration diagram of a data line driving circuit according to a first embodiment. Timing chart of data line drive system 2 is a configuration diagram of a data line driving circuit according to a second embodiment. Illustration of display area Block diagram of the mode generation circuit External perspective view of a mobile phone equipped with an electro-optical device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display part 2 Pixel 3 Scan line drive circuit 4 Data line drive circuit 5 Control circuit 6 Mode generation circuit 40 X shift register 41a 1st circuit unit 41b 2nd circuit unit 42 Data bus latch 43a, 43b Latch circuit 44 Selector 45 First latch circuit 46 Second latch circuit 47 DAC
48 selector

Claims (10)

In the data line drive circuit,
In the high resolution mode, m (m ≧ 2) gradation data serially supplied from the host device in a predetermined period is output to the data bus as it is, and in the low resolution mode in which the resolution is lower than the high resolution mode. A holding circuit that thins out a part of the m pieces of data and outputs i (m>i> 1) pieces of gradation data to the data bus;
In the high resolution mode, m latch signals that define the timing of capturing each of the m gradation data are generated, and in the low resolution mode, each of the i gradation data is captured. A shift register that generates i latch signals defining the timing;
In the high resolution mode, any one of the m pieces of gradation data output to the data bus is taken in at a take-in timing defined by any one of the m pieces of latch signals, and according to the gradation data. Output the gray scale signal to the data line, and at the time of the low resolution mode, the i gray scale data output to the data bus at the capture timing defined by any of the i latch signals. A first circuit unit that captures any one of the above and outputs a gradation signal corresponding to the gradation data to the data line;
In the high resolution mode, any one of the m pieces of gradation data output to the data bus is taken in at a take-in timing defined by any one of the m pieces of latch signals, and according to the gradation data. Output the gradation signal to a data line different from the output destination of the first circuit unit, and at the time of the low resolution mode, any one of the i gradation data captured in the first circuit unit. And a second circuit unit for outputting a gradation signal corresponding to the data line to the data line. The first circuit unit includes:
A first latch circuit having its own input connected to the data bus;
A second latch circuit having its own input terminal connected to the output terminal of the first latch circuit;
An output circuit for outputting to the data line a gradation signal corresponding to the gradation data output from the output terminal of the second latch circuit;
The second circuit unit includes:
A first latch circuit having its own input connected to the data bus;
One input terminal is connected to the output terminal of the first latch circuit in the second circuit unit, and the other input terminal is connected to the output terminal of the first latch circuit in the first circuit unit. And a first selector for selectively connecting the one input terminal or the other input terminal to its own output terminal;
A second latch circuit having its input terminal connected to the output terminal of the first selector;
2. The data line drive according to claim 1, further comprising: an output circuit that outputs a grayscale signal corresponding to the grayscale data output from the output terminal of the second latch circuit to the data line. circuit. The first circuit unit includes:
A first latch circuit having its own input connected to the data bus;
A second latch circuit having its own input terminal connected to the output terminal of the first latch circuit;
An output circuit for outputting to the data line a gradation signal corresponding to the gradation data output from the output terminal of the second latch circuit;
The second circuit unit includes:
A first latch circuit having its own input connected to the data bus;
A second latch circuit having its own input terminal connected to the output terminal of the first latch circuit;
One input terminal of the second latch circuit is connected to the output terminal of the second latch circuit in the second circuit unit, and the other input terminal of the second circuit unit is connected to the output terminal of the second latch circuit in the first circuit unit. And a first selector for selectively connecting the one input terminal or the other input terminal to its own output terminal;
2. The data line driving circuit according to claim 1, further comprising: an output circuit that outputs a gradation signal corresponding to the gradation data output from an output terminal of the first selector to the data line. 3. . The shift register is
a plurality of third latch circuits forming part of an m-stage shift register configuration and generating the latch signal for the first circuit unit;
A plurality of fourth latch circuits that form part of the m-stage shift register configuration and that generate the latch signal for the second circuit unit by alternately providing the third latch circuit,
One of its own input terminals is connected to the output terminal of the fourth latch circuit located in the preceding stage, and the other input terminal of its own is connected to the output terminal of the third latch circuit located in the preceding stage, A second selector having its own output terminal connected to the input terminal of the third latch circuit located in the subsequent stage and selectively connecting the one input terminal or the other input terminal to the output terminal The data line driving circuit according to claim 1, wherein the data line driving circuit includes: In the high resolution mode, the second selector connects a plurality of output terminals of the fourth latch circuit positioned in the previous stage and an input terminal of the third latch circuit positioned in the subsequent stage, thereby The third latch circuit and the plurality of fourth latch circuits cooperate to generate the m latch signals;
In the low resolution mode, the second selector connects the output terminal of the third latch circuit located in the preceding stage and the input terminal of the third latch circuit located in the succeeding stage, 5. The data line driving circuit according to claim 4, wherein a plurality of the third latch circuits operate to generate the i number of latch signals. The third latch circuit operates with a first clock signal, the fourth latch circuit operates with a second clock signal,
In the high resolution mode, the first clock signal and the second clock signal are set to the same clock,
In the low resolution mode, the first clock signal is set to a longer cycle than in the high resolution mode, and the second clock signal sets the fourth latch circuit to a non-operating state. 6. The data line driving circuit according to claim 5, wherein the data line driving circuit is maintained at a level. In an electro-optical device,
A plurality of scan lines;
Multiple data lines,
A display unit in which a plurality of pixels are arranged corresponding to positions of intersections of the plurality of scanning lines and the plurality of data lines;
A scanning line driving circuit for sequentially selecting the plurality of scanning lines;
In cooperation with the scanning line driving circuit, a data line driving circuit that outputs gradation signals to the plurality of data lines,
The electro-optical device, wherein the data line driving circuit is the data line driving circuit according to claim 1. A mode signal generation circuit for generating a mode signal instructing switching between the high resolution mode and the low resolution mode;
The mode signal generation circuit includes:
A register for holding an address of a designated area for performing low resolution display or high resolution display in the display unit;
A horizontal counter that counts the number of data in the horizontal direction;
A vertical counter that counts the number of data in the vertical direction;
The comparison circuit according to claim 7, further comprising: a comparison circuit that generates the mode signal by comparing the count value by the horizontal counter and the count value by the vertical counter with the address held by the register. Electro-optical device.   The electro-optical device according to claim 8, wherein the mode signal generation circuit generates the mode signal in accordance with a usage state or a remaining battery level.   An electronic apparatus comprising the electro-optical device according to claim 7.

Images