CN114564421B - Method and system for training high-speed memory - Google Patents
Method and system for training high-speed memory Download PDFInfo
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Abstract
The application discloses a method and a system for training a high-speed memory, relates to the technical field of chip design, and particularly relates to the field of high-speed memory training. The application enables the memory system to work at a relatively low frequency, and performs memory initialization and memory parameter training at the low frequency. After the low-frequency memory parameter training is completed, calculating the delay time required to compensate each signal according to the training result, wherein the delay time is required to meet the bus equal length. And taking the calculated compensation delay time as an initial value of the high-speed memory training. And then the memory system is tuned to a high-speed mode to perform memory initialization, and memory training is performed according to the initial value to obtain an optimal value under the high-speed condition. The application can reduce the requirement of the delay time of external signals and the like, thereby reducing the realization difficulty of a high-speed memory system on the rear end of a chip and a PCB layout.
Description
Technical Field
The application relates to the field of high-speed memory training, in particular to a method and a system for high-speed memory training.
Background
With the increasing capacity and bandwidth demands of various electronic products on a memory (SDRAM), the access speed of the memory is also required to be higher and higher, and the speed and stability of the memory become important indicators of consumer electronic products.
Because the working frequency of the memory is high, the bus bit width (including a data bus, an address bus and a command bus) is also relatively wide, and the delay time of the memory signal is influenced by the differences of the packaging process, the PCB wiring and the external environment such as temperature and voltage. Therefore, the memory controller has some parameter configuration for the memory bus signal, and the parameter configuration needs to be configured to an appropriate optimal value to ensure the stability of the memory system. When the environment is different, the wiring is different, the packaging process is different, and the optimal value of the parameter is also different. The memory training is to find the best value of the parameter.
However, in the prior art, delay time of external signals is often required to be equal in length in the high-speed memory training process, which is not beneficial to realization of the high-speed memory system on the back end of the chip and the PCB layout.
Disclosure of Invention
Aiming at the defects in the prior art, the application provides a method and a system for training a high-speed memory, which enable a memory system to work at a relatively low frequency and perform memory initialization and memory parameter training at the low frequency. After the low-frequency memory parameter training is completed, calculating the delay time required to compensate each signal according to the training result, wherein the delay time is required to meet the bus equal length. And taking the calculated compensation delay time as an initial value of the high-speed memory training. And then the memory system is tuned to a high-speed mode for memory initialization, and memory training is carried out according to the initial value to obtain the optimal value under the high-speed condition. The complexity of the high-speed memory training algorithm can be reduced, so that the cost of the chip is reduced.
In order to achieve the above object, the present application can be realized by the following technical scheme:
a method of high speed memory training, comprising:
completing a parameter training process of hardware at a frequency point of a first transmission speed to obtain a parameter result at the first transmission speed;
obtaining a parameter initial value at a second transmission speed according to a parameter result at the first transmission speed, wherein the second transmission speed is higher than the first transmission speed;
and completing the parameter training process of the hardware under the frequency point of the second transmission speed according to the parameter initial value under the second transmission speed.
The method for training the high-speed memory further completes the parameter training process of the hardware under the frequency point of the first transmission speed, and the method comprises the following steps: and (3) training the CA bus memory parameters, and/or training the data bus read related parameters, and/or training the data bus write related parameters.
In the method for training the high-speed memory, the initial value of the parameter further comprises delay time required by compensating the equal length of the address bus and the data bus.
The method for training the high-speed memory further includes: the delay time required to be compensated for the CA bus to achieve equal length, the delay time required to be compensated for the data bus to achieve equal length, and/or the delay time required to be compensated for the data bus to be written to achieve equal length.
The method for training the high-speed memory further includes: and training the CA bus memory parameter according to the compensated value, and/or training the data bus read related parameter according to the compensated value, and/or training the data bus write related parameter according to the compensated value.
In the method for training the high-speed memory, further, the parameters of the parameter training process include a memory address bus parameter and a data bus parameter.
A system for high-speed memory training, comprising:
the central processing unit is used for processing the data,
the memory controller receives the configuration instruction of the central processing unit and is used for completing the following work:
completing a parameter training process of hardware at a frequency point of a first transmission speed to obtain a parameter result at the first transmission speed;
obtaining a parameter initial value at a second transmission speed according to a parameter result at the first transmission speed, wherein the second transmission speed is higher than the first transmission speed;
and completing the parameter training process of the hardware under the frequency point of the second transmission speed according to the parameter initial value under the second transmission speed.
The system for high-speed memory training as described above, further, the memory controller includes: the PHY module comprises a data receiving and transmitting module, a delay module and an IO module, wherein,
the initialization module is used for sending an initialization instruction to an SDRAM chip outside the memory controller;
the parameter training module is used for training parameters required by the delay module;
the parameter training module is used for training a CA bus, and/or training a data bus reading function and/or training a data bus writing function, and after each training is finished, an optimal value of a corresponding delay parameter is calculated and is sent to the delay module;
the command conversion module is used for sending the instructions sent by the initialization module and the parameter training module to a data transceiver module in the PHY module according to set protocol requirements and set time sequences;
the data transceiver module in the PHY module is used for sending CA, sending data DQ and receiving data DQ;
the delay module is used for delaying the received and transmitted signals to a certain extent according to the configured parameters, then sending the signals to the IO module, and delaying the signals received from the IO module and then sending the signals to the data receiving and transmitting module;
the initial parameter calculation module is used for calculating delay time required by the realization of equal length of the compensation address bus and the data bus according to the result of the low-frequency parameter training.
The system for training the high-speed memory as described above, further, the types of the memory include: DDR1, or DDR2, or DDR3, or DDR4, or LPDDR2, or LPDDR3, or LPDDR4.
The system for high-speed memory training as described above, further, the second transmission speed includes: LPDDR4-3200Mbps, DDR3-2133Mbps, or LPDDR3-2133Mbps.
Compared with the prior art, the application has the beneficial effects that: the application can reduce the requirement of the delay time of external signals and the like, thereby reducing the realization difficulty of a high-speed memory system on the rear end of a chip and a PCB layout. The complexity of the high-speed memory training algorithm can be reduced, so that the cost of the chip is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly explain the drawings needed in the embodiments, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a diagram of the relationship between CK/DQS and CA Bus/DQ Bus sent by a sender;
FIG. 2 is a diagram showing the relationship between the CK/DQS and CA Bus/DQ Bus that the receiving end wishes to receive;
FIG. 3 is a diagram showing the relationship between CK/DQS and CA Bus/DQ Bus actually received by the receiving end (before parameter training);
FIG. 4 is a diagram showing the relationship between CK/DQS and CA Bus/DQ Bus actually received by the receiving end (after parameter training);
FIG. 5 shows the relationship between CK/DQS and CA Bus/DQ Bus actually received by the receiving end at high frequency (before parameter training)
FIG. 6 is a system block diagram of an embodiment of the present application;
FIG. 7 is a flow chart of a method of implementing an embodiment of the present application;
FIG. 8 is a graph showing the relationship between CK/DQS and CA Bus/DQ Bus actually received by the receiver (before parameter training) at high frequency after compensating for the delay time.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Examples:
it should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.
In order to better reveal the technical concept of the present application and to clarify the improvements of the present application, the technical difficulties faced by the present application will now be elucidated:
the memory training is to find the optimal value of the memory controller parameter. For example, FIG. 1 is a graph of the CK/DQS versus CA bus/DQ bus that the sender theoretically sends out, where CK and DQS are both differential signals, sampled on both upper and lower edges. The CK/DQS is in phase with the CA bus/DQ bus when sent out by the sender. FIG. 2 is a graph of the relationship of the CK/DQS and CA bus/DQ buses that the receiving end theoretically wishes to receive, where CK and DQS are both differential signals, and upper and lower edge double sampling. For more stable data reception, the receiving end expects the CK/DQS to be 90 degrees phase relationship with the CA bus/DQ bus. Ideally, only one 90 degree phase relationship adjustment is required for either the CK/DQS or CA bus/DQ buses. However, in practice, after the IO and the PCB have passed, each signal has a certain delay due to the influence of various external environments, and after the various delays, the signal received by the receiving end is shown in fig. 3. In fig. 3 Tskew represents the absolute shift of the delay time of the bus signal, and the actual signal will have a slope, and the actual eye diagram is Teye. The memory controller adjusts the delay time of the signal, the eye pattern of the bus signal, and the phase of the CK/DQS and CA bus/DQ buses by some parameters. The memory training is to find the best parameter value through training, and realize the largest eye diagram and the smallest absolute delay difference value. After the memory parameter training and adjustment, the relation between the CK/DQS and the CA bus/DQ bus actually received by the receiving end is shown in FIG. 4.
The memory training may be software training or hardware training. Hardware training can increase the speed of training. However, whether the software training or the hardware training is performed, the delay time of the external signal (the signal delay time in the chip plus the delay time of the external PCB) is required to be as long as possible, or the absolute offset Tskew of the delay time of the bus signal is within a certain range. This range is typically related to the operating frequency, and if the memory operating frequency is not high, the absolute offset requirement may be greater, and if the memory speed is relatively high, the absolute offset requirement may be relatively less.
As shown in fig. 5, in the high frequency situation, the ratio of Tskew to one CK/DQS period is relatively high, if the memory training is to be successfully trained to obtain the optimal value in the high speed situation, the requirement on absolute offset is often required to be increased, the buses are required to be equal in length, and the complexity of the memory training algorithm is required to be increased, so that the optimal parameter value is obtained, and stable operation can be ensured in the situation that the high frequency exists.
In the case where the memory is operated at high speed and the bus signals are not of equal length. The direct access is difficult to train the result through high-speed memory training, and the optimal value of the parameter is obtained. In this case, the system requires another indirect training mode. I.e., first operating the memory system at a relatively low frequency, such as 40% to 60% of the target speed. And initializing the memory at low frequency and training the memory. After the low-frequency memory training is completed, calculating the delay time required to be compensated for each signal if the buses are equal in length according to the training result. And taking the calculated compensation delay time as an initial value of the high-speed memory training. And then the memory system is tuned to a high-speed mode to perform memory initialization, and memory training is performed according to the compensated initial value to obtain an optimal value under the high-speed condition.
Referring to fig. 6-8, the present application provides a method and system for high-speed memory training, which first enables a memory system to work at a relatively low frequency, and performs memory initialization and memory parameter training at the low frequency. After the low-frequency memory parameter training is completed, calculating the delay time required to compensate each signal according to the training result, wherein the delay time is required to meet the bus equal length. And taking the calculated compensation delay time as an initial value of the high-speed memory training. And then the memory system is tuned to a high-speed mode for memory initialization, and memory training is carried out according to the initial value to obtain the optimal value under the high-speed condition. The complexity of the high-speed memory training algorithm can be reduced, so that the cost of the chip is reduced.
A method of high-speed memory training, which may include the steps of:
step 101: completing a parameter training process of hardware at a frequency point of a first transmission speed to obtain a parameter result at the first transmission speed;
step 102: and obtaining a parameter initial value at a second transmission speed according to a parameter result at the first transmission speed, wherein the second transmission speed is higher than the first transmission speed. The first transmission speed may be referred to as a low speed or a relatively low speed, and the second transmission speed may be referred to as a high speed or a relatively high speed, wherein the low speed is a relatively intermediate speed that is lower than the highest speed achieved by the current system, but is not limited to a range of low speeds or to a fixed speed.
Step 103: and completing the parameter training process of the hardware under the frequency point of the second transmission speed according to the parameter initial value under the second transmission speed.
As an alternative implementation, in some embodiments, a method for training a high-speed memory may include the following steps:
step 201: completing a parameter training process of hardware at a frequency point of a first transmission speed to obtain a parameter result at the first transmission speed; the method for completing the parameter training process of the hardware under the frequency point of the first transmission speed comprises the following steps: and (3) training the CA bus memory parameters, and/or training the data bus read related parameters, and/or training the data bus write related parameters.
Step 202: and obtaining a parameter initial value at a second transmission speed according to a parameter result at the first transmission speed, wherein the second transmission speed is higher than the first transmission speed. The first transmission speed may be referred to as a low speed or a relatively low speed, and the second transmission speed may be referred to as a high speed or a relatively high speed, wherein the low speed is a relatively intermediate speed that is lower than the highest speed achieved by the current system, but is not limited to a range of low speeds or to a fixed speed.
Step 203: and completing the parameter training process of the hardware under the frequency point of the second transmission speed according to the parameter initial value under the second transmission speed.
As an alternative implementation, in some embodiments, a method for training a high-speed memory may include the following steps:
step 301: completing a parameter training process of hardware at a frequency point of a first transmission speed to obtain a parameter result at the first transmission speed; the method for completing the parameter training process of the hardware under the frequency point of the first transmission speed comprises the following steps: and (3) training the CA bus memory parameters, and/or training the data bus read related parameters, and/or training the data bus write related parameters.
Step 302: and obtaining a parameter initial value at a second transmission speed according to a parameter result at the first transmission speed, wherein the second transmission speed is higher than the first transmission speed. The first transmission speed may be referred to as a low speed or a relatively low speed, and the second transmission speed may be referred to as a high speed or a relatively high speed, wherein the low speed is a relatively intermediate speed that is lower than the highest speed achieved by the current system, but is not limited to a range of low speeds or to a fixed speed. The initial values of the parameters include delay times required to compensate for the equal length of the address bus and the data bus.
Step 303: and completing the parameter training process of the hardware under the frequency point of the second transmission speed according to the parameter initial value under the second transmission speed.
As an alternative implementation, in some embodiments, a method for training a high-speed memory may include the following steps:
step 401: completing a parameter training process of hardware at a frequency point of a first transmission speed to obtain a parameter result at the first transmission speed; the method for completing the parameter training process of the hardware under the frequency point of the first transmission speed comprises the following steps: and (3) training the CA bus memory parameters, and/or training the data bus read related parameters, and/or training the data bus write related parameters.
Step 402: and obtaining a parameter initial value at a second transmission speed according to a parameter result at the first transmission speed, wherein the second transmission speed is higher than the first transmission speed. The first transmission speed may be referred to as a low speed or a relatively low speed, and the second transmission speed may be referred to as a high speed or a relatively high speed, wherein the low speed is a relatively intermediate speed that is lower than the highest speed achieved by the current system, but is not limited to a range of low speeds or to a fixed speed. The parameter initial value includes delay time required for compensating the address bus and the data bus, and further includes: the delay time required to be compensated for the CA bus to achieve equal length, the delay time required to be compensated for the data bus to achieve equal length, and/or the delay time required to be compensated for the data bus to be written to achieve equal length.
Step 403: and completing the parameter training process of the hardware under the frequency point of the second transmission speed according to the parameter initial value under the second transmission speed.
As an alternative implementation, in some embodiments, a method for training a high-speed memory may include the following steps:
step 501: completing a parameter training process of hardware at a frequency point of a first transmission speed to obtain a parameter result at the first transmission speed; the method for completing the parameter training process of the hardware under the frequency point of the first transmission speed comprises the following steps: and (3) training the CA bus memory parameters, and/or training the data bus read related parameters, and/or training the data bus write related parameters.
Step 502: and obtaining a parameter initial value at a second transmission speed according to a parameter result at the first transmission speed, wherein the second transmission speed is higher than the first transmission speed. The first transmission speed may be referred to as a low speed or a relatively low speed, and the second transmission speed may be referred to as a high speed or a relatively high speed, wherein the low speed is a relatively intermediate speed that is lower than the highest speed achieved by the current system, but is not limited to a range of low speeds or to a fixed speed. The parameter initial value includes delay time required for compensating the address bus and the data bus, and further includes: the delay time required to be compensated for the CA bus to achieve equal length, the delay time required to be compensated for the data bus to achieve equal length, and/or the delay time required to be compensated for the data bus to be written to achieve equal length.
Step 503: and completing the parameter training process of the hardware under the frequency point of the second transmission speed according to the parameter initial value under the second transmission speed. The parameter training process of the hardware under the frequency point of the second transmission speed comprises the following steps: and training the CA bus memory parameter according to the compensated value, and/or training the data bus read related parameter according to the compensated value, and/or training the data bus write related parameter according to the compensated value.
The system for implementing the application is shown in figure 6,
the system consists of three modules: a Central Processing Unit (CPU) 601, a memory controller 602, and an SDRAM chip 603.
A Central Processing Unit (CPU) 601 is used to configure a memory controller 602.
The SDRAM chip 603 is an external memory chip.
The memory controller 602 includes an initialization module 604, a parameter training module 605, an initial parameter calculation module 606, a command conversion module 607, and a PHY module 608. The PHY module 608 further includes a data transceiver module 609, a delay module 610, and an IO module 611.
The initialization module 604 is responsible for sending commands related to initializing the external SDRAM chip 603. The parameter training module 605 is responsible for training the parameters required by the delay module 610. The parameter training module 605 includes training of the CA bus, training of the data bus read function, and training of the data bus write function. After each training is finished, the optimal value of the corresponding delay parameter is calculated. The optimal value is fed to the delay module 610.
The command conversion module 607 transmits the commands issued by the initialization module 604 and the parameter training module 605 to the data transceiver module 609 of the PHY module 608 according to the JEDEC protocol requirements and according to a specified timing sequence. The data transceiver module 609 inside the PHY module 608 mainly includes transmission of CA, transmission of data DQ, and reception of data DQ. The delay module 610 includes a delay module corresponding to each of the CA buses, a delay module corresponding to each of the read data buses DQS and DQ, and a delay module corresponding to each of the write data buses DQS and DQ. The delay modules delay the received and transmitted signals to a certain extent according to the configured parameters and send the signals to the IO. Or the signals received from the IO are delayed to a certain extent and then sent to the data transceiver module.
The initial parameter calculation module 606 calculates the delay time required for compensating the equal length of the address bus and the data bus according to the result of the low frequency parameter training. If the module is not available, the result of the low-frequency parameter training can be read through software, and then the delay time required by compensating the address bus and the data bus to have equal length is calculated. The delay time to be compensated is configured into the memory controller.
As an optional implementation manner, in some embodiments, the type of the memory includes: DDR1, or DDR2, or DDR3, or DDR4, or LPDDR2, or LPDDR3, or LPDDR4.
As an alternative implementation, in some embodiments, the second transmission speed includes: LPDDR4-3200Mbps, DDR3-2133Mbps, or LPDDR3-2133Mbps.
Referring to fig. 7, as an alternative implementation, in some embodiments, a method for training a high-speed memory may include the following steps:
step 701, the DDRC system works at a low frequency, initializes the memory according to the configuration, then enters the training module, and starts to prepare to train the parameters.
Step 702, the training of the memory parameters of the CA bus is completed under the low frequency. CA bus memory parameter training is not required for all particle types, such as LPDDR3 and LPDDR4, which require training of the CA bus, and other particle types are not required.
Step 703, completing training of data bus read related parameters under low frequency.
Step 704, completing training of writing related parameters to the data bus at low frequency.
Step 705, calculating the delay time of the CA bus to be compensated for equal length according to the CA bus training result.
Step 706, calculating the delay time required to be compensated for by the read-related data lines (including RDQ, RDQS/RDQSN, RDBI) according to the training result of the read-related parameters of the data bus.
Step 707, calculating the delay time required to be compensated for by the write-related data lines (including WDQ, WDQS/WDQSN, WDMI/WDBI) according to the training result of the write-related parameters of the data bus.
Steps 705 to 707 may be performed in parallel by hardware, or may be performed in series by software.
Step 708, writing the compensation delay time calculated in step 705 to step 707 into the corresponding position of the delay register.
Step 709, the DDRC system switches to work at high frequency, initializes when there is high frequency in the configuration pair, then enters into the training module, and starts to prepare to train parameters.
As shown in fig. 8, in the case of high frequency, tskew is greatly reduced after completing the low frequency parameter compensation to high frequency, compared with the Tskew before compensation, so that successful parameter training at high frequency can be ensured.
Step 710, training the CA bus memory parameter according to the compensated value at high frequency.
Step 711, training the data bus read related parameters according to the compensated value at high frequency.
Step 712, training the data bus write related parameters according to the compensated value at high frequency.
Step 713, after the high-frequency training is completed, the normal working mode can be entered, and other modules can read and write DDR normally.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The above embodiments are only for illustrating the technical concept and features of the present application, and are intended to enable those skilled in the art to understand the content of the present application and implement the same, and are not intended to limit the scope of the present application. All equivalent changes or modifications made in accordance with the essence of the present application are intended to be included within the scope of the present application.
Claims (10)
1. A method for high-speed memory training, comprising:
completing a parameter training process of hardware at a frequency point of a first transmission speed to obtain a parameter result at the first transmission speed;
obtaining a parameter initial value at a second transmission speed according to a parameter result at the first transmission speed, wherein the second transmission speed is higher than the first transmission speed;
and completing the parameter training process of the hardware under the frequency point of the second transmission speed according to the parameter initial value under the second transmission speed.
2. The method for training the high-speed memory according to claim 1, wherein completing the parameter training process of the hardware at the frequency point of the first transmission speed comprises: and (3) training the CA bus memory parameters, and/or training the data bus read related parameters, and/or training the data bus write related parameters.
3. The method of claim 1, wherein the initial value of the parameter comprises a delay time required to compensate for an equal length of an address bus and a data bus.
4. The method for training the high-speed memory according to claim 3, wherein the initial value of the parameter at the second transmission speed comprises: the delay time required to be compensated for the CA bus to achieve equal length, the delay time required to be compensated for the data bus to achieve equal length, and/or the delay time required to be compensated for the data bus to be written to achieve equal length.
5. The method for training the high-speed memory according to claim 4, wherein the parameter training process of the hardware at the frequency point of the second transmission speed comprises: and training the CA bus memory parameter according to the compensated value, and/or training the data bus read related parameter according to the compensated value, and/or training the data bus write related parameter according to the compensated value.
6. The method of any one of claims 1-5, wherein the parameters of the parameter training process include a memory address bus parameter and a data bus parameter.
7. A system for high-speed memory training, comprising:
the central processing unit is used for processing the data,
the memory controller receives the configuration instruction of the central processing unit and is used for completing the following work:
completing a parameter training process of hardware at a frequency point of a first transmission speed to obtain a parameter result at the first transmission speed;
obtaining a parameter initial value at a second transmission speed according to a parameter result at the first transmission speed, wherein the second transmission speed is higher than the first transmission speed;
and completing the parameter training process of the hardware under the frequency point of the second transmission speed according to the parameter initial value under the second transmission speed.
8. The system for high-speed memory training of claim 7, wherein the memory controller comprises: the PHY module comprises a data receiving and transmitting module, a delay module and an IO module, wherein,
the initialization module is used for sending an initialization instruction to an SDRAM chip outside the memory controller;
the parameter training module is used for training parameters required by the delay module;
the parameter training module is used for training a CA bus, and/or training a data bus reading function and/or training a data bus writing function, and after each training is finished, an optimal value of a corresponding delay parameter is calculated and is sent to the delay module;
the command conversion module is used for sending the instructions sent by the initialization module and the parameter training module to a data transceiver module in the PHY module according to set protocol requirements and set time sequences;
the data transceiver module in the PHY module is used for sending CA, sending data DQ and receiving data DQ;
the delay module is used for delaying the received and transmitted signals to a certain extent according to the configured parameters, then sending the signals to the IO module, and delaying the signals received from the IO module and then sending the signals to the data receiving and transmitting module;
the initial parameter calculation module is used for calculating delay time required by the realization of equal length of the compensation address bus and the data bus according to the result of the low-frequency parameter training.
9. The system for high-speed memory training according to any of claims 7-8, wherein the type of memory comprises: DDR1, or DDR2, or DDR3, or DDR4, or LPDDR2, or LPDDR3, or LPDDR4.
10. The system for high-speed memory training of any of claims 7-8, wherein the second transmission speed comprises: LPDDR4-3200Mbps, DDR3-2133Mbps, or LPDDR3-2133Mbps.
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