CN102890663A - Data transmitting method and time delay module - Google Patents
Data transmitting method and time delay module Download PDFInfo
- Publication number
- CN102890663A CN102890663A CN2011102055490A CN201110205549A CN102890663A CN 102890663 A CN102890663 A CN 102890663A CN 2011102055490 A CN2011102055490 A CN 2011102055490A CN 201110205549 A CN201110205549 A CN 201110205549A CN 102890663 A CN102890663 A CN 102890663A
- Authority
- CN
- China
- Prior art keywords
- data
- transmission
- time
- delay time
- propagation delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 39
- 230000005540 biological transmission Effects 0.000 claims abstract description 168
- 238000001514 detection method Methods 0.000 claims abstract description 77
- 238000012360 testing method Methods 0.000 claims description 109
- 239000011159 matrix material Substances 0.000 claims description 36
- 230000001143 conditioned effect Effects 0.000 claims description 5
- 230000003111 delayed effect Effects 0.000 abstract 1
- 230000001429 stepping effect Effects 0.000 description 15
- 206010012186 Delayed delivery Diseases 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 230000000630 rising effect Effects 0.000 description 9
- 230000008569 process Effects 0.000 description 4
- 239000000047 product Substances 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention provides a data transmitting method and a time delay module. The data transmitting method comprises following steps of setting a transmission delay time initial value of a delay transmission module between a first data terminal and a second data terminal; adjusting the transmission delay time for multiple times so as to detect the transmission data for multiple times, and acquiring a detection result corresponding to each transmission delay time; selecting an optimum detection result from the detection results corresponding to each transmission delay time; and setting the transmission delay time corresponding to the optimum detection result as the optimum transmission delay time of the delay transmission module, so that the data transmission between the first data terminal and the second data terminal is delayed through the optimum transmission delay time. Through the data transmitting method and the time delay module, the data transmission delay time can be automatically adjusted, and the data transmission completeness and accuracy can be guaranteed.
Description
Technical field
The present invention relates to data communication field, relate in particular to a kind of data transmission method and time delay module.
Background technology
In general, processor (such as CPU or DSP etc.) all can be integrated with Memory Controller Hub on the application veneer of base station, core net, and the plug-in memory chip of the common meeting of this Memory Controller Hub is for the storage data.Can carry out the transmission of data between Memory Controller Hub and the memory chip.When Memory Controller Hub sent write order, data were transferred to memory chip from Memory Controller Hub.When Memory Controller Hub sent read command, data were sent to Memory Controller Hub and are processed by processor from memory chip.
Memory chip uses synchronous DRAM (SDRAM) usually, is the need of work synchronous clock of storer synchronously.And double data stream SDRAM (DDR SDRAM) can both carry out the transmission of data at rising edge (rising edge) and the negative edge (falling edge) of clock, is that memory chip institute extensively adopts, so followingly be described as an example of the DDR chip example.
When Memory Controller Hub sent reading command, the selected plug-in DDR chip of processor can begin driving data signal (DQ signal) and data strobe (Data Strobe) signal (being called for short the DQS signal), and the DDR chip is regarded as transmitting terminal.When Memory Controller Hub sends when writing instruction, then drive DQ signal and DQS signal by Memory Controller Hub, and Memory Controller Hub is regarded as transmitting terminal.The DQS signal is two-way, and it is the synchronizing clock signals of data, transmits corresponding DQS signal of per 8 DQ signals of a byte (Byte).Be used for distinguishing accurately each transmission cycle, and be convenient to the accurate receive data of take over party.
Fig. 1 is receiving end DQ signal and DQS signal timing diagram under the perfect condition.In ideal conditions, receiving end DQ signal (DQ0～DQ7 the is a Byte) central authorities of signal must be aligned in rising edge or the negative edge of DQS signal (DQS0), guaranteeing maximum sequential allowance, thereby ensure integrality and the accuracy of sampled data.Yet, because the wiring (lay out) of the Memory Controller Hub of the various processors that each manufacturer dispatches from the factory is different, in addition in the veneer actual application, be subjected to the impact of the factors such as change, chip power supply voltage of environment temperature, transmission line resistive performance, the DQ signal is not identical with the transmission delay (propagation delay) of DQS signal yet, thus cause that data can't be correct write the DDR chip or can't be correct read by the DDR chip.
Fig. 2 has showed the actual DQ signal of receiving of a receiving end and DQS signal timing diagram.When DQ signal and DQS signal are transferred to receiving end, usually can shine into DQ signal central authorities and can't align with the DQS signal.When the DQS signal transmission delay is very serious, might cause data correctly to transmit, namely can't carry out the correct read-write of DDR chip.
For the plug-in DDR chip from different vendor of different processor all can be read and write smoothly, single board design personnel are in research and development veneer process, must buy the DDR chip of various different vendors in advance and be welded on the veneer, all signal wires of ddr interface with these DDR chips and processor chips are connected to oscillograph again, then test the signal quality under these DDR chip operation states.Because the factors such as different processors and the wiring difference of DDR chip, DDR chip rate grade difference, environment temperature, chip power supply voltage there are differences, some DDR chip can't read or write smoothly, the tester judges according to the test signal quality, and replaces the DDR chip that these can't be read and write smoothly.
And when the kind of processor memory controller and DDR chip is a lot, to make efficient become low by manual testing's signal and queueing problem, and (have a long way to go such as test environment) when the actual working environment of veneer changes, DDR chip plug-in on the veneer by test also possibly can't correctly be read and write.
Summary of the invention
For realizing the automatic adjusting in propagation delay time, the embodiment of the invention provides a kind of data transmission method and time delay module.
For solving the problems of the technologies described above, it is as follows to the invention provides scheme:
A kind of data transmission method comprises:
Delay transport module between the first data terminal and the second data terminal obtains the initial value in propagation delay time, and the described propagation delay time is the time-delay that described delay transport module is applied to the transmission of data between described the first data terminal and the second data terminal;
Described delay transport module obtains testing result corresponding to each propagation delay time by the repeatedly adjustment in described propagation delay time being carried out the repeated detection of the transmission of data;
Described delay transport module is selected the optimal detection result in testing result corresponding to described each propagation delay time;
The propagation delay time that described delay transport module is corresponding with described optimal detection result, be set to the optimal transmission time delay of described delay transport module, make data transmission between described the first data terminal and the second data terminal through the delay of time delay of described optimal transmission.
Preferably, in the above-mentioned data transmission method,
Before repeatedly adjusting of described propagation delay time carried out the repeated detection of the transmission of data, described method further comprised:
Described delay transport module detects the frequency of the data strobe signal of described the transmission of data;
Described delay transport module carries out frequency division to described frequency, determines the step units time;
The repeatedly adjustment in described propagation delay time comprises:
Described step value is repeatedly adjusted;
On the basis of described initial value, increase or reduce the product of described step units time and step value, the propagation delay time after being adjusted.
Preferably, in the above-mentioned data transmission method, the divide ratio that described frequency is carried out frequency division is N, and N is the natural number greater than 1;
Described delay transport module specifically comprises by the repeated detection of carrying out the transmission of data of repeatedly adjusting to the described propagation delay time:
Whether the every acquisition one-time detection of described delay transport module result judges described step value less than N, if described step value less than N, progressively increases described step value, and continues the data that receive are detected; If described step value equals N, then continue in testing result corresponding to described each propagation delay time, to select optimal detection result's step.
Preferably, in the above-mentioned data transmission method, the described propagation delay time comprises:
Described the first data terminal receives the receive delay time of described the second data that data terminal sends and the transmission lag time that described the first data terminal is sent to described the second data terminal data;
Described delay transport module obtains testing result corresponding to each propagation delay time and specifically comprises by the repeatedly adjustment in described propagation delay time being carried out the repeated detection of the transmission of data:
Adjust described receive delay time and transmission lag time and carry out the repeated detection of the transmission of data, obtain each testing result that detects, wherein, when data transmission fails occurs in the either direction of the first data terminal to the second data terminal or the second data terminal to the first data terminal, described testing result is bust this, when the data transmission success all occured on the both direction of the first data terminal to the second data terminal and the second data terminal to the first data terminal, described testing result was transmission success;
Take the receive delay time as row-coordinate, the transmission lag time is the row coordinate, generates the testing result matrix that comprises the testing result that described repeated detection obtains.
Preferably, in the above-mentioned data transmission method, described delay transport module selects the optimal detection result to be specially in testing result corresponding to described each propagation delay time:
In described testing result matrix, described delay transport module is selected the maximum matrix of testing result number of sign transmission success;
Selection is positioned at the testing result of described matrix core, as described optimal detection result.
Preferably, in the above-mentioned data transmission method, further comprise: when reaching optimized transmission time delay pre-conditioned, begin the described step that delay transport module between the first data terminal and the second data terminal is arranged the initial value in propagation delay time.
Preferably, in the above-mentioned data transmission method, described delay transport module makes the data strobe signal of data sending terminal through after the propagation delay time, as the clock signal of trigger, control the conducting of described flip-flop data end, thereby control the propagation delay time of described the transmission of data.
The present invention also provides a kind of time delay module, and between the first data terminal and the second data terminal, described time delay module comprises:
The propagation delay time adjusting module, the propagation delay time initial value of be used for to receive setting, and the described propagation delay time repeatedly adjusted on described propagation delay time initial value basis;
The transmission of data detection module is used under the propagation delay time that described propagation delay time adjusting module sends the transmission of data being detected, and obtains corresponding testing result;
Optimal detection is acquisition module as a result, is used for obtaining the optimal detection result from described a plurality of testing results; And optimal transmission configuration module time delay, being used for the propagation delay time that the optimal detection result is corresponding is configured to optimal transmission time delay, makes data transmission between described the first data terminal and the second data terminal through the delay of time delay of described optimal transmission.
Preferably, further comprise in the above-mentioned time delay module:
Frequency detection module is for detection of the frequency of the data strobe signal of described the transmission of data; And
Frequency division module is used for described frequency is carried out frequency division, determines the step units time;
The described propagation delay time is the product of described step units time and step value; Described step value is the natural number more than or equal to 1;
Described propagation delay time adjusting module specifically is used for, and receives the propagation delay time initial value of setting, and on described propagation delay time initial value basis, described step value is repeatedly adjusted, and will notify described the transmission of data detection module the propagation delay time.
Preferably, in the above-mentioned time delay module, described frequency division module specifically is used for, and described frequency is carried out frequency division by divide ratio N, determines the step units time, and N is the natural number greater than 1;
Described propagation delay time adjusting module is further used for, and whether judges described step value less than N, if described step value less than N, progressively increases described step value, and will notify described the transmission of data detection module the propagation delay time; If described step value equals N, then notify as a result acquisition module of described optimal detection.
Preferably, in the above-mentioned time delay module, the described propagation delay time comprises: described the first data terminal receives the receive delay time of described the second data that data terminal sends and the transmission lag time that described the first data terminal is sent to described the second data terminal data;
Described propagation delay time adjusting module specifically is used for, receive receive delay time initial value and the transmission lag time initial value set, and the described receive delay time repeatedly adjusted on described receive delay time initial value basis, and the described transmission lag time is repeatedly being adjusted on described transmission lag time initial value basis;
Described the transmission of data detection module specifically is used for, under time the transmission of data is carried out repeated detection at receive delay time and transmission lag that described propagation delay time adjusting module repeatedly sends, obtain each testing result that detects, take the described receive delay time as row-coordinate, the described transmission lag time is the row coordinate, generates the testing result matrix that comprises the testing result that described repeated detection obtains; Wherein, when data transmission fails occurs in the either direction of the first data terminal to the second data terminal or the second data terminal to the first data terminal, described testing result is bust this, when the data transmission success all occured on the both direction of the first data terminal to the second data terminal and the second data terminal to the first data terminal, described testing result was transmission success.
Preferably, in the above-mentioned time delay module, described optimal detection as a result acquisition module specifically is used for, in described testing result matrix, select the maximum matrix of testing result number of transmission success, and select to be positioned at the testing result of described matrix core, as described optimal detection result.
Preferably, in the above-mentioned time delay module, also comprise: the optimized transmission time starts module, when being used for reaching optimized transmission time delay pre-conditioned, the propagation delay time initial value is sent to described propagation delay time adjusting module, start the adjustment in propagation delay time.
The data transmission method that the embodiment of the invention provides and time delay module, so that the data transfer delay time can automatically be regulated and optimize and need not to be welded to memory chip on the veneer and carry out manual detection by oscillograph, and can guarantee integrality and the accuracy of data transmission.
Description of drawings
Fig. 1 is desirable receiving end DQ signal and DQS signal timing diagram;
Fig. 2 is receiving end DQ signal and DQS signal timing diagram under the real use state;
Fig. 3 is the method flow diagram of one embodiment of the invention;
Fig. 4 is one embodiment of the invention circuit connection structure isoboles;
Fig. 5 is the method flow diagram of one embodiment of the invention;
Fig. 6 is one embodiment of the invention testing result matrix synoptic diagram;
Fig. 7 is one embodiment of the invention testing result matrix synoptic diagram;
Fig. 8 is one embodiment of the invention time delay modular structure block diagram.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention is clearer, below in conjunction with embodiment and accompanying drawing, the embodiment of the invention is done in further detail explanation.At this, illustrative examples of the present invention and explanation are used for explanation the present invention, but not as a limitation of the invention.
The invention provides a kind of embodiment of data transmission method, carry out the detection of the transmission of data by regulating the propagation delay time, and then obtain optimal transmission time delay, and with carrying out data transfer this time delay.Referring to Fig. 3, an embodiment of the method comprises:
Delay transport module between the first data terminal and the second data terminal is arranged the initial value in propagation delay time;
By the repeatedly adjustment in described propagation delay time being carried out the repeated detection of the transmission of data, obtain testing result corresponding to each propagation delay time;
In testing result corresponding to described each propagation delay time, select the optimal detection result;
The propagation delay time that described optimal detection result is corresponding is set to optimal transmission time delay of described delay transport module, makes data transmission between described the first data terminal and the second data terminal through the delay of time delay of described optimal transmission.
If the first data terminal in above-described embodiment and the second data terminal be respectively Memory Controller Hub with and plug-in memory chip, the difference of the instruction of sending according to Memory Controller Hub, Memory Controller Hub sends data or receives data from memory chip to memory chip.Between Memory Controller Hub and memory chip, the delay transport module is arranged, postpone transport module so that the DQS signal produces the delay (this delay can be in advance or step back, unitedly call delay) of certain hour section, thereby make the DOS signal be positioned at the center of DQ signal as far as possible.
Figure 4 shows that the process that data are read to Memory Controller Hub by memory chip, postponing transport module can be realized by delay phase-locked loop (Delay Lock Loop, DLL) and d type flip flop, and DLL is used for the certain retardation of enable clock signal generation.The clock end (CLK end) of the data strobe signal DQS of memory chip input d type flip flop after DLL postpones, the DQ signal of memory chip connects the data terminal (D end) of d type flip flop.Like this, the DQS signal through after the delay such as T ' shown in Figure 2, triggers the d type flip flop conducting in DLL, make the central authorities of just in time aiming at the DQ signal through the DQS signal after " skew ".Like this, postpone transport module and obtain repeatedly test result corresponding to each propagation delay time by the automatic adjustment propagation delay time, from test result, select optimal value, make and postpone transport module and obtain optimal transmission time delay, automatically realize the optimization in propagation delay time, avoided using artificial test mode to adjust the loaded down with trivial details of propagation delay time, and in the use procedure because the change of the factors such as environment temperature, chip power supply voltage, the inconvenience that brings to the manual testing when causing the propagation delay time to adjust.
In the specific embodiment, behind the Board Power up, the initial value in propagation delay time is set at first, generally can selects zero, then on the basis of initial value, progressively increase or the minimizing propagation delay time at every turn.Can certainly be set to the numerical value outside zero, the scope of initial value is relevant with the DQS signal frequency, if the DDR chip, the scope of initial value is the duration between adjacent two rising edge of a pulses of DQS and the negative edge, followingly is described as an example of the DDR chip example.
After the initial value setting in propagation delay time, begin the transmission of data is tested.Carry out the read test of DDR chip in this example, so for Memory Controller Hub, be the time of reception that postpones the DQ signal, namely the propagation delay time is the receive delay time.Memory Controller Hub will compare with the DQ signal that receives at Memory Controller Hub at the DQ signal of DDR chip side output, obtains test result one time.If identical with the value of the DQ signal of receiving in the Memory Controller Hub termination from the DQ signal of DDR chip side output, then representative is read successfully, otherwise reads failure.The receive delay time is constantly adjusted within limits, obtained repeatedly test result.The scope of adjusting is identical with the scope of setting initial value.
Then, from test result repeatedly, select optimal result, and find receive delay time corresponding to optimal result.Repeatedly can comprise the record that reads successfully repeatedly in the test result, if such as first rising edge of a pulse among Fig. 2 very near the mid point of D0, mean receive delay so that the reception of data is comparatively stable (if as shown in Figure 2, though first rising edge of a pulse within the D0 scope, does not represent and reads successfully).In repeatedly reading successful test record, only once so that the rising edge of pulse (or negative edge) close to the centre of D0, the receive delay time of this time correspondence, is the optimum receive delay time.This optimum receive delay time assignment to DLL, so that reading, the data of DDR chip is in maximum sequential allowance.
Same, above-mentioned read test also can be for by the write test of Memory Controller Hub to the DDR chip, and step is similar.Certainly, because the data transmission between Memory Controller Hub and the memory chip is two-way, be reading and write and all needing adjust to postpone the transmission time of memory chip data, more excellent testing scheme should be to test reading and writing all, and to receive time delay and transmission lag time comprehensively get excellent, thereby obtain the optimum propagation delay time of read-write.
The below provides a kind of more excellent testing scheme.The test process of finishing output and write between Memory Controller Hub and DDR chip namely writes the DQ signal at content controller side direction DDR chip, receives the DQ signal from the DDR chip side again, and these two signals are compared.At first, the DQ signal that Memory Controller Hub writes respectively to the DDR chip is 55AA55AA, AA55AA55,0, FFFFFFFF (order does not limit), respectively take above-mentioned value continuous coverage four times (such as the first time DQ signal as 55AA55AA, the DQ signal is AA55AA55 for the second time), if each byte that the Memory Controller Hub termination is received is all identical with above-mentioned data, then this readwrite tests success.The consideration point of choosing above-mentioned value is that 5 is that 0101, A is 1010 in the scale-of-two, F is 1111, through four tests, (test namely occur one time 1 and one time 0 for twice also be feasible) all appears 0,1,0,1 in each bit, can judge accurately more whether 0 and 1 occasion all receives normally.Find out that thus above-mentioned measuring-signal is that A5A5A5A5,5A5A5A5A, FFFFFFFF, the Similar Composite Systems such as 0 also can reach same effect.
Realize repeated detection with the stepping detection method in the preferred embodiment.Before the propagation delay time is repeatedly adjusted, first the frequency of DQS signal detected, again this frequency is carried out frequency division and obtain the step units time.Suppose to use the inner phase-locked loop pll frequency-dividing clock of processor, the frequency that detects DDR end DQS signal is 500M Hz, and divide ratio is 10 o'clock, and the frequency of process frequency division is 5000M Hz, and namely the step units time is 2*10
-10S.To the adjustment in propagation delay time, with 2*10
-10For unit finely tunes.Step value is 1 o'clock, and the propagation delay time is to increase or reduce 2*10 on the initial value basis
-10S; Step value is 2 o'clock, and the propagation delay time is to increase or reduce 4*10 on the initial value basis
-10S, by that analogy.
Divide ratio in theory can be infinitely great, and namely the step units time can be infinitely short.Divide ratio numerically is identical with the stepping sum, namely is divided into what step units times, and the stepping sum namely can have how many times.Certainly, step value also not necessarily will increase one by one, and when divide ratio was enough large, step value can increase by 2,3 or larger value at every turn, but when above-mentioned step value is incremented to the stepping sum, a test period end.Still to read the DDR chip as example, the test result of selective reception success at first the test result that obtains from this cycle, therefrom find again one or two (be even number when inferior when receiving successfully, optimal value is two) in the middle of being positioned at namely to obtain its corresponding optimal delay time of reception.When optimal value is two, select at random one of them to get final product.
The method of above-mentioned all embodiment, can be applicable to memory chip write and Memory Controller Hub from the reading of memory chip, namely postpone the adjustment of time of reception and delayed delivery time.Such as, memory chip is write fashionable, postponing the transmission time is the delayed delivery time, the DQS signal that Memory Controller Hub sends triggered d type flip flop again and comes conducting DQ signal to the transmission of memory chip through the delayed delivery time.
In the following embodiments, the invention provides a kind of method of data transmission, in the data transmission procedure between Memory Controller Hub and memory chip (take the DDR chip as example), use the delayed delivery time and postpone time of reception (as using the DLL function) and adjust the sequential relationship between receiving end DQ signal and the DQS signal.As shown in Figure 5, with Board Power up, processor is finished Memory Controller Hub and the operation of DDR chip initiation, and obtains step units after the time according to the method for above-described embodiment, and the optimization method in propagation delay time may further comprise the steps:
The initial value of step 1. reconfiguration latency time of reception (initially receiving the DLL Configuration Values);
The initial value of step 2. reconfiguration latency transmitting time (initialization DLL Configuration Values), step 2 is not done restriction with the time sequencing of step 1;
Step 3. is come the reconfiguration latency transmitting time with the mode of stepping, namely adjusts the delayed delivery time by the mode of adjusting step value, delayed delivery time=transmission step value * step units time;
Step 4. pair DDR chip writes test and logging test results;
Step 5. judges whether reach stepping sum N, namely whether cumulative transmission DLL stepping number of times has reached and can supply the sum of stepping if sending step value; If do not reach, then come back to step 3 and carry out, if reach, then execution in step 6;
Step 6. is come the reconfiguration latency time of reception with the mode of stepping, namely adjusts by the mode of adjusting step value to postpone time of reception (receiving step value * step units time);
Step 7. pair DDR chip carries out read test and logging test results;
Step 8. judges whether reach stepping sum N, namely whether cumulative reception DLL stepping number of times has reached and can supply the sum of stepping if receiving step value; If do not reach, then come back to step 3 and carry out, if reach, then execution in step 9;
Step 9. obtains the test result matrix, calculates optimum test result from the test result matrix, obtains corresponding optimal transmission time delay.
At last, dispose the DLL functional module time delay with optimal transmission, data transmission realizes postponing with the DLL functional module.
In the mode of above-mentioned loop nesting, namely come reconfiguration latency transmitting time and step 6 to come the sequencing of reconfiguration latency time of reception to exchange with the mode of stepping by the mode of above-mentioned steps 3 usefulness steppings, same can realize with the delayed delivery time and postpone the time of reception two dimension being worth the detection of the data transmission of correspondence, and in step 9, obtain the test result of arranging in the mode of matrix.
In the above-mentioned steps 9, test result is arranged in the mode of matrix, from matrix table, find out the maximum matrix of readwrite tests success number, find in total matrix table, all readwrite tests results are successful matrix, in these matrixes, select the test result number maximum, be reflected in the test result matrix table (part) of Fig. 6 and be the rectangle of " √ " area maximum, and draw in this rectangle two dimension value near intermediate value.Take test result matrix shown in Figure 6 as example, the horizontal ordinate of matrix represents to send DLL Configuration Values (delayed delivery time), and the ordinate of matrix represents to receive DLL Configuration Values (delay time of reception).The gap size of adjacent step value is identical.After sign " * " expression in the matrix uses corresponding (abscissa value, ordinate value) two-dimentional DLL Configuration Values to carry out transmission delay, the DDR chip is carried out readwrite tests failure (read failure or write failure or all read and write failures); After sign in the matrix " √ " expression uses corresponding (abscissa value, ordinate value) two-dimentional DLL Configuration Values to carry out transmission delay, DDR is carried out readwrite tests success (reading and write successes).How in the test result of these readwrite tests successes in the corresponding propagation delay time, find the only propagation delay time (being that data delay transmitting time and time delay time of reception are comprehensively optimum), namely, make the Memory Controller Hub termination receive DQS signal rising edge and negative edge and level off to as far as possible the centre of the DQ signal that receives, and the DDR die terminals receives DQS signal rising edge and negative edge levels off to as far as possible in the centre of the DQ signal that receives, be by selecting in the maximum area matrix.
Among Fig. 6, the rectangle of area maximum of sign " √ " is 3 * 3 square, and ordinate and the horizontal ordinate of " √ " of its middle (" √ " that lived by the circle circle) are optimal transmission time delay.And among Fig. 7, the rectangle of area maximum of sign " √ " is 2 * 4 rectangle, and its optimal transmission has four kinds of (" √ " that lived by four circle circles respectively) array modes time delay.After obtaining these four groups of delayed delivery times and postponing the optimum combination of time of reception, can select at random wherein one group to be arranged in the DLL module.
In above-mentioned detection, the choosing of DQ signal to transmission, can use aforementioned recommendation, such as 55AA55AA, AA55AA55,0, FFFFFFFF (order does not limit) continuous coverage four times, if the value of these DQ signals that the Memory Controller Hub side joint is received all value with its DQ signal that writes to the DDR chip is identical, then this readwrite tests success, reason repeats no more.
Among the more excellent embodiment, set again the trigger condition of Optimal Parameters, such as variations such as environment temperature, chip power supply voltages, so that the propagation delay time need to be optimized adjustment again, so initial value of reconfiguration latency transmitting time and delay time of reception within postponing transport module, the delay transport module that obtains initial value namely begins to carry out above-mentioned test, by repeatedly testing and in test result, find delayed delivery time corresponding to optimum test result and postponing time of reception, for the data transmission between Memory Controller Hub and the memory chip.Can avoid so in use because the impact of various factors the inconvenience that brings to the manual testing when causing the propagation delay time to adjust.
The present invention also provides the embodiment of a time Postponement module, such as the function that realizes the time delay module by the delay phase-locked loop among Fig. 4 (DLL) and d type flip flop.Fig. 8 has showed the inner structure block diagram of the DLL between the first data terminal and the second data terminal, comprises:
The propagation delay time adjusting module, the propagation delay time initial value of be used for to receive setting, and the propagation delay time repeatedly adjusted on propagation delay time initial value basis;
The transmission of data detection module is used under the propagation delay time that the propagation delay time adjusting module sends the transmission of data being detected, and obtains corresponding testing result;
Optimal detection is acquisition module as a result, is used for obtaining the optimal detection result from a plurality of testing results; With
Optimal transmission configuration module time delay is used for the propagation delay time that the optimal detection result is corresponding to be configured to optimal transmission time delay, makes data transmission between the first data terminal and the second data terminal through the optimal transmission delay of time delay.
More excellent, this time delay module further comprises:
Frequency detection module is for detection of the frequency of the data strobe signal of the transmission of data;
Frequency division module is used for the above-mentioned frequency that detects is carried out frequency division, determines the step units time.
The above-mentioned propagation delay time is the product of step units time and step value; Step value is the natural number more than or equal to 1;
The propagation delay time adjusting module then specifically is used for, and receives the propagation delay time initial value of setting, and on propagation delay time initial value basis, step value is repeatedly adjusted, with propagation delay time notification transmission data detection module.
Among the more excellent embodiment, above-mentioned frequency division module specifically is used for, and the frequency that detects is carried out frequency division by divide ratio N determine that step units time, N are the natural number greater than 1;
Above-mentioned propagation delay time adjusting module is further used for, and whether judges step value less than N, if step value less than N, progressively increases step value, so that the propagation delay time is adjusted, and the propagation delay time after will adjusting is notified described the transmission of data detection module; If step value equals N, show that step value has arrived for the sum of stepping, then to notify as a result acquisition module of optimal detection.
Can carry out between the first data terminal and the second data terminal in the scene of bidirectional data transfers, arbitrary end wherein can be data sending terminal or data receiver, and the propagation delay time comprises: receive delay time and transmission lag time.
The propagation delay time adjusting module specifically is used for receiving receive delay time initial value and the transmission lag time initial value of setting, and the described receive delay time repeatedly adjusted on described receive delay time initial value basis, the described transmission lag time is repeatedly being adjusted on described transmission lag time initial value basis;
The transmission of data detection module specifically is used for, and the receive delay time and the transmission lag that send at the propagation delay time adjusting module detected the transmission of data under the time, obtained corresponding testing result, forms the testing result matrix.
Further, optimal detection as a result acquisition module specifically is used for, and in the testing result matrix, comprises the maximum matrix of test result (rectangle of area maximum) in the testing result of selection transmission success, and select to be positioned at described rectangular centre testing result partly, as the optimal detection result.
Further, the time delay module further comprises: the optimized transmission time starts module, when being used for reaching optimized transmission time delay pre-conditioned, the propagation delay time initial value is sent to the propagation delay time adjusting module, start the adjustment in propagation delay time.
The above only is preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (13)
1. a data transmission method is characterized in that, comprises:
Delay transport module between the first data terminal and the second data terminal obtains the initial value in propagation delay time, and the described propagation delay time is the time-delay that described delay transport module is applied to the transmission of data between described the first data terminal and the second data terminal;
Described delay transport module obtains testing result corresponding to each propagation delay time by the repeatedly adjustment in described propagation delay time being carried out the repeated detection of the transmission of data;
Described delay transport module is selected the optimal detection result in testing result corresponding to described each propagation delay time;
The propagation delay time that described delay transport module is corresponding with described optimal detection result, be set to the optimal transmission time delay of described delay transport module, make data transmission between described the first data terminal and the second data terminal through the delay of time delay of described optimal transmission.
2. data transmission method according to claim 1 is characterized in that,
Before repeatedly adjusting of described propagation delay time carried out the repeated detection of the transmission of data, described method further comprised:
Described delay transport module detects the frequency of the data strobe signal of described the transmission of data;
Described delay transport module carries out frequency division to described frequency, determines the step units time;
The repeatedly adjustment in described propagation delay time comprises:
Described step value is repeatedly adjusted;
On the basis of described initial value, increase or reduce the product of described step units time and step value, the propagation delay time after being adjusted.
3. data transmission method according to claim 2 is characterized in that, the divide ratio that described frequency is carried out frequency division is N, and N is the natural number greater than 1;
Described delay transport module specifically comprises by the repeated detection of carrying out the transmission of data of repeatedly adjusting to the described propagation delay time:
Whether the every acquisition one-time detection of described delay transport module result judges described step value less than N, if described step value less than N, progressively increases described step value, and continues the data that receive are detected; If described step value equals N, then continue in testing result corresponding to described each propagation delay time, to select optimal detection result's step.
4. each described data transmission method is characterized in that according to claim 1～3, and the described propagation delay time comprises:
Described the first data terminal receives the receive delay time of described the second data that data terminal sends and the transmission lag time that described the first data terminal is sent to described the second data terminal data;
Described delay transport module obtains testing result corresponding to each propagation delay time and specifically comprises by the repeatedly adjustment in described propagation delay time being carried out the repeated detection of the transmission of data:
Adjust described receive delay time and transmission lag time and carry out the repeated detection of the transmission of data, obtain each testing result that detects, wherein, when data transmission fails occurs in the either direction of the first data terminal to the second data terminal or the second data terminal to the first data terminal, described testing result is bust this, when the data transmission success all occured on the both direction of the first data terminal to the second data terminal and the second data terminal to the first data terminal, described testing result was transmission success;
Take the receive delay time as row-coordinate, the transmission lag time is the row coordinate, generates the testing result matrix that comprises the testing result that described repeated detection obtains.
5. data transmission method according to claim 4 is characterized in that,
Described delay transport module selects the optimal detection result to be specially in testing result corresponding to described each propagation delay time:
In described testing result matrix, described delay transport module is selected the maximum matrix of testing result number of sign transmission success;
Selection is positioned at the testing result of described matrix core, as described optimal detection result.
6. data transmission method according to claim 1, it is characterized in that, described method further comprises: when reaching optimized transmission time delay pre-conditioned, begin the described step that delay transport module between the first data terminal and the second data terminal is arranged the initial value in propagation delay time.
7. data transmission method according to claim 1, it is characterized in that, described delay transport module makes the data strobe signal of data sending terminal through after the propagation delay time, clock signal as trigger, control the conducting of described flip-flop data end, thereby control the propagation delay time of described the transmission of data.
8. a time delay module between the first data terminal and the second data terminal, is characterized in that, described time delay module comprises:
The propagation delay time adjusting module, the propagation delay time initial value of be used for to receive setting, and the described propagation delay time repeatedly adjusted on described propagation delay time initial value basis;
The transmission of data detection module is used under the propagation delay time that described propagation delay time adjusting module sends the transmission of data being detected, and obtains corresponding testing result;
Optimal detection is acquisition module as a result, is used for obtaining the optimal detection result from described a plurality of testing results; And optimal transmission configuration module time delay, being used for the propagation delay time that the optimal detection result is corresponding is configured to optimal transmission time delay, makes data transmission between described the first data terminal and the second data terminal through the delay of time delay of described optimal transmission.
9. time delay module according to claim 8 is characterized in that, also comprises:
Frequency detection module is for detection of the frequency of the data strobe signal of described the transmission of data; And
Frequency division module is used for described frequency is carried out frequency division, determines the step units time;
The described propagation delay time is the product of described step units time and step value; Described step value is the natural number more than or equal to 1;
Described propagation delay time adjusting module specifically is used for, and receives the propagation delay time initial value of setting, and on described propagation delay time initial value basis, described step value is repeatedly adjusted, and will notify described the transmission of data detection module the propagation delay time.
10. time delay module according to claim 9 is characterized in that, described frequency division module specifically is used for, and described frequency is carried out frequency division by divide ratio N, determines the step units time, and N is the natural number greater than 1;
Described propagation delay time adjusting module is further used for, and whether judges described step value less than N, if described step value less than N, progressively increases described step value, and will notify described the transmission of data detection module the propagation delay time; If described step value equals N, then notify as a result acquisition module of described optimal detection.
11. each described time delay module according to claim 8～10, it is characterized in that the described propagation delay time comprises: described the first data terminal receives the receive delay time of described the second data that data terminal sends and the transmission lag time that described the first data terminal is sent to described the second data terminal data;
Described propagation delay time adjusting module specifically is used for, receive receive delay time initial value and the transmission lag time initial value set, and the described receive delay time repeatedly adjusted on described receive delay time initial value basis, and the described transmission lag time is repeatedly being adjusted on described transmission lag time initial value basis;
Described the transmission of data detection module specifically is used for, under time the transmission of data is carried out repeated detection at receive delay time and transmission lag that described propagation delay time adjusting module repeatedly sends, obtain each testing result that detects, take the described receive delay time as row-coordinate, the described transmission lag time is the row coordinate, generates the testing result matrix that comprises the testing result that described repeated detection obtains; Wherein, when data transmission fails occurs in the either direction of the first data terminal to the second data terminal or the second data terminal to the first data terminal, described testing result is bust this, when the data transmission success all occured on the both direction of the first data terminal to the second data terminal and the second data terminal to the first data terminal, described testing result was transmission success.
12. time delay module according to claim 11, it is characterized in that, described optimal detection as a result acquisition module specifically is used for, in described testing result matrix, select the maximum matrix of testing result number of transmission success, and select to be positioned at the testing result of described matrix core, as described optimal detection result.
13. time delay module according to claim 8 is characterized in that, also comprises:
The optimized transmission time starts module, when being used for reaching optimized transmission time delay pre-conditioned, the propagation delay time initial value is sent to described propagation delay time adjusting module, starts the adjustment in propagation delay time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110205549.0A CN102890663B (en) | 2011-07-21 | 2011-07-21 | A kind of data transmission method and time delay module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110205549.0A CN102890663B (en) | 2011-07-21 | 2011-07-21 | A kind of data transmission method and time delay module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102890663A true CN102890663A (en) | 2013-01-23 |
| CN102890663B CN102890663B (en) | 2016-08-10 |
Family
ID=47534170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110205549.0A Expired - Fee Related CN102890663B (en) | 2011-07-21 | 2011-07-21 | A kind of data transmission method and time delay module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102890663B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103677081A (en) * | 2013-12-30 | 2014-03-26 | 龙芯中科技术有限公司 | Processing method and processing device for data signals |
| CN106527977A (en) * | 2016-10-17 | 2017-03-22 | 锐捷网络股份有限公司 | A parameter configuring method and a storage apparatus |
| CN110428856A (en) * | 2019-07-29 | 2019-11-08 | 珠海市一微半导体有限公司 | It is a kind of for reading and writing the delay parameter optimization method and system of DDR memory |
| CN111092789A (en) * | 2019-12-18 | 2020-05-01 | 歌尔微电子有限公司 | Data transmission method, device, equipment and computer readable storage medium |
| CN113630296A (en) * | 2021-08-31 | 2021-11-09 | 中国电子科技集团公司第三十八研究所 | Automatic LVDS transmission delay window testing method and system |
| CN114817110A (en) * | 2022-04-26 | 2022-07-29 | 地平线(上海)人工智能技术有限公司 | Data transmission method and device |
| CN116913368A (en) * | 2023-09-08 | 2023-10-20 | 合肥康芯威存储技术有限公司 | Test system and test method for memory chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1212399A (en) * | 1997-08-04 | 1999-03-31 | 松下电器产业株式会社 | Delay time adjuster and adjusting method between multiple transmission lines |
| US20080159022A1 (en) * | 2006-12-29 | 2008-07-03 | Suryaprasad Kareenahalli | Dynamic adaptive read return of DRAM data |
-
2011
- 2011-07-21 CN CN201110205549.0A patent/CN102890663B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1212399A (en) * | 1997-08-04 | 1999-03-31 | 松下电器产业株式会社 | Delay time adjuster and adjusting method between multiple transmission lines |
| US20080159022A1 (en) * | 2006-12-29 | 2008-07-03 | Suryaprasad Kareenahalli | Dynamic adaptive read return of DRAM data |
Non-Patent Citations (2)
| Title |
|---|
| MAO ZE-HUI JIANG BIN: "Fault estimation and accommodation for networked control systems with transfer delay", 《ACTA AUTOMATICA SINICA》 * |
| 屈八一 周渭 苗苗 靳东: "基于传输延迟的时间量化技术研究", 《宇航计测技术》 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103677081A (en) * | 2013-12-30 | 2014-03-26 | 龙芯中科技术有限公司 | Processing method and processing device for data signals |
| CN103677081B (en) * | 2013-12-30 | 2017-03-15 | 龙芯中科技术有限公司 | The processing method and processing meanss of data signal |
| CN106527977A (en) * | 2016-10-17 | 2017-03-22 | 锐捷网络股份有限公司 | A parameter configuring method and a storage apparatus |
| CN110428856A (en) * | 2019-07-29 | 2019-11-08 | 珠海市一微半导体有限公司 | It is a kind of for reading and writing the delay parameter optimization method and system of DDR memory |
| CN110428856B (en) * | 2019-07-29 | 2021-06-08 | 珠海市一微半导体有限公司 | Delay parameter optimization method and system for reading and writing DDR memory |
| CN111092789A (en) * | 2019-12-18 | 2020-05-01 | 歌尔微电子有限公司 | Data transmission method, device, equipment and computer readable storage medium |
| CN113630296A (en) * | 2021-08-31 | 2021-11-09 | 中国电子科技集团公司第三十八研究所 | Automatic LVDS transmission delay window testing method and system |
| CN114817110A (en) * | 2022-04-26 | 2022-07-29 | 地平线(上海)人工智能技术有限公司 | Data transmission method and device |
| CN114817110B (en) * | 2022-04-26 | 2023-04-25 | 地平线(上海)人工智能技术有限公司 | Data transmission method and device |
| CN116913368A (en) * | 2023-09-08 | 2023-10-20 | 合肥康芯威存储技术有限公司 | Test system and test method for memory chip |
| CN116913368B (en) * | 2023-09-08 | 2023-12-12 | 合肥康芯威存储技术有限公司 | Test system and test method for memory chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102890663B (en) | 2016-08-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102890663A (en) | Data transmitting method and time delay module | |
| US10580465B2 (en) | System and method for providing a configurable timing control for a memory system | |
| US11990912B2 (en) | Data transmission using delayed timing signals | |
| KR101855512B1 (en) | Read training a memory controller | |
| US7752364B2 (en) | Apparatus and method for communicating with semiconductor devices of a serial interconnection | |
| KR101733483B1 (en) | Method to calibrate start values for write leveling in a memory system | |
| US8458507B2 (en) | Bus frequency adjustment circuitry for use in a dynamic random access memory device | |
| KR20110130887A (en) | Semiconductor memory device and operating method thereof | |
| US10482946B2 (en) | Management of strobe/clock phase tolerances during extended write preambles | |
| US11217298B2 (en) | Delay-locked loop clock sharing | |
| US10510398B2 (en) | Systems and methods for improving write preambles in DDR memory devices | |
| US11748035B2 (en) | Command address input buffer bias current reduction | |
| US9330034B2 (en) | Levelization of memory interface for communicating with multiple memory devices | |
| CN1992087B (en) | Parts testing device and method and interface apparatus thereof | |
| US7606110B2 (en) | Memory module, memory unit, and hub with non-periodic clock and methods of using the same | |
| CN102930901B (en) | Controller used for memory and method for using controller | |
| CN100412749C (en) | Memory signal timing regulation method and related device | |
| US10192599B2 (en) | Semiconductor device | |
| CN106847319A (en) | A kind of FPGA circuitry and window signal method of adjustment | |
| JP2023543479A (en) | Memory training methods, memory controllers, processors and electronic devices | |
| US12019512B2 (en) | System and method to control memory error detection with automatic disabling | |
| US20230236996A1 (en) | Single ended pattern dependent and power supply based reference voltage adaptation to improve data eye margin | |
| US20240290365A1 (en) | Circuit for aligning command input data and semiconducter device including the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| CB03 | Change of inventor or designer information |
Inventor after: Wang Yanmei Inventor after: Yan Xiao Inventor after: Liu Qian Inventor after: Wang Lili Inventor after: Qian Cong Inventor after: Xue Yongqin Inventor after: Sun Jianing Inventor after: Wu Qiang Inventor after: Yu Honghong Inventor after: Feng Zhe Inventor after: Gu Yanchun Inventor after: Wang Ziwei Inventor after: Wu Bin Inventor after: Guo Luyang Inventor after: Chu Kainan Inventor after: Chen Xinling Inventor after: Ge Jie Inventor after: Tang Liang Inventor after: Wang Lei Inventor after: Li Wenqiang Inventor before: Chen Zeqiang Inventor before: Zhao Yan |
|
| COR | Change of bibliographic data | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20160707 Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Applicant after: State Grid Corporation of China Applicant after: State Grid Shandong Electric Power Company, Jining City Rencheng District Power Supply Company Address before: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice Applicant before: ZTE Corporation |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160810 Termination date: 20170721 |