CN102930901B - Controller used for memory and method for using controller - Google Patents

Controller used for memory and method for using controller Download PDF

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Publication number
CN102930901B
CN102930901B CN201110226216.6A CN201110226216A CN102930901B CN 102930901 B CN102930901 B CN 102930901B CN 201110226216 A CN201110226216 A CN 201110226216A CN 102930901 B CN102930901 B CN 102930901B
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controller
storer
automatic detection
register
described controller
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CN102930901A (en
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操冬华
葛保建
谢树
胡胜发
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Guangzhou Ankai Microelectronics Co.,Ltd.
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Anyka Guangzhou Microelectronics Technology Co Ltd
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Abstract

The invention discloses a controller used for memories and a method for using the controller; with the invention, a logical function register is adjusted according to a received first signal so as to bind with a logical function corresponding to the memory type; a level mode of an input-output port of the controller and a drive load capacity are adjusted according to a received second signal; therefore, control of various types of memories can be supported by a same controller. In addition, through automatic detection of the operation sequence of the controller, the processing efficiency and the flexibility are improved.

Description

A kind of controller for storer and apply the method for this controller
Technical field
The present invention relates to storage control technology field, particularly a kind of controller for storer and apply the method for this controller.
Background technology
Along with embedded product is at consumer electronics product, industry, the field application such as security protection are more and more extensive, and people need a large amount of dynamic RAMs (DRAM), for storing data dynamically, operational system and the relevant code of application and data.
Such as, the dynamic storage DDR2SDRAM used on the market at present.Due to the memory device that ddr2 storer is a kind of high speed, therefore its controller needs the problem considering signal, and general controller majority adopts in the sequential of hardware to do, that is, the deviser of controller can according to electronic engineering design development joint conference (JEDEC in the protocol circuit of sdram, Joint Electron DeviceEngineering Council) standard, provide a kind of time sequential routine of the support to standard, also the Controller gain variations person had, adopt the mode of semi-software half hardware, to the time sequence parameter of some operation, adopt the mode that software is adjustable, by in the clock counter of parameter read-in controller.But once after operation failure, hardware circuit or printed circuit board (PCB) (PCB, Printed Circuit Board) plate just must be readjusted, until meet the timing requirements of this controller, just can normal running.
Visible, the controller due to storer is in the market substantially all based on hardware mode design, or based on the patten's design of half hardware.Therefore, the dirigibility of existing controller is poor, can not be compatible be applied to polytype storer, and treatment effeciency is low.
Summary of the invention
The embodiment of the present invention provides a kind of controller for storing and applies the method for this controller, same controller can be made to support multiple memorizers, and improve treatment effeciency and dirigibility.
The embodiment of the invention discloses a kind of controller for storer, comprising:
Type selection unit, for the type according to the first signal behavior of receiving storer to be controlled, adjustment logic function register, to bind the logic function corresponding with this type of memory;
Input and output control unit, for according to the secondary signal received, adjusts the input/output port level mode of described controller and drives the ability of load;
Dll control module, after the register parameters configuration in described controller, enable reset dll, after waiting for dll stable output, notice initialization unit;
Initialization unit, for after described initialize memory end of operation to be controlled, notifies compatible probe unit;
Compatible probe unit, for carrying out automatic detection to the time sequential routine of storer, after automatic detection correctly completes, arranges the control word of all signals, to carry out subsequent operation to storer to be controlled.
Wherein, described controller also comprises:
Error-detecting adjustment unit, for after automatic detection failure, check the state of each register in described controller, obtain reason and the position of operation failure, according to the reason of described operation failure and the corresponding with it register value of position adjustment, notify compatible probe unit afterwards;
Described compatible probe unit, also for according to the notice from error-detecting adjustment unit, starts automatic detection again.
Wherein, described controller also comprises:
Whether status toggle unit, being in idle condition for judging that described controller is current, if so, then described controller being switched to terminating resistor power down mode, otherwise, described controller is switched to duty.
Wherein, described compatible probe unit comprises:
Read-write subelement, for reading and writing continuously a certain piece of region of storer to be detected;
Relatively subelement, for gathering described read-write result as sampled data, carrying out analysis to described sampled data and obtaining analysis result;
Adjustment arranges subelement, for automatically completing the synchronous adjustment of clock according to analysis result, after automatic detection correctly completes, arranges the control word of all signals, with the object that the clock edge reaching automatic calibration data sampling is synchronous.
Wherein, the described logic function corresponding with this type of memory at least comprises: the control model of storer, the drive level pattern of controller pin interface and driving force, amount of bandwidth, the stand-by period of memory span, read-write operation.
The embodiment of the invention also discloses a kind of method of application controller, comprising:
According to the type of the first signal behavior received storer to be controlled, adjustment logic function register, to bind the logic function corresponding with this type of memory; Wherein, described first signal is that logic function selects signal;
According to the signal received, adjust the input/output port level mode of described controller and drive the ability of load; Wherein, described secondary signal is the signal of input/output port level mode for adjusting controller and the ability driving load;
After register parameters configuration in described controller, enable reset dll, waits for dll stable output; Afterwards,
Initialization operation is carried out to described storer to be controlled;
Automatic detection is carried out to the time sequential routine of storer, after automatic detection correctly completes, the control word of all signals is set, to carry out subsequent operation to storer to be controlled.
Wherein, described method also comprises:
A) after automatic detection failure, check the state of each register in described controller, obtain the reason of operation failure and position, according to the reason of described operation failure and the corresponding with it register value of position adjustment,
B) again automatic detection is started;
C) step is repeated a) and b), until automatic detection is correct.
Wherein, described method also comprises:
Judge that described controller is current and whether be in idle condition, if so, then described controller is switched to terminating resistor power down mode, otherwise, described controller is switched to duty.
Wherein, the step of carrying out automatic detection comprises the described time sequential routine to storer:
A certain piece of region of storer to be detected is read and write continuously;
Gather described read-write result as sampled data, analysis is carried out to described sampled data and obtains analysis result;
Automatically the synchronous adjustment of clock is completed according to analysis result.
Wherein, the described logic function corresponding with this type of memory at least comprises: the control model of storer, the drive level pattern of controller pin interface and driving force, amount of bandwidth, the stand-by period of memory span, read-write operation.
The controller that the application embodiment of the present invention provides and the method applying this controller, according to the first signal adjustment logic function register received, with the logic function that binding is corresponding with this type of memory, according to the secondary signal received, adjust the input/output port level mode of described controller and drive the ability of load, thus, the control that same controller is supported polytype storer is enable.Further, by carrying out automatic detection to the time sequential routine of storer, improve treatment effeciency and dirigibility.
In addition, owing to adding the error detection function to storer, when when not revising any hardware, the parameter of register being readjusted after automatic detection failure, thus realize the time delay readjusting each signal, can normally work to allow controller.
For portable electronic product, power consumption is less, and service time is longer.And the index that service time is normally very important.Therefore, make it enter battery saving mode when controller is in idle condition, like this, under the prerequisite meeting signal quality, reduce product power consumption as far as possible.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the controller architecture schematic diagram for storer according to the embodiment of the present invention;
Fig. 2 is the read operation sequential chart of ddr2 of the prior art;
Fig. 3 is the write operation sequential chart of ddr2 of the prior art;
Fig. 4 switches schematic diagram according to the state of the controller of the embodiment of the present invention;
Fig. 5 is the method flow schematic diagram of the application controller according to the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
See Fig. 1, it is the controller architecture schematic diagram for storer according to the embodiment of the present invention, this controller specifically comprises: type selection unit 101, input and output control unit 102, delay locked loop (dll, delay locked loop) control module 103, initialization unit 104 and compatible probe unit 105, wherein
Type selection unit 101, for the type according to the first signal behavior of receiving storer to be controlled, adjustment logic function register, to bind the logic function corresponding with this type of memory; Wherein, described first signal is the signal for adjusting controller logic function, as can be selected the memory span etc. of the model of storer to be controlled, data line bandwidth, read-write time delay, device to be controlled by register according to the first signal.Such as, table 1 is the schematic diagram of a register interface, can complete the basic parameter treating control store control by this register.
Table 1
The above-mentioned logic function corresponding with this type of memory at least comprises: the control model of storer, the drive level pattern of controller pin interface and driving force, amount of bandwidth, the stand-by period of memory span, read-write operation.
Above-mentioned storer to be controlled can be synchronous DRAM (Sdram, synchronousdynamic random access memory), mobile synchronous DRAM (Mobile sdram, mobile synchronous dynamic random access memory), double data rate random access memory (Ddr sdram, double data rate synchronous dynamic random access memory), 2nd generation double data rate random access memory (Ddr2 sdram, double data rate2 synchronousdynamic random access memory) or the 3rd generation double data rate random access memory (Ddr3sdram, double data rate3 synchronous dynamic random access memory).
Input and output control unit 102, for according to the secondary signal received, adjusts the input/output port level mode of described controller and drives the ability of load; Wherein, described secondary signal is the signal of input/output port level mode for adjusting controller and the ability driving load;
Table 2 is schematic diagram of a register interface, can be arranged the driving force of the IO interface of controller by this register by the mode of software.
Table 2
Dll control module 103, after the register parameters configuration in described controller, enable reset dll, after waiting for dll stable output, notice initialization unit;
Initialization unit 104, for after described initialize memory end of operation to be controlled, notifies compatible probe unit;
Compatible probe unit 105, for carrying out automatic detection to the time sequential routine of storer, after automatic detection correctly completes, arranges the control word of all signals, to carry out subsequent operation to storer to be controlled.
Above-mentioned compatible probe unit 105 can specifically comprise:
Read-write subelement, for reading and writing continuously a certain piece of region of storer to be detected;
Relatively subelement, for gathering described read-write result as sampled data, carrying out analysis to described sampled data and obtaining analysis result;
Adjustment arranges subelement, for automatically completing the synchronous adjustment of clock according to analysis result, after automatic detection correctly completes, arranges the control word of all signals, with the object that the clock edge reaching automatic calibration data sampling is synchronous.
The controller that the application embodiment of the present invention provides, by type selection unit according to the first signal adjustment logic function register received, with the logic function that binding is corresponding with this type of memory, by input and output control unit according to the secondary signal received, adjust the input/output port level mode of described controller and drive the ability of load, thus, the control that same controller is supported polytype storer is enable.Further, carry out automatic detection by compatible probe unit to the time sequential routine of storer, improve treatment effeciency and dirigibility.
In addition, for controller shown in Fig. 1, can also comprise:
Error-detecting adjustment unit (not shown), for after automatic detection failure, check the state of each register in described controller, obtain reason and the position of operation failure, according to the reason of described operation failure and the corresponding with it register value of position adjustment, notify compatible probe unit afterwards; Now, compatible probe unit also for according to the notice from error-detecting adjustment unit, starts automatic detection again.
Owing to adding the error detection function to storer, when when not revising any hardware, the parameter of register being readjusted after automatic detection failure, thus realizing the time delay readjusting each signal, can normally work to allow controller.
Controller shown in Fig. 1 can also comprise:
Whether status toggle unit (not shown), being in idle condition for judging that described controller is current, if so, then described controller being switched to terminating resistor power down mode, otherwise, described controller is switched to duty.
For portable electronic product, power consumption is less, and service time is longer.And the index that service time is normally very important.Therefore, make it enter battery saving mode when controller is in idle condition, like this, under the prerequisite meeting signal quality, reduce product power consumption as far as possible.
Below for storer to be controlled for ddr2, the present invention is elaborated again.
See Fig. 2 and Fig. 3, it is the reading and writing time sequential routine figure of ddr2 of the prior art.According to the protocol circuit of electronic engineering design development joint conference (JEDEC, Joint Electron Device Engineering Council) standard implementation sdram.In Fig. 2,3, " # " represents negative sign, and the difference not with " # " and band " # " is that they represent positive-negative relationship respectively, and such as, CK, CK# represent forward clock signal and negative sense clock signal respectively.Bi-directional data controls pin (DQS, Bi-directional Data Strobe), and DQS# represents positive and negative to latch signal respectively, and DM represents input data mask signal, and DQ represents data.In Fig. 2 and Fig. 3 represent the data transmitted, represent the data not needing to consider.
See Fig. 2 and Fig. 3, because ddr2 takes full advantage of the positive and negative edge of clock, and there is the structure of efficient double data rate (DDR) transmission.The problem of a multiplying power conversion is just there is like this at ddr2 controller end.The accuracy read and write data of ddr2 controller, just and dll have very large relation, existing when ddr2 write by controller at present, dll produces 4 fixing phase clock clk_0, clk_90, clk_180, clk_270 for the channel writing data provide multiplying power transform required for clock, when controller read data time, with clk_0 as a reference, dll carries out 90 ° of phase shifts to the sampling clock dqs sent by sdram, obtain a new clock DQS90, because dqs90 is in the center of data dq, thus obtain best Time Created and hold time, ensure that the correct sampling of DQ under clock DQS90.Existing controller also can when read data except adopt dll ensure data sampling accurately except, also can increase some fine setting time sequential routine circuit.
And the controller in the application is when writing data, adopt the frequency locking of dll, when ensureing to write data, the center alignment of clock dqs and dq of sampling.And when read data, adopt compatible detection (normal calibration) completely.Go to design because existing controller is all the basis of aliging based on data line (data line), and in fact, this is unpractiaca.
When reading and writing data, the reference clock that controller and ddr2 sdram work is all the clock (clock) provided of controller, but when writing data, the latch signal dqs of data dq, is provided by ddr2 controller.Therefore time data write by controller, just than being easier to, but when read data time, dqs and dq is that ddr2 storer is sent over there.And during read data, dqs and dq is edge alignment, therefore after sampling dqs, just with dll produce clk_90 ° for reference clock, the data sampling clock of controller inside is allowed just to align with the data dq center of input, can obtain one to be like this worth more accurately, certain precondition is that all data line align.By this method, can solve by the mode of software the clock signal problem that inconsistent and some quality of pcb length of arrangement wire are not good ddr2 storeies.
After ddr2 sdram initialization is completed, use the pattern of dll frequency locking, compatible detection (normal calibration) is adopted to detect, carry out read-write to a certain piece of continuum of ddr2 sdram storer exactly to compare, then according to the result compared, complete the synchronous adjustment of clock signal automatically, realize the step by step modulating of dll, synchronous with the clock edge reaching automatic calibration data sampling, realize the compatible different ddr2 of controller and relevant time sequential routine problem.
Still for ddr2, as shown in table 3 to the explanation of time in the description of ddr2:
Table 3
Based on parameter shown in table 3, the method for configuration operation sequential is as follows:
For ddr2-800 (5-5-5), in tRAS ddr2 specification, minimum time specification is 45ns, if ddr2 controller work clock is now mclk=100mhz, so the operating clock cycle of controller is Tclk=1/100mhz=10ns, Tras_cfg=45/10=5Tclk, wherein, the time delay that what Tras_cfg represented is between an activation command and another precharge command.So be 5 by control unit interface register bit [20:16] tRAS_CFG software merit rating, by this method, according to different work clock mclk and different sdram storer specifications, better compatibility and faster speed ability can be realized by software merit rating flexibly.Table 4 is that a kind of possible register value arranges illustration.
Table 4
When compatibility detection runs succeeded, the follow-up normal and correct operation to dram just can be realized.If compatible detection performs failure, so because add the error detection function to sdram, controller can according to related register state after operation failure, check reason and the position of operation failure, comprise any data lines, any root control line, and at certain stage produced problem of sequential of operation, can reflect in status register, to realize following the tracks of the debugging of sdram operation.And because controller of the present invention is the method adopting software design patterns, therefore can according to concrete signal sequence relation, their time delay is adjusted by the mode of software, and the relative timing relation between them, thus reach when not revising any hardware, controller can be worked normally.
After debugging, restart compatible detection, after compatibility detection, if still detect failure, then again carry out error-detecting, and re-start compatible detection after the adjustment, so repeat, detect successfully until compatible.
To in the debug process of controller, data collection problems must be related to.And for common storer, during data acquisition, remove the data-signal on image data line according to clock clock edge, for the storer of high frequency, data acquisition gathers according to the edge relation of data latch clock and data.Therefore, in this application, compatible detection mainly comprises following content:
(1) center of data latch clock whether corresponding data is judged.
(2) judge whether the edge of data latch clock image data is synchronized to inner clock.
(3), during windowing process data latch clock acquiescence high resistant, the ringing condition after receiving data is judged.
(4) calculate to send between read command how often obtain data, according to the interval time calculated and the current state of a control of threshold decision interval time that obtains in advance whether normal.
In above-mentioned 4 detections, the testing result of corresponding each link can be produced, this testing result is corresponding with the status information of position and this position, like this, the adjustment of being correlated with can be carried out according to position and corresponding status information, to adjust the position of detection next time, so repeat until automatic detection completes, thus realize the automatic adjustment of controller.
When using the storeies such as ddr, ddr2 sdram, the signal quality of controller in order to provide data to transmit, by increasing terminating resistor at controller and storer two ends, improves signal transmission quality in the mode of sacrificing power consumption.But for portable electronic product, power consumption is less, and service time is longer, and service time be a very important index.Therefore, under the future meeting signal quality, need to save power consumption as far as possible.Like this, the application uses automatic mode to switch duty and the battery saving mode of sdram, to reduce the power consumption of system, improves the service property (quality) of product.When controller enters data transfer operation, just exit battery saving mode, when the controller is idle, enter battery saving mode as termination battery saving mode, the termination relevant with storer with closing controller and other circuit, realization clearly can reduce the function of system power dissipation, especially higher to system dominant frequency, power consumption and the larger controller of thermal value are all good solutions.
See Fig. 4, it switches schematic diagram according to the state of the controller of the embodiment of the present invention.In figure, thick black solid line represents the step of automated execution, and thin black solid line is the step performed according to order.In Fig. 4, the implication of command abbreviation is as follows:
Ckel: clock is enable is low level, enters power down mode;
Ckeh: clock is enable is high level, enters power down mode;
Act: activation command;
Write: write order;
Read: read command;
Pr, pra: precharge, or all pieces of precharge;
Srf: enter self-refresh command;
Ref: refresh command automatically.
The embodiment of the present invention additionally provides a kind of method of application controller, see Fig. 5, specifically comprises:
Step 501, according to the type of the first signal behavior received storer to be controlled, adjustment logic function register, to bind the logic function corresponding with this type of memory; Wherein, described first signal is that logic function selects signal;
Step 502, according to the signal received, adjusts the input/output port level mode of described controller and drives the ability of load; Wherein, described secondary signal is the signal of input/output port level mode for adjusting controller and the ability driving load;
Step 503, after the register parameters configuration in described controller, enable reset dll, waits for dll stable output;
Step 504, carries out initialization operation to described storer to be controlled; Afterwards,
Step 505, carries out automatic detection to the time sequential routine of storer, after automatic detection correctly completes, arranges the control word of all signals, to carry out subsequent operation to storer to be controlled.
Said method can also comprise:
A) after automatic detection failure, check the state of each register in described controller, obtain the reason of operation failure and position, according to the reason of described operation failure and the corresponding with it register value of position adjustment,
B) again automatic detection is started;
C) step is repeated a) and b), until automatic detection is correct.
Said method can also comprise:
Judge that described controller is current and whether be in idle condition, if so, then described controller is switched to terminating resistor power down mode, otherwise, described controller is switched to duty.
The step that the above-mentioned time sequential routine to storer carries out automatic detection comprises:
A certain piece of region of storer to be detected is read and write continuously;
Gather described read-write result as sampled data, analysis is carried out to described sampled data and obtains analysis result;
Automatically the synchronous adjustment of clock is completed, with the object that the clock edge reaching automatic calibration data sampling is synchronous according to analysis result.
The above-mentioned logic function corresponding with this type of memory at least comprises: the control model of storer, the drive level pattern of controller pin interface and driving force, amount of bandwidth, the stand-by period of memory span, read-write operation.
The method that the application embodiment of the present invention provides, according to the first signal adjustment logic function register received, with the logic function that binding is corresponding with this type of memory, according to the secondary signal received, adjust the input/output port level mode of described controller and drive the ability of load, thus, the control that same controller is supported polytype storer is enable.Further, by carrying out automatic detection to the time sequential routine of storer, improve treatment effeciency and dirigibility.
In addition, owing to adding the error detection function to storer, when when not revising any hardware, the parameter of register being readjusted after automatic detection failure, thus realize the time delay readjusting each signal, can normally work to allow controller.
For portable electronic product, power consumption is less, and service time is longer.And the index that service time is normally very important.Therefore, make it enter battery saving mode when controller is in idle condition, like this, under the prerequisite meeting signal quality, reduce product power consumption as far as possible.
For embodiment of the method, because it is substantially similar to product embodiments, so description is fairly simple, relevant part illustrates see the part of embodiment of the method.
It should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
One of ordinary skill in the art will appreciate that all or part of step realized in said method embodiment is that the hardware that can carry out instruction relevant by program has come, described program can be stored in computer read/write memory medium, here the alleged storage medium obtained, as: ROM/RAM, magnetic disc, CD etc.
The foregoing is only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.All any amendments done within the spirit and principles in the present invention, equivalent replacement, improvement etc., be all included in protection scope of the present invention.

Claims (10)

1. for a controller for storer, it is characterized in that, comprising:
Type selection unit, for the type according to the first signal behavior of receiving storer to be controlled, adjustment logic function register, to bind the logic function corresponding with this type of memory;
Input and output control unit, for according to the secondary signal received, adjusts the input/output port level mode of described controller and drives the ability of load;
Delay locked loop dll control module, after the register parameters configuration in described controller, enable reset dll, after waiting for dll stable output, notice initialization unit;
Initialization unit, for after described initialize memory end of operation to be controlled, notifies compatible probe unit;
Compatible probe unit, for carrying out automatic detection to the time sequential routine of storer, after automatic detection correctly completes, arranges the control word of all signals, to carry out subsequent operation to storer to be controlled.
2. controller according to claim 1, is characterized in that, described controller also comprises:
Error-detecting adjustment unit, for after automatic detection failure, check the state of each register in described controller, obtain reason and the position of operation failure, according to the reason of described operation failure and the corresponding with it register value of position adjustment, notify compatible probe unit afterwards;
Described compatible probe unit, also for according to the notice from error-detecting adjustment unit, starts automatic detection again.
3. controller according to claim 1 and 2, is characterized in that, described controller also comprises:
Whether status toggle unit, being in idle condition for judging that described controller is current, if so, then described controller being switched to terminating resistor power down mode, otherwise, described controller is switched to duty.
4. controller according to claim 1, is characterized in that, described compatible probe unit comprises:
Read-write subelement, for reading and writing continuously a certain piece of region of storer to be detected;
Relatively subelement, for gathering described read-write result as sampled data, carrying out analysis to described sampled data and obtaining analysis result;
Adjustment arranges subelement, for automatically completing the synchronous adjustment of clock according to analysis result, after automatic detection correctly completes, arranges the control word of all signals, with the object that the clock edge reaching automatic calibration data sampling is synchronous.
5. controller according to claim 1, it is characterized in that, the described logic function corresponding with this type of memory at least comprises: the control model of storer, the drive level pattern of controller pin interface and driving force, amount of bandwidth, the stand-by period of memory span, read-write operation.
6. a method for application controller, is characterized in that, comprising:
According to the type of the first signal behavior received storer to be controlled, adjustment logic function register, to bind the logic function corresponding with this type of memory; Wherein, described first signal is that logic function selects signal;
According to the secondary signal received, adjust the input/output port level mode of described controller and drive the ability of load; Wherein, described secondary signal is the signal of input/output port level mode for adjusting controller and the ability driving load;
After register parameters configuration in described controller, enable reset delay locked loop dll, waits for dll stable output; Afterwards,
Initialization operation is carried out to described storer to be controlled;
Automatic detection is carried out to the time sequential routine of storer, after automatic detection correctly completes, the control word of all signals is set, to carry out subsequent operation to storer to be controlled.
7. method according to claim 6, is characterized in that, described method also comprises:
A) after automatic detection failure, check the state of each register in described controller, obtain the reason of operation failure and position, according to the reason of described operation failure and the corresponding with it register value of position adjustment,
B) again automatic detection is started;
C) step is repeated a) and b), until automatic detection is correct.
8. the method according to claim 6 or 7, is characterized in that, described method also comprises:
Judge that described controller is current and whether be in idle condition, if so, then described controller is switched to terminating resistor power down mode, otherwise, described controller is switched to duty.
9. method according to claim 6, is characterized in that, the step that the described time sequential routine to storer carries out automatic detection comprises:
A certain piece of region of storer to be detected is read and write continuously;
Gather described read-write result as sampled data, analysis is carried out to described sampled data and obtains analysis result;
Automatically the synchronous adjustment of clock is completed according to analysis result.
10. method according to claim 6, it is characterized in that, the described logic function corresponding with this type of memory at least comprises: the control model of storer, the drive level pattern of controller pin interface and driving force, amount of bandwidth, the stand-by period of memory span, read-write operation.
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